Couple improvements for Tegra clk driver
Subsystems (3)
v3 cover Couple improvements for Tegra clk driver
This series fixes couple minor standalone problems of the Tegra clk driver.
Changelog:
v3: - Added acks from Thierry Reding that he gave to v2.
- Added new patch "clk: tegra: Don't allow zero clock rate for PLLs".
v2: - Added these new patches:
clk: tegra: Halve SCLK rate on Tegra20
MAINTAINERS: Hand Tegra clk driver to Jon and Thierry
v1: - Collected clk patches into a single series.
Dmitry Osipenko (6):
clk: tegra30: Use 300MHz for video decoder by default
clk: tegra: Fix refcounting of gate clocks
clk: tegra: Ensure that PLLU configuration is applied properly
clk: tegra: Halve SCLK rate on Tegra20
MAINTAINERS: Hand Tegra clk driver to Jon and Thierry
clk: tegra: Don't allow zero clock rate for PLLs
CREDITS | 6 +++ MAINTAINERS | 4 +- drivers/clk/tegra/clk-periph-gate.c | 72 +++++++++++++++++++---------- drivers/clk/tegra/clk-periph.c | 11 +++++ drivers/clk/tegra/clk-pll.c | 12 +++-- drivers/clk/tegra/clk-tegra20.c | 6 +-- drivers/clk/tegra/clk-tegra30.c | 2 +- 7 files changed, 77 insertions(+), 36 deletions(-)
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2.29.2
PATCH v3 1/6 clk: tegra30: Use 300MHz for video decoder by default
The 600MHz is a too high clock rate for some SoC versions for the video decoder hardware and this may cause stability issues. Use 300MHz for the video decoder by default, which is supported by all hardware versions.
--- drivers/clk/tegra/clk-tegra30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/tegra/clk-tegra30.c +1 -1
@@ -1245,7 +1245,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, - { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 600000000, 0 }, + { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
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2.29.2
PATCH v3 2/6 clk: tegra: Fix refcounting of gate clocks
In reply to Dmitry OsipenkoThe refcounting of the gate clocks has a bug causing the enable_refcnt to underflow when unused clocks are disabled. This happens because clk provider erroneously bumps the refcount if clock is enabled at a boot time, which it shouldn't be doing, and it does this only for the gate clocks, while peripheral clocks are using the same gate ops and the peripheral clocks are missing the initial bump. Hence the refcount of the peripheral clocks is 0 when unused clocks are disabled and then the counter is decremented further by the gate ops, causing the integer underflow.
Fix this problem by removing the erroneous bump and by implementing the disable_unused() callback, which disables the unused gates properly.
The visible effect of the bug is such that the unused clocks are never gated if a loaded kernel module grabs the unused clocks and starts to use them. In practice this shouldn't cause any real problems for the drivers and boards supported by the kernel today.
--- drivers/clk/tegra/clk-periph-gate.c | 72 +++++++++++++++++++---------- drivers/clk/tegra/clk-periph.c | 11 +++++ 2 files changed, 58 insertions(+), 25 deletions(-)
drivers/clk/tegra/clk-periph-gate.c +47 -25
@@ -48,18 +48,9 @@ static int clk_periph_is_enabled(struct clk_hw *hw)return state; } -static int clk_periph_enable (struct clk_hw *hw) +static void clk_periph_enable_locked (struct clk_hw *hw) {struct tegra_clk_periph_gate *gate =to_clk_periph_gate (hw); -unsigned long flags =0 ; - -spin_lock_irqsave (&periph_ref_lock, flags); - - gate->enable_refcnt[gate->clk_num]++; -if (gate->enable_refcnt[gate->clk_num] >1 ) { -spin_unlock_irqrestore (&periph_ref_lock, flags); -return 0 ; - }write_enb_set (periph_clk_to_bit (gate), gate);udelay (2 );
@@ -78,6 +69,32 @@ static int clk_periph_enable(struct clk_hw *hw)udelay (1 );writel_relaxed (0 , gate->clk_base +LVL2_CLK_GATE_OVRE ); } +} + +static void clk_periph_disable_locked (struct clk_hw *hw) +{ +struct tegra_clk_periph_gate *gate =to_clk_periph_gate (hw); + +/* +* If peripheral is in the APB bus then read the APB bus to +* flush the write operation in apb bus. This will avoid the +* peripheral access after disabling clock +*/ +if (gate->flags &TEGRA_PERIPH_ON_APB ) +tegra_read_chipid (); + +write_enb_clr (periph_clk_to_bit (gate), gate); +} + +static int clk_periph_enable (struct clk_hw *hw) +{ +struct tegra_clk_periph_gate *gate =to_clk_periph_gate (hw); +unsigned long flags =0 ; + +spin_lock_irqsave (&periph_ref_lock, flags); + +if (!gate->enable_refcnt[gate->clk_num]++) +clk_periph_enable_locked (hw);spin_unlock_irqrestore (&periph_ref_lock, flags);
@@ -91,21 +108,28 @@ static void clk_periph_disable(struct clk_hw *hw)spin_lock_irqsave (&periph_ref_lock, flags); - gate->enable_refcnt[gate->clk_num]--; -if (gate->enable_refcnt[gate->clk_num] >0 ) { -spin_unlock_irqrestore (&periph_ref_lock, flags); -return ; - } +WARN_ON (!gate->enable_refcnt[gate->clk_num]); + +if (gate->enable_refcnt[gate->clk_num]-- ==1 ) +clk_periph_disable_locked (hw); + +spin_unlock_irqrestore (&periph_ref_lock, flags); +} + +static void clk_periph_disable_unused (struct clk_hw *hw) +{ +struct tegra_clk_periph_gate *gate =to_clk_periph_gate (hw); +unsigned long flags =0 ; + +spin_lock_irqsave (&periph_ref_lock, flags);/* -* If peripheral is in the APB bus then read the APB bus to -* flush the write operation in apb bus. This will avoid the -* peripheral access after disabling clock +* Some clocks are duplicated and some of them are marked as critical, +* like fuse and fuse_burn for example, thus the enable_refcnt will +* be non-zero here id the "unused" duplicate is disabled by CCF. */ -if (gate->flags &TEGRA_PERIPH_ON_APB ) -tegra_read_chipid (); - -write_enb_clr (periph_clk_to_bit (gate), gate); +if (!gate->enable_refcnt[gate->clk_num]) +clk_periph_disable_locked (hw);spin_unlock_irqrestore (&periph_ref_lock, flags); }
@@ -114,6 +138,7 @@ const struct clk_ops tegra_clk_periph_gate_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, }; struct clk *tegra_clk_register_periph_gate(const char *name,
@@ -148,9 +173,6 @@ struct clk *tegra_clk_register_periph_gate(const char *name, gate->enable_refcnt = enable_refcnt; gate->regs = pregs; -if (read_enb (gate) &periph_clk_to_bit (gate)) - enable_refcnt[clk_num]++; -/* Data in .init is copied by clk_register(), so stack variable OK */ gate->hw.init = &init;
drivers/clk/tegra/clk-periph.c +11 -0
@@ -100,6 +100,15 @@ static void clk_periph_disable(struct clk_hw *hw) gate_ops->disable (gate_hw); } +static void clk_periph_disable_unused (struct clk_hw *hw) +{ +struct tegra_clk_periph *periph =to_clk_periph (hw); +const struct clk_ops *gate_ops = periph->gate_ops; +struct clk_hw *gate_hw = &periph->gate.hw; + + gate_ops->disable_unused (gate_hw); +} +static void clk_periph_restore_context (struct clk_hw *hw) {struct tegra_clk_periph *periph =to_clk_periph (hw);
@@ -126,6 +135,7 @@ const struct clk_ops tegra_clk_periph_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, .restore_context = clk_periph_restore_context, };
@@ -135,6 +145,7 @@ static const struct clk_ops tegra_clk_periph_nodiv_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, .restore_context = clk_periph_restore_context, };
Signature · 1 line
2.29.2
PATCH v3 3/6 clk: tegra: Ensure that PLLU configuration is applied properly
In reply to Dmitry OsipenkoThe PLLU (USB) consists of the PLL configuration itself and configuration of the PLLU outputs. The PLLU programming is inconsistent on T30 vs T114, where T114 immediately bails out if PLLU is enabled and T30 re-enables a potentially already enabled PLL (left after bootloader) and then fully reprograms it, which could be unsafe to do. The correct way should be to skip enabling of the PLL if it's already enabled and then apply configuration to the outputs. This patch doesn't fix any known problems, it's a minor improvement.
--- drivers/clk/tegra/clk-pll.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)
drivers/clk/tegra/clk-pll.c +4 -5
@@ -1131,7 +1131,8 @@ static int clk_pllu_enable(struct clk_hw *hw)if (pll->lock)spin_lock_irqsave (pll->lock, flags); -_clk_pll_enable (hw); +if (!clk_pll_is_enabled (hw)) +_clk_pll_enable (hw); ret =clk_pll_wait_for_lock (pll);if (ret <0 )
@@ -1748,15 +1749,13 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw)return -EINVAL ; } -if (clk_pll_is_enabled (hw)) -return 0 ; - input_rate =clk_hw_get_rate (__clk_get_hw (osc));if (pll->lock)spin_lock_irqsave (pll->lock, flags); -_clk_pll_enable (hw); +if (!clk_pll_is_enabled (hw)) +_clk_pll_enable (hw); ret =clk_pll_wait_for_lock (pll);if (ret <0 )
Signature · 1 line
2.29.2
PATCH v3 4/6 clk: tegra: Halve SCLK rate on Tegra20
In reply to Dmitry OsipenkoHigher SCLK rates on Tegra20 require high core voltage. The higher clock rate may have a positive performance effect only for AHB DMA transfers and AVP CPU, but both aren't used by upstream kernel at all. Halve SCLK rate on Tegra20 in order to remove the high core voltage requirement.
--- drivers/clk/tegra/clk-tegra20.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/clk/tegra/clk-tegra20.c +3 -3
@@ -1021,9 +1021,9 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 }, - { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, - { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 }, - { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, + { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, + { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 120000000, 0 }, + { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 }, { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 }, { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
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2.29.2
PATCH v3 5/6 MAINTAINERS: Hand Tegra clk driver to Jon and Thierry
In reply to Dmitry OsipenkoPeter and Prashant aren't actively maintaining Tegra clock driver anymore. Jonathan and Thierry will pick up maintaining of the driver from now on.
--- CREDITS | 6 ++++++ MAINTAINERS | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-)
CREDITS +6 -0
@@ -1250,6 +1250,10 @@ S: 29 Duchifat St. S: Ra'anana 4372029 S: Israel +N: Prashant Gaikwad +E: [email protected] +D: Maintained NVIDIA Tegra clock driver + N: Kumar Gala E: [email protected] D: Embedded PowerPC 6xx/7xx/74xx/82xx/83xx/85xx support
@@ -3387,7 +3391,9 @@ E: D: Macintosh IDE Driver N: Peter De Schrijver +E: [email protected] E: [email protected] +D: Maintained NVIDIA Tegra clock driver D: Mitsumi CD-ROM driver patches March version S: Molenbaan 29 S: B2240 Zandhoven
MAINTAINERS +2 -2
@@ -17587,8 +17587,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git N: [^a-z]tegra TEGRA CLOCK DRIVER -M: Peter De Schrijver <[email protected]> -M: Prashant Gaikwad <[email protected]> +M: Jonathan Hunter <[email protected]> +M: Thierry Reding <[email protected]> S: Supported F: drivers/clk/tegra/
Signature · 1 line
2.29.2
PATCH v3 6/6 clk: tegra: Don't allow zero clock rate for PLLs
In reply to Dmitry OsipenkoZero clock rate doesn't make sense for PLLs and tegra-clk driver enters into infinite loop on trying to calculate PLL parameters for zero rate. Make code to error out if requested rate is zero.
Originally this trouble was found by Robert Yang while he was trying to bring up upstream kernel on Samsung Galaxy Tab, which happened due to a bug in Tegra DRM driver that erroneously sets PLL rate to zero. This issues came over again recently during of kernel bring up on ASUS TF700T.
--- drivers/clk/tegra/clk-pll.c | 3 +++ 1 file changed, 3 insertions(+)
drivers/clk/tegra/clk-pll.c +3 -0
@@ -558,6 +558,9 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,u32 p_div =0 ;int ret; +if (!rate) +return -EINVAL ; +switch (parent_rate) {case 12000000 :case 26000000 :
Signature · 1 line
2.29.2