Couple improvements for Tegra clk driver
v7 cover Couple improvements for Tegra clk driver
This series fixes couple minor standalone problems of the Tegra clk driver and adds new features.
Changelog:
v7: - Added r-b from Rob Herring to the schema patch which he gave to v6.
- Dropped the MAINTAINERS-update patch. Previously Peter said on IRC that he doesn't have time on the tegra-clk driver anymore and approved the patch, but then he refused to ack the v6 patch, saying that he is not reading mailing lists. So I don't feel comfortable with that patch. Peter could send it by himself if will be necessary.
- Added these new patches:
clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
clk: tegra: Mark external clocks as not having reset control
I sent out the new Tegra30 thermal sensor driver and now CPU clock could be throttled by the sensor hardware [1]. The first patch adds support for reporting of the throttled frequency properly.
[1] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=243126
During of debugging sound issues of Asus Transformer devices, I noticed that the external clocks are missing the no-reset flag. The second patch fixes it.
v6: - Made a small improvement and corrected a typo in patch
"Fix refcounting of gate clocks" that were spotted by Michał Mirosław.
v5: - Corrected example in the schema binding to silence dt_binding_check
warning.
- The Tegra124 binding is factored out into standalone binding since Tegra124 has properties that aren't used by other SoCs and I couldn't figure out how to make them conditional in schema.
v4: - Added new patch that converts DT bindings to schema.
v3: - Added acks from Thierry Reding that he gave to v2.
- Added new patch "clk: tegra: Don't allow zero clock rate for PLLs".
v2: - Added these new patches:
clk: tegra: Halve SCLK rate on Tegra20
MAINTAINERS: Hand Tegra clk driver to Jon and Thierry
v1: - Collected clk patches into a single series.
Dmitry Osipenko (8):
clk: tegra30: Use 300MHz for video decoder by default
clk: tegra: Fix refcounting of gate clocks
clk: tegra: Ensure that PLLU configuration is applied properly
clk: tegra: Halve SCLK rate on Tegra20
clk: tegra: Don't allow zero clock rate for PLLs
clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
clk: tegra: Mark external clocks as not having reset control
dt-bindings: clock: tegra: Convert to schema
.../bindings/clock/nvidia,tegra114-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra124-car.txt | 107 ---------------- .../bindings/clock/nvidia,tegra124-car.yaml | 115 ++++++++++++++++++ .../bindings/clock/nvidia,tegra20-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra20-car.yaml | 69 +++++++++++ .../bindings/clock/nvidia,tegra210-car.txt | 56 --------- .../bindings/clock/nvidia,tegra30-car.txt | 63 ---------- drivers/clk/tegra/clk-periph-gate.c | 72 +++++++---- drivers/clk/tegra/clk-periph.c | 11 ++ drivers/clk/tegra/clk-pll.c | 12 +- drivers/clk/tegra/clk-tegra-periph.c | 6 +- drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++- drivers/clk/tegra/clk-tegra20.c | 6 +- drivers/clk/tegra/clk-tegra30.c | 4 +- 14 files changed, 271 insertions(+), 392 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
Signature · 1 line
2.30.2
PATCH v7 1/8 clk: tegra30: Use 300MHz for video decoder by default
The 600MHz is a too high clock rate for some SoC versions for the video decoder hardware and this may cause stability issues. Use 300MHz for the video decoder by default, which is supported by all hardware versions.
--- drivers/clk/tegra/clk-tegra30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/tegra/clk-tegra30.c +1 -1
@@ -1245,7 +1245,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, - { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 600000000, 0 }, + { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
Signature · 1 line
2.30.2
PATCH v7 2/8 clk: tegra: Fix refcounting of gate clocks
In reply to Dmitry OsipenkoThe refcounting of the gate clocks has a bug causing the enable_refcnt to underflow when unused clocks are disabled. This happens because clk provider erroneously bumps the refcount if clock is enabled at a boot time, which it shouldn't be doing, and it does this only for the gate clocks, while peripheral clocks are using the same gate ops and the peripheral clocks are missing the initial bump. Hence the refcount of the peripheral clocks is 0 when unused clocks are disabled and then the counter is decremented further by the gate ops, causing the integer underflow.
Fix this problem by removing the erroneous bump and by implementing the disable_unused() callback, which disables the unused gates properly.
The visible effect of the bug is such that the unused clocks are never gated if a loaded kernel module grabs the unused clocks and starts to use them. In practice this shouldn't cause any real problems for the drivers and boards supported by the kernel today.
--- drivers/clk/tegra/clk-periph-gate.c | 72 +++++++++++++++++++---------- drivers/clk/tegra/clk-periph.c | 11 +++++ 2 files changed, 58 insertions(+), 25 deletions(-)
drivers/clk/tegra/clk-periph-gate.c +47 -25
@@ -48,18 +48,9 @@ static int clk_periph_is_enabled(struct clk_hw *hw)return state; } -static int clk_periph_enable (struct clk_hw *hw) +static void clk_periph_enable_locked (struct clk_hw *hw) {struct tegra_clk_periph_gate *gate =to_clk_periph_gate (hw); -unsigned long flags =0 ; - -spin_lock_irqsave (&periph_ref_lock, flags); - - gate->enable_refcnt[gate->clk_num]++; -if (gate->enable_refcnt[gate->clk_num] >1 ) { -spin_unlock_irqrestore (&periph_ref_lock, flags); -return 0 ; - }write_enb_set (periph_clk_to_bit (gate), gate);udelay (2 );
@@ -78,6 +69,32 @@ static int clk_periph_enable(struct clk_hw *hw)udelay (1 );writel_relaxed (0 , gate->clk_base +LVL2_CLK_GATE_OVRE ); } +} + +static void clk_periph_disable_locked (struct clk_hw *hw) +{ +struct tegra_clk_periph_gate *gate =to_clk_periph_gate (hw); + +/* +* If peripheral is in the APB bus then read the APB bus to +* flush the write operation in apb bus. This will avoid the +* peripheral access after disabling clock +*/ +if (gate->flags &TEGRA_PERIPH_ON_APB ) +tegra_read_chipid (); + +write_enb_clr (periph_clk_to_bit (gate), gate); +} + +static int clk_periph_enable (struct clk_hw *hw) +{ +struct tegra_clk_periph_gate *gate =to_clk_periph_gate (hw); +unsigned long flags =0 ; + +spin_lock_irqsave (&periph_ref_lock, flags); + +if (!gate->enable_refcnt[gate->clk_num]++) +clk_periph_enable_locked (hw);spin_unlock_irqrestore (&periph_ref_lock, flags);
@@ -91,21 +108,28 @@ static void clk_periph_disable(struct clk_hw *hw)spin_lock_irqsave (&periph_ref_lock, flags); - gate->enable_refcnt[gate->clk_num]--; -if (gate->enable_refcnt[gate->clk_num] >0 ) { -spin_unlock_irqrestore (&periph_ref_lock, flags); -return ; - } +WARN_ON (!gate->enable_refcnt[gate->clk_num]); + +if (--gate->enable_refcnt[gate->clk_num] ==0 ) +clk_periph_disable_locked (hw); + +spin_unlock_irqrestore (&periph_ref_lock, flags); +} + +static void clk_periph_disable_unused (struct clk_hw *hw) +{ +struct tegra_clk_periph_gate *gate =to_clk_periph_gate (hw); +unsigned long flags =0 ; + +spin_lock_irqsave (&periph_ref_lock, flags);/* -* If peripheral is in the APB bus then read the APB bus to -* flush the write operation in apb bus. This will avoid the -* peripheral access after disabling clock +* Some clocks are duplicated and some of them are marked as critical, +* like fuse and fuse_burn for example, thus the enable_refcnt will +* be non-zero here if the "unused" duplicate is disabled by CCF. */ -if (gate->flags &TEGRA_PERIPH_ON_APB ) -tegra_read_chipid (); - -write_enb_clr (periph_clk_to_bit (gate), gate); +if (!gate->enable_refcnt[gate->clk_num]) +clk_periph_disable_locked (hw);spin_unlock_irqrestore (&periph_ref_lock, flags); }
@@ -114,6 +138,7 @@ const struct clk_ops tegra_clk_periph_gate_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, }; struct clk *tegra_clk_register_periph_gate(const char *name,
@@ -148,9 +173,6 @@ struct clk *tegra_clk_register_periph_gate(const char *name, gate->enable_refcnt = enable_refcnt; gate->regs = pregs; -if (read_enb (gate) &periph_clk_to_bit (gate)) - enable_refcnt[clk_num]++; -/* Data in .init is copied by clk_register(), so stack variable OK */ gate->hw.init = &init;
drivers/clk/tegra/clk-periph.c +11 -0
@@ -100,6 +100,15 @@ static void clk_periph_disable(struct clk_hw *hw) gate_ops->disable (gate_hw); } +static void clk_periph_disable_unused (struct clk_hw *hw) +{ +struct tegra_clk_periph *periph =to_clk_periph (hw); +const struct clk_ops *gate_ops = periph->gate_ops; +struct clk_hw *gate_hw = &periph->gate.hw; + + gate_ops->disable_unused (gate_hw); +} +static void clk_periph_restore_context (struct clk_hw *hw) {struct tegra_clk_periph *periph =to_clk_periph (hw);
@@ -126,6 +135,7 @@ const struct clk_ops tegra_clk_periph_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, .restore_context = clk_periph_restore_context, };
@@ -135,6 +145,7 @@ static const struct clk_ops tegra_clk_periph_nodiv_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, .restore_context = clk_periph_restore_context, };
Signature · 1 line
2.30.2
PATCH v7 3/8 clk: tegra: Ensure that PLLU configuration is applied properly
In reply to Dmitry OsipenkoThe PLLU (USB) consists of the PLL configuration itself and configuration of the PLLU outputs. The PLLU programming is inconsistent on T30 vs T114, where T114 immediately bails out if PLLU is enabled and T30 re-enables a potentially already enabled PLL (left after bootloader) and then fully reprograms it, which could be unsafe to do. The correct way should be to skip enabling of the PLL if it's already enabled and then apply configuration to the outputs. This patch doesn't fix any known problems, it's a minor improvement.
--- drivers/clk/tegra/clk-pll.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)
drivers/clk/tegra/clk-pll.c +4 -5
@@ -1131,7 +1131,8 @@ static int clk_pllu_enable(struct clk_hw *hw)if (pll->lock)spin_lock_irqsave (pll->lock, flags); -_clk_pll_enable (hw); +if (!clk_pll_is_enabled (hw)) +_clk_pll_enable (hw); ret =clk_pll_wait_for_lock (pll);if (ret <0 )
@@ -1748,15 +1749,13 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw)return -EINVAL ; } -if (clk_pll_is_enabled (hw)) -return 0 ; - input_rate =clk_hw_get_rate (__clk_get_hw (osc));if (pll->lock)spin_lock_irqsave (pll->lock, flags); -_clk_pll_enable (hw); +if (!clk_pll_is_enabled (hw)) +_clk_pll_enable (hw); ret =clk_pll_wait_for_lock (pll);if (ret <0 )
Signature · 1 line
2.30.2
PATCH v7 4/8 clk: tegra: Halve SCLK rate on Tegra20
In reply to Dmitry OsipenkoHigher SCLK rates on Tegra20 require high core voltage. The higher clock rate may have a positive performance effect only for AHB DMA transfers and AVP CPU, but both aren't used by upstream kernel at all. Halve SCLK rate on Tegra20 in order to remove the high core voltage requirement.
--- drivers/clk/tegra/clk-tegra20.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/clk/tegra/clk-tegra20.c +3 -3
@@ -1021,9 +1021,9 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 }, - { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, - { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 }, - { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, + { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, + { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 120000000, 0 }, + { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 }, { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 }, { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
Signature · 1 line
2.30.2
PATCH v7 5/8 clk: tegra: Don't allow zero clock rate for PLLs
In reply to Dmitry OsipenkoZero clock rate doesn't make sense for PLLs and tegra-clk driver enters into infinite loop on trying to calculate PLL parameters for zero rate. Make code to error out if requested rate is zero.
Originally this trouble was found by Robert Yang while he was trying to bring up upstream kernel on Samsung Galaxy Tab, which happened due to a bug in Tegra DRM driver that erroneously sets PLL rate to zero. This issues came over again recently during of kernel bring up on ASUS TF700T.
--- drivers/clk/tegra/clk-pll.c | 3 +++ 1 file changed, 3 insertions(+)
drivers/clk/tegra/clk-pll.c +3 -0
@@ -558,6 +558,9 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,u32 p_div =0 ;int ret; +if (!rate) +return -EINVAL ; +switch (parent_rate) {case 12000000 :case 26000000 :
Signature · 1 line
2.30.2
PATCH v7 6/8 clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
In reply to Dmitry OsipenkoCheck whether thermal DIV2 throttle is active in order to report the CPU frequency properly. This very useful for userspace tools like cpufreq-info which show actual frequency asserted from hardware.
--- drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++++++++++++++-- drivers/clk/tegra/clk-tegra30.c | 2 +- 2 files changed, 15 insertions(+), 3 deletions(-)
drivers/clk/tegra/clk-tegra-super-cclk.c +14 -2
@@ -25,6 +25,8 @@#define SUPER_CDIV_ENB BIT(31) +#define TSENSOR_SLOWDOWN BIT(23) +static struct tegra_clk_super_mux *cclk_super;static bool cclk_on_pllx;
@@ -47,10 +49,20 @@ static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate,static unsigned long cclk_super_recalc_rate (struct clk_hw *hw,unsigned long parent_rate) { +struct tegra_clk_super_mux *super =to_clk_super_mux (hw); +u32 val =readl_relaxed (super->reg); +unsigned int div2; + +/* check whether thermal throttling is active */ +if (val &TSENSOR_SLOWDOWN ) + div2 =2 ; +else + div2 =1 ; +if (cclk_super_get_parent (hw) ==PLLX_INDEX ) -return parent_rate; +return parent_rate / div2; -return tegra_clk_super_ops.recalc_rate (hw, parent_rate); +return tegra_clk_super_ops.recalc_rate (hw, parent_rate) / div2; } static int cclk_super_determine_rate(struct clk_hw *hw,
drivers/clk/tegra/clk-tegra30.c +1 -1
@@ -930,7 +930,7 @@ static void __init tegra30_super_clk_init(void)/* CCLKG */ clk =tegra_clk_register_super_cclk ("cclk_g" , cclk_g_parents,ARRAY_SIZE (cclk_g_parents), -CLK_SET_RATE_PARENT , +CLK_SET_RATE_PARENT |CLK_GET_RATE_NOCACHE , clk_base +CCLKG_BURST_POLICY ,0 ,NULL ); clks[TEGRA30_CLK_CCLK_G ] = clk;
Signature · 1 line
2.30.2
Re: [PATCH v7 6/8] clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
Quoted 34 lines · Dmitry Osipenko
Check whether thermal DIV2 throttle is active in order to report the CPU frequency properly. This very useful for userspace tools like cpufreq-info which show actual frequency asserted from hardware.
Signed-off-by Dmitry Osipenko <[email protected]>--- drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++++++++++++++-- drivers/clk/tegra/clk-tegra30.c | 2 +- 2 files changed, 15 insertions(+), 3 deletions(-)drivers/clk/tegra/clk-tegra-super-cclk.c +9
-0@@ -25,6 +25,8 @@#define SUPER_CDIV_ENB BIT(31) +#define TSENSOR_SLOWDOWN BIT(23) +static struct tegra_clk_super_mux *cclk_super;static bool cclk_on_pllx;@@ -47,10 +49,20 @@ static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate,static unsigned long cclk_super_recalc_rate (struct clk_hw *hw,unsigned long parent_rate) { +struct tegra_clk_super_mux *super =to_clk_super_mux (hw); +u32 val =readl_relaxed (super->reg); +unsigned int div2; + +/* check whether thermal throttling is active */ +if (val &TSENSOR_SLOWDOWN ) + div2 =2 ;
drivers/clk/tegra/clk-tegra-super-cclk.c static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, · line 66
Quoted 10 lines
drivers/clk/tegra/clk-tegra-super-cclk.c +5
-2+else + div2 =1 ; +if (cclk_super_get_parent (hw) ==PLLX_INDEX ) -return parent_rate; +return parent_rate / div2; -return tegra_clk_super_ops.recalc_rate (hw, parent_rate); +return tegra_clk_super_ops.recalc_rate (hw, parent_rate) / div2; }
Could you check if the compiler can optimize out the division? I know this is a slow path, but nevertheless the 'shr' version would be the same amount of source code.
Best Regrads
Michał Mirosław
Re: [PATCH v7 6/8] clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
11.05.2021 17:41, Michał Mirosław пишет:
Quoted 42 lines · Dmitry Osipenko
Quoted 41 lines
Check whether thermal DIV2 throttle is active in order to report the CPU frequency properly. This very useful for userspace tools like cpufreq-info which show actual frequency asserted from hardware.
Signed-off-by Dmitry Osipenko <[email protected]>--- drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++++++++++++++-- drivers/clk/tegra/clk-tegra30.c | 2 +- 2 files changed, 15 insertions(+), 3 deletions(-)drivers/clk/tegra/clk-tegra-super-cclk.c +13
-1@@ -25,6 +25,8 @@#define SUPER_CDIV_ENB BIT(31) +#define TSENSOR_SLOWDOWN BIT(23) +static struct tegra_clk_super_mux *cclk_super;static bool cclk_on_pllx;@@ -47,10 +49,20 @@ static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate,static unsigned long cclk_super_recalc_rate (struct clk_hw *hw,unsigned long parent_rate) { +struct tegra_clk_super_mux *super =to_clk_super_mux (hw); +u32 val =readl_relaxed (super->reg); +unsigned int div2; + +/* check whether thermal throttling is active */ +if (val &TSENSOR_SLOWDOWN ) + div2 =2 ; +else + div2 =1 ; +if (cclk_super_get_parent (hw) ==PLLX_INDEX ) -return parent_rate; +return parent_rate / div2;
Quoted 7 lines
drivers/clk/tegra/clk-tegra-super-cclk.c static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, · line 66
Quoted 3 lines
drivers/clk/tegra/clk-tegra-super-cclk.c +1
-1-return tegra_clk_super_ops.recalc_rate (hw, parent_rate); +return tegra_clk_super_ops.recalc_rate (hw, parent_rate) / div2; }Could you check if the compiler can optimize out the division? I know this is a slow path, but nevertheless the 'shr' version would be the same amount of source code.
Hello Michał,
GCC can't optimize that division. I'll wait for more comments and then update this patch in v8 with yours suggestion. Thank you for taking a look at the patches.
PATCH v7 7/8 clk: tegra: Mark external clocks as not having reset control
In reply to Dmitry OsipenkoThe external clocks don't have reset bits as they don't belong to any specific hardware unit. Mark them as not having reset control for consistency.
--- drivers/clk/tegra/clk-tegra-periph.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/clk/tegra/clk-tegra-periph.c +3 -3
@@ -712,9 +712,9 @@ static struct tegra_periph_init_data periph_clks[] = {MUX8 ("ndflash" , mux_pllp_pllc2_c_c3_pllm_clkm,CLK_SOURCE_NDFLASH ,13 ,TEGRA_PERIPH_ON_APB , tegra_clk_ndflash_8),MUX8 ("ndspeed" , mux_pllp_pllc2_c_c3_pllm_clkm,CLK_SOURCE_NDSPEED ,80 ,TEGRA_PERIPH_ON_APB , tegra_clk_ndspeed_8),MUX8 ("hdmi" , mux_pllp_pllm_plld_plla_pllc_plld2_clkm,CLK_SOURCE_HDMI ,51 ,0 , tegra_clk_hdmi), -MUX8 ("extern1" , mux_plla_clk32_pllp_clkm_plle,CLK_SOURCE_EXTERN1 ,120 ,0 , tegra_clk_extern1), -MUX8 ("extern2" , mux_plla_clk32_pllp_clkm_plle,CLK_SOURCE_EXTERN2 ,121 ,0 , tegra_clk_extern2), -MUX8 ("extern3" , mux_plla_clk32_pllp_clkm_plle,CLK_SOURCE_EXTERN3 ,122 ,0 , tegra_clk_extern3), +MUX8 ("extern1" , mux_plla_clk32_pllp_clkm_plle,CLK_SOURCE_EXTERN1 ,120 ,TEGRA_PERIPH_NO_RESET , tegra_clk_extern1), +MUX8 ("extern2" , mux_plla_clk32_pllp_clkm_plle,CLK_SOURCE_EXTERN2 ,121 ,TEGRA_PERIPH_NO_RESET , tegra_clk_extern2), +MUX8 ("extern3" , mux_plla_clk32_pllp_clkm_plle,CLK_SOURCE_EXTERN3 ,122 ,TEGRA_PERIPH_NO_RESET , tegra_clk_extern3),MUX8 ("soc_therm" , mux_pllm_pllc_pllp_plla,CLK_SOURCE_SOC_THERM ,78 ,TEGRA_PERIPH_ON_APB , tegra_clk_soc_therm),MUX8 ("soc_therm" , mux_clkm_pllc_pllp_plla,CLK_SOURCE_SOC_THERM ,78 ,TEGRA_PERIPH_ON_APB , tegra_clk_soc_therm_8), MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
Signature · 1 line
2.30.2
PATCH v7 8/8 dt-bindings: clock: tegra: Convert to schema
In reply to Dmitry OsipenkoConvert NVIDIA Tegra clock bindings to schema.
--- .../bindings/clock/nvidia,tegra114-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra124-car.txt | 107 ---------------- .../bindings/clock/nvidia,tegra124-car.yaml | 115 ++++++++++++++++++ .../bindings/clock/nvidia,tegra20-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra20-car.yaml | 69 +++++++++++ .../bindings/clock/nvidia,tegra210-car.txt | 56 --------- .../bindings/clock/nvidia,tegra30-car.txt | 63 ---------- 7 files changed, 184 insertions(+), 352 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt deleted +0 -63
@@ -1,63 +0,0 @@ -NVIDIA Tegra114 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra114-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - <dt-bindings/clock/tegra114-car.h>. -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra114-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA114_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -};
Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt deleted +0 -107
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Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt deleted +0 -63
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Signature · 1 line
2.30.2
Rob Herring
maintainerRe: [PATCH v7 8/8] dt-bindings: clock: tegra: Convert to schema
Quoted 4 lines · Dmitry Osipenko
Convert NVIDIA Tegra clock bindings to schema.
Reviewed-by Rob Herring <[email protected]>Signed-off-by Dmitry Osipenko <[email protected]>
Quoted 17 lines
--- .../bindings/clock/nvidia,tegra114-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra124-car.txt | 107 ---------------- .../bindings/clock/nvidia,tegra124-car.yaml | 115 ++++++++++++++++++ .../bindings/clock/nvidia,tegra20-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra20-car.yaml | 69 +++++++++++ .../bindings/clock/nvidia,tegra210-car.txt | 56 --------- .../bindings/clock/nvidia,tegra30-car.txt | 63 ---------- 7 files changed, 184 insertions(+), 352 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:Documentation/devicetree/bindings/clock/nvidia,tegra20-car.example.dt.yaml:0:0: /example-0/usb-controller@c5004000: failed to match any schema with compatible: ['nvidia,tegra20-ehci'] Documentation/devicetree/bindings/clock/nvidia,tegra124-car.example.dt.yaml:0:0: /example-0/usb-controller@c5004000: failed to match any schema with compatible: ['nvidia,tegra20-ehci']
See https://patchwork.ozlabs.org/patch/1476773
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.