arm64: dts: qcom: sc7280: Add nodes for eMMC and SD card
Subsystems (5)
PATCH v5 1/1 arm64: dts: qcom: sc7280: Add nodes for eMMC and SD card
Add nodes for eMMC and SD card on sc7280.
---
This change is depends on the below patch series:
https://lore.kernel.org/patchwork/cover/1418814/
Changes since V4:
- Included gpio header in proper order and moved default pins configs to soc file as suggested by Stephen Boyd.
Changes since V3:
- Changed pinconfig names as suggested by Konrad Dybcio.
- Removed extra lines and aligned some of lines as suggested by Bjorn Andersson.
Change since V2:
- Added leading zero's for register address and "qcom,sc7280-sdhci" string in compatible as suggested by Stephen Boyd and Doug.
- Removed max-frequency flag, no-mmc and no-sdio flags for Sd card as suggested by Doug and Stephen Boyd.
- Moved non-removable, no-sd, no-sdio and some pin config changes from soc to board dts file as suggested by Doug.
- Removed sleep state for CD line and drive-strength for input pins as suggested by Doug.
- Updated bus vote numbers for eMMC and SD card.
Changes since V1:
- Moved SDHC nodes as suggested by Bjorn Andersson.
- Dropped "pinconf-" prefix as suggested by Bjorn Andersson.
- Removed extra newlines as suggested by Konrad Dybcio.
- Changed sd-cd pin to bias-pull-up in sdc2_off as suggested by Veerabhadrarao Badiganti.
- Added bandwidth votes for eMMC and SD card.
--- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 71 ++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 185 ++++++++++++++++++++++++++++++++ 2 files changed, 256 insertions(+)
arch/arm64/boot/dts/qcom/sc7280-idp.dts +71 -0
@@ -7,6 +7,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h> #include <dt-bindings/iio/qcom,spmi-adc7-pmr735b.h> #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
@@ -272,6 +273,34 @@ status = "okay"; }; +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + non-removable; + no-sd; + no-sdio; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + &uart5 { status = "okay"; };
@@ -291,3 +320,45 @@ bias-pull-up; }; }; + +&sdc1_on { + clk { + bias-disable; + drive-strength = <16>; + }; + + cmd { + bias-pull-up; + drive-strength = <10>; + }; + + data { + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + bias-pull-down; + }; +}; + +&sdc2_on { + clk { + bias-disable; + drive-strength = <16>; + }; + + cmd { + bias-pull-up; + drive-strength = <10>; + }; + + data { + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + bias-pull-up; + }; +};
arch/arm64/boot/dts/qcom/sc7280.dtsi +185 -0
209 lines not on this page · raw message
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
kernel test robot
build botThank you for the patch! Yet something to improve:
Hi Shaik,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on next-20210625]
[cannot apply to robh/for-next v5.13-rc7 v5.13-rc6 v5.13-rc5 v5.13-rc7] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Shaik-Sajida-Bhanu/arm64-dts-qcom-sc7280-Add-nodes-for-eMMC-and-SD-card/20210627-224336 base: 8702f95941c215501826ea8743a8b64b83479209 config: arm64-randconfig-r036-20210627 (attached as .config) compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/27dabbb7c6b1d684442e1d4b3321c71d01211341
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Shaik-Sajida-Bhanu/arm64-dts-qcom-sc7280-Add-nodes-for-eMMC-and-SD-card/20210627-224336 git checkout 27dabbb7c6b1d684442e1d4b3321c71d01211341
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/qcom/sc7280.dtsi:461.33-34 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
Quoting Shaik Sajida Bhanu (2021-06-27 07:42:30)
arch/arm64/boot/dts/qcom/sc7280.dtsi line 445
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0@@ -436,6 +441,60 @@ #mbox-cells = <2>; }; + sdhc_1: sdhci@7c4000 { + compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
Is qcom,sc7280-sdhci compatible documented somewhere?
Quoted 23 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +23
-0+ status = "disabled"; + + reg = <0 0x007c4000 0 0x1000>, + <0 0x007c5000 0 0x1000>; + reg-names = "hc", "cqhci"; + + iommus = <&apps_smmu 0xc0 0x0>; + interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + bus-width = <8>; + supports-cqe;
arch/arm64/boot/dts/qcom/sc7280.dtsi line 478
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + sdhc1_opp_table: sdhc1-opp-table {
Please make it
sdhc1_opp_table: opp-table {Quoted 42 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +35
-0+ compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1800000 400000>; + opp-avg-kBps = <100000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <390000 0>; + }; + }; + + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>;@@ -1035,6 +1094,51 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; + status = "disabled"; + + reg = <0 0x08804000 0 0x1000>; + + iommus = <&apps_smmu 0x100 0x0>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
arch/arm64/boot/dts/qcom/sc7280.dtsi line 1122
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + bus-width = <4>; + + qcom,dll-config = <0x0007642c>; + + sdhc2_opp_table: sdhc2-opp-table {
Please make it
sdhc2_opp_table: opp-table {Quoted 22 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +19
-0+ compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1800000 400000>; + opp-avg-kBps = <100000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <200000 0>; + }; + }; + + }; + dc_noc: interconnect@90e0000 { reg = <0 0x090e0000 0 0x5080>; compatible = "qcom,sc7280-dc-noc";
Quoted 9 lines · Stephen Boyd
Quoting Shaik Sajida Bhanu (2021-06-27 07:42:30)
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +0
-0@@ -436,6 +441,60 @@ #mbox-cells = <2>; };
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 446
Quoted 3 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0+ sdhc_1: sdhci@7c4000 { + compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";Is qcom,sc7280-sdhci compatible documented somewhere?
Yes, please find the link below:
https://patchwork.kernel.org/project/linux-arm-msm/patch/[email protected]/
Quoted 41 lines
Quoted 28 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +16
-0+ status = "disabled"; + + reg = <0 0x007c4000 0 0x1000>, + <0 0x007c5000 0 0x1000>; + reg-names = "hc", "cqhci"; + + iommus = <&apps_smmu 0xc0 0x0>; + interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_1 0
&mc_virtSLAVE_EBI10>,
+ <&gem_nocMASTER_APPSS_PROC0
&cnoc2SLAVE_SDCC_10>;arch/arm64/boot/dts/qcom/sc7280.dtsi +6
-0+ interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + bus-width = <8>; + supports-cqe;arch/arm64/boot/dts/qcom/sc7280.dtsi line 478
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + sdhc1_opp_table: sdhc1-opp-table {Please make it
Quoted 1 line
sdhc1_opp_table: opp-table {Sure
Quoted 68 lines
Quoted 56 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64<100000000>;
+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1800000
400000>;arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ opp-avg-kBps = <100000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64<384000000>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000
1600000>;arch/arm64/boot/dts/qcom/sc7280.dtsi +22
-0+ opp-avg-kBps = <390000 0>; + }; + }; + + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>;@@ -1035,6 +1094,51 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; + status = "disabled"; + + reg = <0 0x08804000 0 0x1000>; + + iommus = <&apps_smmu 0x100 0x0>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_2 0
&mc_virtSLAVE_EBI10>,
+ <&gem_nocMASTER_APPSS_PROC0
&cnoc2SLAVE_SDCC_20>;arch/arm64/boot/dts/qcom/sc7280.dtsi line 1122
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +9
-0+ interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + bus-width = <4>; + + qcom,dll-config = <0x0007642c>; + + sdhc2_opp_table: sdhc2-opp-table {Please make it
Quoted 1 line
sdhc2_opp_table: opp-table {Sure
Quoted 30 lines
Quoted 30 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64<100000000>;
+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1800000
400000>;arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ opp-avg-kBps = <100000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64<202000000>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000
1600000>;arch/arm64/boot/dts/qcom/sc7280.dtsi +6
-0+ opp-avg-kBps = <200000 0>; + }; + }; + + }; + dc_noc: interconnect@90e0000 { reg = <0 0x090e0000 0 0x5080>; compatible = "qcom,sc7280-dc-noc";