tegra20-emc: Identify memory chip by LPDDR configuration
v4 cover tegra20-emc: Identify memory chip by LPDDR configuration
Support memory chip identification by LPDDR2 configuration, which is needed by ASUS Transformer TF101 tablet device that doesn't store RAMCODE in Tegra's NVMEM.
Changelog:
v4: - Moved DDR bindings directory to memory-controllers/, like it
was suggested by Krzysztof Kozlowski.
- Converted existing LPDDR2 binding to schema and utilized it, like it was requested by Krzysztof Kozlowski.
- Added Elpida B8132B2PB-6D-F compatible.
- Made code changes that were requested by Krzysztof Kozlowski.
v3: - Corrected sub-node name in tegra20-emc.yaml.
v2: - Added separate binding for standard LPDDR2 properties, like it
was suggested by Krzysztof Kozlowski.
- Switched Tegra binding to use new lpddr2-configuration sub-node that contains the standard properties.
- Extended commit message of the "emc: Document new LPDDR2 sub-node" patch, telling how the properties are supposed to be used, which was requested by Krzysztof Kozlowski.
- Added new common helpers for parsing LPDDR2 properties and made tegra20-emc driver to use these helpers.
Dmitry Osipenko (7):
dt-bindings: Relocate DDR bindings
dt-bindings: memory: lpddr2: Convert to schema
dt-bindings: memory: lpddr2: Add revision-id properties
dt-bindings: memory: lpddr2: Document Elpida B8132B2PB-6D-F
dt-bindings: memory: tegra20: emc: Document new LPDDR2 sub-node
memory: Add LPDDR2 configuration helpers
memory: tegra20-emc: Support matching timings by LPDDR2 configuration
.../devicetree/bindings/ddr/lpddr2.txt | 102 ---------
.../memory-controllers/ddr/jedec,lpddr2.yaml | 208 ++++++++++++++++++
.../ddr/lpddr2-timings.txt | 0
.../ddr/lpddr3-timings.txt | 0
.../{ => memory-controllers}/ddr/lpddr3.txt | 0
.../nvidia,tegra20-emc.yaml | 23 +-
drivers/memory/jedec_ddr.h | 46 ++++
drivers/memory/jedec_ddr_data.c | 41 ++++
drivers/memory/of_memory.c | 88 ++++++++
drivers/memory/of_memory.h | 9 +
drivers/memory/tegra/Kconfig | 1 +
drivers/memory/tegra/tegra20-emc.c | 199 +++++++++++++++--
12 files changed, 599 insertions(+), 118 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ddr/lpddr2.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
rename Documentation/devicetree/bindings/{ => memory-controllers}/ddr/lpddr2-timings.txt (100%)
rename Documentation/devicetree/bindings/{ => memory-controllers}/ddr/lpddr3-timings.txt (100%)
rename Documentation/devicetree/bindings/{ => memory-controllers}/ddr/lpddr3.txt (100%)Signature · 1 line
2.32.0
PATCH v4 1/7 dt-bindings: Relocate DDR bindings
Move DDR bindings to memory-controllers directory to make them more discoverable.
---
.../bindings/{ => memory-controllers}/ddr/lpddr2-timings.txt | 0
.../devicetree/bindings/{ => memory-controllers}/ddr/lpddr2.txt | 0
.../bindings/{ => memory-controllers}/ddr/lpddr3-timings.txt | 0
.../devicetree/bindings/{ => memory-controllers}/ddr/lpddr3.txt | 0
4 files changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{ => memory-controllers}/ddr/lpddr2-timings.txt (100%)
rename Documentation/devicetree/bindings/{ => memory-controllers}/ddr/lpddr2.txt (100%)
rename Documentation/devicetree/bindings/{ => memory-controllers}/ddr/lpddr3-timings.txt (100%)
rename Documentation/devicetree/bindings/{ => memory-controllers}/ddr/lpddr3.txt (100%)Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt renamed from Documentation/devicetree/bindings/ddr/lpddr2-timings.txt +0 -0
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2.txt renamed from Documentation/devicetree/bindings/ddr/lpddr2.txt +0 -0
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt renamed from Documentation/devicetree/bindings/ddr/lpddr3-timings.txt +0 -0
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt renamed from Documentation/devicetree/bindings/ddr/lpddr3.txt +0 -0
Signature · 1 line
2.32.0
PATCH v4 2/7 dt-bindings: memory: lpddr2: Convert to schema
In reply to Dmitry OsipenkoConvert LPDDR2 binding to schema. I removed obsolete ti,jedec-lpddr2-* compatibles since they were never used by device-trees and by the code.
--- .../memory-controllers/ddr/jedec,lpddr2.yaml | 195 ++++++++++++++++++ .../memory-controllers/ddr/lpddr2.txt | 102 --------- 2 files changed, 195 insertions(+), 102 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2.txt
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +195 -0
@@ -0,0 +1,195 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR2 SDRAM compliant to JEDEC JESD209-2 + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +properties: + compatible: + oneOf: + - items: + - enum: + - Elpida,ECB240ABACN + - enum: + - jedec,lpddr2-s4 + - items: + - enum: + - jedec,lpddr2-s2 + - items: + - enum: + - jedec,lpddr2-nvm + + density: + description: | + Density in megabits of SDRAM chip. Obtained from device datasheet. + enum: + - 64 + - 128 + - 256 + - 512 + - 1024 + - 2048 + - 4096 + - 8192 + - 16384 + - 32768 + + io-width: + description: | + IO bus width in bits of SDRAM chip. Obtained from device datasheet. + enum: + - 32 + - 16 + - 8 + + tRRD-min-tck: + maximum: 16 + description: | + Active bank a to active bank b in terms of number of clock cycles. + Obtained from device datasheet. + + tWTR-min-tck: + maximum: 16 + description: | + Internal WRITE-to-READ command delay in terms of number of clock cycles. + Obtained from device datasheet. + + tXP-min-tck: + maximum: 16 + description: | + Exit power-down to next valid command delay in terms of number of clock + cycles. Obtained from device datasheet. + + tRTP-min-tck: + maximum: 16 + description: | + Internal READ to PRECHARGE command delay in terms of number of clock + cycles. Obtained from device datasheet. + + tCKE-min-tck: + maximum: 16 + description: | + CKE minimum pulse width (HIGH and LOW pulse width) in terms of number + of clock cycles. Obtained from device datasheet. + + tRPab-min-tck: + maximum: 16 + description: | + Row precharge time (all banks) in terms of number of clock cycles. + Obtained from device datasheet. + + tRCD-min-tck: + maximum: 16 + description: | + RAS-to-CAS delay in terms of number of clock cycles. Obtained from + device datasheet. + + tWR-min-tck: + maximum: 16 + description: | + WRITE recovery time in terms of number of clock cycles. Obtained from + device datasheet. + + tRASmin-min-tck: + maximum: 16 + description: | + Row active time in terms of number of clock cycles. Obtained from device + datasheet. + + tCKESR-min-tck: + maximum: 16 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in terms of number of clock cycles. Obtained from device + datasheet. + + tFAW-min-tck: + maximum: 16 + description: | + Four-bank activate window in terms of number of clock cycles. Obtained + from device datasheet. + +patternProperties: + "^lpddr2-timings": + type: object + description: | + The lpddr2 node may have one or more child nodes of type "lpddr2-timings". + "lpddr2-timings" provides AC timing parameters of the device for + a given speed-bin. The user may provide the timings for as many + speed-bins as is required. Please see Documentation/devicetree/ + bindings/memory-controllers/ddr/lpddr2-timings.txt for more information + on "lpddr2-timings". + +required: + - compatible + - density + - io-width + +additionalProperties: false + +examples: + - | + elpida_ECB240ABACN: lpddr2 { + compatible = "Elpida,ECB240ABACN", "jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + };
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2.txt deleted +0 -102
102 lines not on this page · raw message
Signature · 1 line
2.32.0
Re: [PATCH v4 2/7] dt-bindings: memory: lpddr2: Convert to schema
Quoted 18 lines · Dmitry Osipenko
Convert LPDDR2 binding to schema. I removed obsolete ti,jedec-lpddr2-* compatibles since they were never used by device-trees and by the code.
Suggested-by Krzysztof Kozlowski <[email protected]>Signed-off-by Dmitry Osipenko <[email protected]>--- .../memory-controllers/ddr/jedec,lpddr2.yaml | 195 ++++++++++++++++++ .../memory-controllers/ddr/lpddr2.txt | 102 --------- 2 files changed, 195 insertions(+), 102 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2.txtDocumentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +0
-0
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml line 10
Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +10
-0@@ -0,0 +1,195 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR2 SDRAM compliant to JEDEC JESD209-2 + +maintainers: + - Krzysztof Kozlowski <[email protected]>
My Canonical address please, so:
Krzysztof Kozlowski <[email protected]>
Quoted 9 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +9
-0+ +properties: + compatible: + oneOf: + - items: + - enum: + - Elpida,ECB240ABACN + - enum: + - jedec,lpddr2-s4
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml line 29
Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +10
-0+ - items: + - enum: + - jedec,lpddr2-s2 + - items: + - enum: + - jedec,lpddr2-nvm + + density: + description: | + Density in megabits of SDRAM chip. Obtained from device datasheet.
You need here a type/ref, so uint32.
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +5
-0+ enum: + - 64 + - 128 + - 256 + - 512
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml line 44
Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +10
-0+ - 1024 + - 2048 + - 4096 + - 8192 + - 16384 + - 32768 + + io-width: + description: | + IO bus width in bits of SDRAM chip. Obtained from device datasheet.
You need here a type/ref, so uint32.
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml line 51
Quoted 7 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +7
-0+ enum: + - 32 + - 16 + - 8 + + tRRD-min-tck: + maximum: 16
Here and further type is needed.
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml line 61
Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +10
-0+ description: | + Active bank a to active bank b in terms of number of clock cycles. + Obtained from device datasheet. + + tWTR-min-tck: + maximum: 16 + description: | + Internal WRITE-to-READ command delay in terms of number of clock cycles. + Obtained from device datasheet. +
Best regards,
Krzysztof
Re: [PATCH v4 2/7] dt-bindings: memory: lpddr2: Convert to schema
06.10.2021 13:57, Krzysztof Kozlowski пишет:
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml line 29
Quoted 3 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +3
-0+ density: + description: | + Density in megabits of SDRAM chip. Obtained from device datasheet.You need here a type/ref, so uint32.
The type is uint32 by default. I can add it, but it's not really necessary.
Re: [PATCH v4 2/7] dt-bindings: memory: lpddr2: Convert to schema
06.10.2021 18:41, Dmitry Osipenko пишет:
Quoted 9 lines
06.10.2021 13:57, Krzysztof Kozlowski пишет:
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml line 29
Quoted 3 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +3
-0+ density: + description: | + Density in megabits of SDRAM chip. Obtained from device datasheet.You need here a type/ref, so uint32.
The type is uint32 by default. I can add it, but it's not really necessary.
You may grep bindings for 'enum: [' to see that nobody is specifying the type.
Re: [PATCH v4 2/7] dt-bindings: memory: lpddr2: Convert to schema
Quoted 5 lines · Dmitry Osipenko
06.10.2021 18:41, Dmitry Osipenko пишет:
Quoted 4 lines
06.10.2021 13:57, Krzysztof Kozlowski пишет:
Quoted 3 lines
Quoted 3 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +3
-0+ density: + description: | + Density in megabits of SDRAM chip. Obtained from device datasheet.
Quoted 9 lines
Quoted 5 lines
Quoted 2 lines
You need here a type/ref, so uint32.
The type is uint32 by default. I can add it, but it's not really necessary.
You may grep bindings for 'enum: [' to see that nobody is specifying the type.
Just because everyone makes a mistake, is not a proof it should be done like that. Please see example schema and vendor,int-property.
AFAIR, only properties defined by schema (directly or by unit suffix, e.g. microvolt) do not need types.
Best regards,
Krzysztof
Re: [PATCH v4 2/7] dt-bindings: memory: lpddr2: Convert to schema
06.10.2021 20:23, Krzysztof Kozlowski пишет:
Quoted 16 lines · Dmitry Osipenko
Quoted 5 lines
06.10.2021 18:41, Dmitry Osipenko пишет:
Quoted 4 lines
06.10.2021 13:57, Krzysztof Kozlowski пишет:
Quoted 3 lines
Quoted 3 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +3
-0+ density: + description: | + Density in megabits of SDRAM chip. Obtained from device datasheet.Quoted 9 lines
Quoted 5 lines
Quoted 2 lines
You need here a type/ref, so uint32.
The type is uint32 by default. I can add it, but it's not really necessary.
You may grep bindings for 'enum: [' to see that nobody is specifying the type.
Quoted 5 lines
Just because everyone makes a mistake, is not a proof it should be done like that. Please see example schema and vendor,int-property.
AFAIR, only properties defined by schema (directly or by unit suffix, e.g. microvolt) do not need types.
I'm not DT expert, but dt_binding_check says that binding is valid, even with W=1. Meanwhile negative values are wrong. All integers are u32 by default for DTB.
Alright, I'll just add the type since it won't hurt anyways.
Re: [PATCH v4 2/7] dt-bindings: memory: lpddr2: Convert to schema
In reply to Dmitry OsipenkoQuoted 8 lines · Dmitry Osipenko
06.10.2021 13:57, Krzysztof Kozlowski пишет:
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml line 29
Quoted 3 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file +3
-0+ density: + description: | + Density in megabits of SDRAM chip. Obtained from device datasheet.You need here a type/ref, so uint32.
The type is uint32 by default. I can add it, but it's not really necessary.
Hmmm, maybe I missed some background here. Who sets uint32 as default? The schema does not define "density" so this is more like a vendor-type property which required therefore a type.
Also Rob's pointed this to my patch here around "op_mode":
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#m17adea693a9cbcca75b0ba6f9d878f5fd1bf5d14
Best regards,
Krzysztof
PATCH v4 3/7 dt-bindings: memory: lpddr2: Add revision-id properties
In reply to Dmitry OsipenkoAdd optional revision-id standard LPDDR2 properties which will help to identify memory chip.
--- .../memory-controllers/ddr/jedec,lpddr2.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +12 -0
@@ -24,6 +24,16 @@ properties: - enum: - jedec,lpddr2-nvm + revision-id1: + maximum: 255 + description: | + Revision 1 value of SDRAM chip. Obtained from device datasheet. + + revision-id2: + maximum: 255 + description: | + Revision 2 value of SDRAM chip. Obtained from device datasheet. + density: description: | Density in megabits of SDRAM chip. Obtained from device datasheet.
@@ -138,6 +148,8 @@ examples: compatible = "Elpida,ECB240ABACN", "jedec,lpddr2-s4"; density = <2048>; io-width = <32>; + revision-id1 = <1>; + revision-id2 = <0>; tRPab-min-tck = <3>; tRCD-min-tck = <3>;
Signature · 1 line
2.32.0
Re: [PATCH v4 3/7] dt-bindings: memory: lpddr2: Add revision-id properties
Quoted 13 lines · Dmitry Osipenko
Add optional revision-id standard LPDDR2 properties which will help to identify memory chip.
Signed-off-by Dmitry Osipenko <[email protected]>--- .../memory-controllers/ddr/jedec,lpddr2.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +0
-0
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml properties: · line 31
Quoted 8 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +5
-0@@ -24,6 +24,16 @@ properties: - enum: - jedec,lpddr2-nvm + revision-id1: + maximum: 255 + description: | + Revision 1 value of SDRAM chip. Obtained from device datasheet. +
Also type/ref for uint32 needed.
Best regards,
Krzysztof
Re: [PATCH v4 3/7] dt-bindings: memory: lpddr2: Add revision-id properties
06.10.2021 13:59, Krzysztof Kozlowski пишет:
Quoted 17 lines · Dmitry Osipenko
Quoted 16 lines
Add optional revision-id standard LPDDR2 properties which will help to identify memory chip.
Signed-off-by Dmitry Osipenko <[email protected]>--- .../memory-controllers/ddr/jedec,lpddr2.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +0
-0@@ -24,6 +24,16 @@ properties: - enum: - jedec,lpddr2-nvm
Quoted 7 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml properties: · line 31
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +5
-0+ revision-id1: + maximum: 255 + description: | + Revision 1 value of SDRAM chip. Obtained from device datasheet. +Also type/ref for uint32 needed.
Also unnecessary :) It's uint32 by default, inferred from the 'maximum'.
Re: [PATCH v4 3/7] dt-bindings: memory: lpddr2: Add revision-id properties
06.10.2021 18:47, Dmitry Osipenko пишет:
Quoted 26 lines
06.10.2021 13:59, Krzysztof Kozlowski пишет:
Quoted 17 lines · Dmitry Osipenko
Quoted 16 lines
Add optional revision-id standard LPDDR2 properties which will help to identify memory chip.
Signed-off-by Dmitry Osipenko <[email protected]>--- .../memory-controllers/ddr/jedec,lpddr2.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +0
-0@@ -24,6 +24,16 @@ properties: - enum: - jedec,lpddr2-nvmQuoted 7 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml properties: · line 31
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +5
-0+ revision-id1: + maximum: 255 + description: | + Revision 1 value of SDRAM chip. Obtained from device datasheet. +Also type/ref for uint32 needed.
Quoted 2 lines
Also unnecessary :) It's uint32 by default, inferred from the 'maximum'.
Please grep for 'maximum: ' to see that other bindings don't specify the type.
PATCH v4 4/7 dt-bindings: memory: lpddr2: Document Elpida B8132B2PB-6D-F
In reply to Dmitry OsipenkoElpida B8132B2PB-6D-F memory chip is used by ASUS Transformer TF101 tablet, add compatible for it. We need to specify this compatible it for a device-tree node containing corresponding memory timings in order to allow software to match the timings with the detected hardware.
--- .../devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +1 -0
@@ -15,6 +15,7 @@ properties: - items: - enum: - Elpida,ECB240ABACN + - elpida,B8132B2PB-6D-F - enum: - jedec,lpddr2-s4 - items:
Signature · 1 line
2.32.0
PATCH v4 5/7 dt-bindings: memory: tegra20: emc: Document new LPDDR2 sub-node
In reply to Dmitry OsipenkoSome Tegra20 boards don't have RAM code stored in NVMEM, which is used for the memory chip identification and the identity information should be read out from LPDDR2 chip in this case. Document new sub-node containing generic LPDDR2 properties that will be used for the memory chip identification if RAM code isn't available. The identification is done by reading out memory configuration values from generic LPDDR2 mode registers of SDRAM chip and comparing them with the values of device-tree 'lpddr2' sub-node.
--- .../nvidia,tegra20-emc.yaml | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml +21 -2
@@ -164,12 +164,20 @@ patternProperties: "#size-cells": const: 0 + lpddr2: + $ref: "ddr/jedec,lpddr2.yaml#" + type: object + patternProperties: "^emc-table@[0-9]+$": $ref: "#/$defs/emc-table" - required: - - nvidia,ram-code + oneOf: + - required: + - nvidia,ram-code + + - required: + - lpddr2 additionalProperties: false
@@ -227,4 +235,15 @@ examples: 0x00000000 0x00000000 0x00000000 0x00000000>; }; }; + + emc-tables@1 { + reg = <1>; + + lpddr2 { + compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; + revision-id1 = <1>; + density = <2048>; + io-width = <16>; + }; + }; };
Signature · 1 line
2.32.0
PATCH v4 6/7 memory: Add LPDDR2 configuration helpers
In reply to Dmitry OsipenkoAdd common helpers for reading and parsing standard LPDDR2 configuration properties.
--- drivers/memory/jedec_ddr.h | 46 +++++++++++++++++ drivers/memory/jedec_ddr_data.c | 41 +++++++++++++++ drivers/memory/of_memory.c | 88 +++++++++++++++++++++++++++++++++ drivers/memory/of_memory.h | 9 ++++ 4 files changed, 184 insertions(+)
drivers/memory/jedec_ddr.h +46 -0
@@ -112,6 +112,26 @@#define NUM_DDR_ADDR_TABLE_ENTRIES 11#define NUM_DDR_TIMING_TABLE_ENTRIES 4 +#define LPDDR2_MANID_SAMSUNG 1 +#define LPDDR2_MANID_QIMONDA 2 +#define LPDDR2_MANID_ELPIDA 3 +#define LPDDR2_MANID_ETRON 4 +#define LPDDR2_MANID_NANYA 5 +#define LPDDR2_MANID_HYNIX 6 +#define LPDDR2_MANID_MOSEL 7 +#define LPDDR2_MANID_WINBOND 8 +#define LPDDR2_MANID_ESMT 9 +#define LPDDR2_MANID_SPANSION 11 +#define LPDDR2_MANID_SST 12 +#define LPDDR2_MANID_ZMOS 13 +#define LPDDR2_MANID_INTEL 14 +#define LPDDR2_MANID_NUMONYX 254 +#define LPDDR2_MANID_MICRON 255 + +#define LPDDR2_TYPE_S4 0 +#define LPDDR2_TYPE_S2 1 +#define LPDDR2_TYPE_NVM 2 +/* Structure for DDR addressing info from the JEDEC spec */ struct lpddr2_addressing {u32 num_banks;
@@ -170,6 +190,32 @@ extern const struct lpddr2_timings lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES ];extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; +/* Structure of MR8 */ +union lpddr2_basic_config4 { +u32 value; + +struct { +unsigned int arch_type :2 ; +unsigned int density :4 ; +unsigned int io_width :2 ; + } __packed; +}; + +/* +* Structure for information about LPDDR2 chip. All parameters are matching +* raw values of mode register bitfields or negative if info unavailable. +*/ +struct lpddr2_info { +int arch_type; +int density; +int io_width; +int manufacturer_id; +int revision_id1; +int revision_id2; +}; + +const char *lpddr2_jedec_manufacturer (unsigned int manufacturer_id); +/* * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields. * All parameters are in pico seconds(ps) excluding max_freq, min_freq which
drivers/memory/jedec_ddr_data.c +41 -0
44 lines not on this page · raw message
drivers/memory/of_memory.c +88 -0
91 lines not on this page · raw message
drivers/memory/of_memory.h +9 -0
@@ -20,6 +20,9 @@ const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np,const struct lpddr3_timings *of_lpddr3_get_ddr_timings (struct device_node *np_ddr,struct device *dev,u32 device_type,u32 *nr_frequencies); + +const struct lpddr2_info *of_lpddr2_get_info (struct device_node *np, +struct device *dev);#else static inline const struct lpddr2_min_tck *of_get_min_tck (struct device_node *np,struct device *dev)
@@ -46,6 +49,12 @@ static inline const struct lpddr3_timings {return NULL ; } + +static inline const struct lpddr2_info + *of_lpddr2_get_info (struct device_node *np,struct device *dev) +{ +return NULL ; +}#endif /* CONFIG_OF && CONFIG_DDR */ #endif /* __LINUX_MEMORY_OF_REG_ */
Signature · 1 line
2.32.0
PATCH v4 7/7 memory: tegra20-emc: Support matching timings by LPDDR2 configuration
In reply to Dmitry OsipenkoASUS Transformer TF101 doesn't provide RAM code and in this case memory timings should be selected based on identity information read out from SDRAM chip. Support matching timings by LPDDR2 configuration.
--- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/tegra20-emc.c | 199 +++++++++++++++++++++++++++-- 2 files changed, 186 insertions(+), 14 deletions(-)
drivers/memory/tegra/Kconfig +1 -0
@@ -16,6 +16,7 @@ config TEGRA20_EMC depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST select DEVFREQ_GOV_SIMPLE_ONDEMAND select PM_DEVFREQ + select DDR help This driver is for the External Memory Controller (EMC) found on Tegra20 chips. The EMC controls the external DRAM on the board.
drivers/memory/tegra/tegra20-emc.c +185 -14
303 lines not on this page · raw message
Signature · 1 line
2.32.0