clocksource/arm_arch_timer: Add basic ARMv8.6 support
Subsystems (5)
Marc Zyngier
maintainerv4 cover clocksource/arm_arch_timer: Add basic ARMv8.6 support
This is v4 (final?) of the series enabling ARMv8.6 support for timer subsystem, and was prompted by a discussion with Oliver around the fact that an ARMv8.6 implementation must have a 1GHz counter, which leads to a number of things to break in the timer code:
- the counter rollover can come pretty quickly as we only advertise a 56bit counter,
- the maximum timer delta can be remarkably small, as we use the countdown interface which is limited to 32bit...
Thankfully, there is a way out: we can compute the minimal width of the counter based on the guarantees that the architecture gives us, and we can use the 64bit comparator interface instead of the countdown to program the timer.
Finally, we start making use of the ARMv8.6 ECV features by switching accesses to the counters to a self-synchronising register, removing the need for an ISB. Hopefully, implementations will *not* just stick an invisible ISB there...
A side effect of the switch to CVAL is that XGene-1 breaks. I have added a workaround to keep it alive.
I have added Oliver's original patch[0] to the series and tweaked a couple of things. Blame me if I broke anything.
The whole things has been tested on Juno (sysreg + MMIO timers), XGene-1 (broken sysreg timers), FVP (FEAT_ECV, CNT*CTSS_EL0).
To ease merging, and after discussion with Daniel, I have created two tags from which the patches can be pulled fromgit://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git :
- clocksource-timers-arm64-8.6 has the first 13 patches, which can go into Daniel's tree, and ultimately tip
- arm64-timers-8.6 has the full series, which can be pulled into the arm64 tree
Alternatively, Will and Daniel can synchronise independently to build a branch of their own.
* From v3 [3]:
- Drop the %x0 qualifiers for the registers in the asm accessors
- Added an update to cpu-feature-registers.rst
- Collected Acks, with thanks.
* From v2 [2]:
- New patch adding a HWCAP (ECV) allowing userspace to probe for the presence of CNTVSS_EL0.
* From v1 [1]:
- New patch adding a bunch of BUILD_BUG()s for register accesses we don't expect. This makes subsequent patches much simpler.
- New patch moving the ISBs for workaround in a way that makes more sense for the self-synchronising accessors.
- Rework the XGene-1 workaround to rely solely on MIDR.
- Split the CNTVCTSS trap handling in its own patch.
- Rebased on 5.15-rc2
- Collected RBs, with thanks.
[0] https://lore.kernel.org/r/[email protected]
[1] https://lore.kernel.org/r/[email protected]
[2] https://lore.kernel.org/r/[email protected]
[3] https://lore.kernel.org/r/[email protected]
Marc Zyngier (16):
clocksource/arm_arch_timer: Add build-time guards for unhandled
register accesses
clocksource/arm_arch_timer: Drop CNT*_TVAL read accessors clocksource/arm_arch_timer: Extend write side of timer register
accessors to u64
clocksource/arm_arch_timer: Move system register timer programming
over to CVAL
clocksource/arm_arch_timer: Move drop _tval from erratum function
names
clocksource/arm_arch_timer: Fix MMIO base address vs callback ordering
issue
clocksource/arm_arch_timer: Move MMIO timer programming over to CVAL clocksource/arm_arch_timer: Advertise 56bit timer to the core code clocksource/arm_arch_timer: Work around broken CVAL implementations clocksource/arm_arch_timer: Remove any trace of the TVAL programming
interface
clocksource/arm_arch_timer: Drop unnecessary ISB on CVAL programming clocksource/arch_arm_timer: Move workaround synchronisation around
arm64: Add a capability for FEAT_ECV
arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0
arm64: Add handling of CNTVCTSS traps
arm64: Add HWCAP for self-synchronising virtual counter
Oliver Upton (1):
clocksource/arm_arch_timer: Fix masking for high freq counters
Documentation/arm64/cpu-feature-registers.rst | 12 +- Documentation/arm64/elf_hwcaps.rst | 4 + arch/arm/include/asm/arch_timer.h | 37 +-- arch/arm64/include/asm/arch_timer.h | 78 +++--- arch/arm64/include/asm/esr.h | 6 + arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/asm/sysreg.h | 3 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 13 +- arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/kernel/traps.c | 11 + arch/arm64/tools/cpucaps | 1 + drivers/clocksource/arm_arch_timer.c | 243 +++++++++++------- include/clocksource/arm_arch_timer.h | 2 +- 14 files changed, 264 insertions(+), 149 deletions(-)
Signature · 1 line
2.30.2
Marc Zyngier
maintainerPATCH v4 1/17 clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses
As we are about to change the registers that are used by the driver, start by adding build-time checks to ensure that we always handle all registers and access modes.
--- arch/arm/include/asm/arch_timer.h | 12 ++++++++++++ arch/arm64/include/asm/arch_timer.h | 13 ++++++++++++- drivers/clocksource/arm_arch_timer.c | 8 ++++++++ 3 files changed, 32 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch_timer.h +12 -0
@@ -34,6 +34,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)case ARCH_TIMER_REG_TVAL : asmvolatile ("mcr p15, 0, %0, c14, c2, 0" : :"r" (val));break ; +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_VIRT_ACCESS ) {switch (reg) {
@@ -43,7 +45,11 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)case ARCH_TIMER_REG_TVAL : asmvolatile ("mcr p15, 0, %0, c14, c3, 0" : :"r" (val));break ; +default : +BUILD_BUG (); } + }else { +BUILD_BUG (); }isb ();
@@ -62,6 +68,8 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)case ARCH_TIMER_REG_TVAL : asmvolatile ("mrc p15, 0, %0, c14, c2, 0" :"=r" (val));break ; +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_VIRT_ACCESS ) {switch (reg) {
@@ -71,7 +79,11 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)case ARCH_TIMER_REG_TVAL : asmvolatile ("mrc p15, 0, %0, c14, c3, 0" :"=r" (val));break ; +default : +BUILD_BUG (); } + }else { +BUILD_BUG (); }return val;
arch/arm64/include/asm/arch_timer.h +12 -1
@@ -112,6 +112,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)case ARCH_TIMER_REG_TVAL :write_sysreg (val, cntp_tval_el0);break ; +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_VIRT_ACCESS ) {switch (reg) {
@@ -121,7 +123,11 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)case ARCH_TIMER_REG_TVAL :write_sysreg (val, cntv_tval_el0);break ; +default : +BUILD_BUG (); } + }else { +BUILD_BUG (); }isb ();
@@ -136,6 +142,8 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)return read_sysreg (cntp_ctl_el0);case ARCH_TIMER_REG_TVAL :return arch_timer_reg_read_stable (cntp_tval_el0); +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_VIRT_ACCESS ) {switch (reg) {
@@ -143,10 +151,13 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)return read_sysreg (cntv_ctl_el0);case ARCH_TIMER_REG_TVAL :return arch_timer_reg_read_stable (cntv_tval_el0); +default : +BUILD_BUG (); } } -BUG (); +BUILD_BUG (); +unreachable (); }static inline u32 arch_timer_get_cntfrq (void )
drivers/clocksource/arm_arch_timer.c +8 -0
@@ -112,6 +112,8 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,case ARCH_TIMER_REG_TVAL :writel_relaxed (val, timer->base +CNTP_TVAL );break ; +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_MEM_VIRT_ACCESS ) {struct arch_timer *timer =to_arch_timer (clk);
@@ -122,6 +124,8 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,case ARCH_TIMER_REG_TVAL :writel_relaxed (val, timer->base +CNTV_TVAL );break ; +default : +BUILD_BUG (); } }else {arch_timer_reg_write_cp15 (access, reg, val);
@@ -143,6 +147,8 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,case ARCH_TIMER_REG_TVAL : val =readl_relaxed (timer->base +CNTP_TVAL );break ; +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_MEM_VIRT_ACCESS ) {struct arch_timer *timer =to_arch_timer (clk);
@@ -153,6 +159,8 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,case ARCH_TIMER_REG_TVAL : val =readl_relaxed (timer->base +CNTV_TVAL );break ; +default : +BUILD_BUG (); } }else { val =arch_timer_reg_read_cp15 (access, reg);
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 4775bc63f880001ee4fbd6456b12ab04674149e3 Gitweb: https://git.kernel.org/tip/4775bc63f880001ee4fbd6456b12ab04674149e3 Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:09 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Sun, 17 Oct 2021 21:45:48 +02:00
clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses
As we are about to change the registers that are used by the driver, start by adding build-time checks to ensure that we always handle all registers and access modes.
--- arch/arm/include/asm/arch_timer.h | 12 ++++++++++++ arch/arm64/include/asm/arch_timer.h | 13 ++++++++++++- drivers/clocksource/arm_arch_timer.c | 8 ++++++++ 3 files changed, 32 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch_timer.h +12 -0
@@ -34,6 +34,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)case ARCH_TIMER_REG_TVAL : asmvolatile ("mcr p15, 0, %0, c14, c2, 0" : :"r" (val));break ; +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_VIRT_ACCESS ) {switch (reg) {
@@ -43,7 +45,11 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)case ARCH_TIMER_REG_TVAL : asmvolatile ("mcr p15, 0, %0, c14, c3, 0" : :"r" (val));break ; +default : +BUILD_BUG (); } + }else { +BUILD_BUG (); }isb ();
@@ -62,6 +68,8 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)case ARCH_TIMER_REG_TVAL : asmvolatile ("mrc p15, 0, %0, c14, c2, 0" :"=r" (val));break ; +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_VIRT_ACCESS ) {switch (reg) {
@@ -71,7 +79,11 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)case ARCH_TIMER_REG_TVAL : asmvolatile ("mrc p15, 0, %0, c14, c3, 0" :"=r" (val));break ; +default : +BUILD_BUG (); } + }else { +BUILD_BUG (); }return val;
arch/arm64/include/asm/arch_timer.h +12 -1
@@ -112,6 +112,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)case ARCH_TIMER_REG_TVAL :write_sysreg (val, cntp_tval_el0);break ; +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_VIRT_ACCESS ) {switch (reg) {
@@ -121,7 +123,11 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)case ARCH_TIMER_REG_TVAL :write_sysreg (val, cntv_tval_el0);break ; +default : +BUILD_BUG (); } + }else { +BUILD_BUG (); }isb ();
@@ -136,6 +142,8 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)return read_sysreg (cntp_ctl_el0);case ARCH_TIMER_REG_TVAL :return arch_timer_reg_read_stable (cntp_tval_el0); +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_VIRT_ACCESS ) {switch (reg) {
@@ -143,10 +151,13 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)return read_sysreg (cntv_ctl_el0);case ARCH_TIMER_REG_TVAL :return arch_timer_reg_read_stable (cntv_tval_el0); +default : +BUILD_BUG (); } } -BUG (); +BUILD_BUG (); +unreachable (); }static inline u32 arch_timer_get_cntfrq (void )
drivers/clocksource/arm_arch_timer.c +8 -0
@@ -112,6 +112,8 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,case ARCH_TIMER_REG_TVAL :writel_relaxed (val, timer->base +CNTP_TVAL );break ; +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_MEM_VIRT_ACCESS ) {struct arch_timer *timer =to_arch_timer (clk);
@@ -122,6 +124,8 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,case ARCH_TIMER_REG_TVAL :writel_relaxed (val, timer->base +CNTV_TVAL );break ; +default : +BUILD_BUG (); } }else {arch_timer_reg_write_cp15 (access, reg, val);
@@ -143,6 +147,8 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,case ARCH_TIMER_REG_TVAL : val =readl_relaxed (timer->base +CNTP_TVAL );break ; +default : +BUILD_BUG (); } }else if (access ==ARCH_TIMER_MEM_VIRT_ACCESS ) {struct arch_timer *timer =to_arch_timer (clk);
@@ -153,6 +159,8 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,case ARCH_TIMER_REG_TVAL : val =readl_relaxed (timer->base +CNTV_TVAL );break ; +default : +BUILD_BUG (); } }else { val =arch_timer_reg_read_cp15 (access, reg);
Marc Zyngier
maintainerPATCH v4 2/17 clocksource/arm_arch_timer: Drop CNT*_TVAL read accessors
In reply to Marc ZyngierThe arch timer driver never reads the various TVAL registers, only writes to them. It is thus pointless to provide accessors for them and to implement errata workarounds.
Drop these read-side accessors, and add a couple of BUG() statements for the time being. These statements will be removed further down the line.
--- arch/arm/include/asm/arch_timer.h | 6 ---- arch/arm64/include/asm/arch_timer.h | 17 ----------- drivers/clocksource/arm_arch_timer.c | 44 ---------------------------- 3 files changed, 67 deletions(-)
arch/arm/include/asm/arch_timer.h +0 -6
@@ -65,9 +65,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)case ARCH_TIMER_REG_CTRL : asmvolatile ("mrc p15, 0, %0, c14, c2, 1" :"=r" (val));break ; -case ARCH_TIMER_REG_TVAL : - asmvolatile ("mrc p15, 0, %0, c14, c2, 0" :"=r" (val)); -break ;default :BUILD_BUG (); }
@@ -76,9 +73,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)case ARCH_TIMER_REG_CTRL : asmvolatile ("mrc p15, 0, %0, c14, c3, 1" :"=r" (val));break ; -case ARCH_TIMER_REG_TVAL : - asmvolatile ("mrc p15, 0, %0, c14, c3, 0" :"=r" (val)); -break ;default :BUILD_BUG (); }
arch/arm64/include/asm/arch_timer.h +0 -17
@@ -52,8 +52,6 @@ struct arch_timer_erratum_workaround {enum arch_timer_erratum_match_type match_type;const void *id;const char *desc; -u32 (*read_cntp_tval_el0)(void); -u32 (*read_cntv_tval_el0)(void);u64 (*read_cntpct_el0)(void);u64 (*read_cntvct_el0)(void);int (*set_next_event_phys)(unsigned long ,struct clock_event_device *);
@@ -64,17 +62,6 @@ struct arch_timer_erratum_workaround { DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); -/* inline sysreg accessors that make erratum_handler() work */ -static inline notrace u32 arch_timer_read_cntp_tval_el0(void) -{ -return read_sysreg (cntp_tval_el0); -} - -static inline notrace u32 arch_timer_read_cntv_tval_el0(void) -{ -return read_sysreg (cntv_tval_el0); -} - static inline notrace u64 arch_timer_read_cntpct_el0(void) {return read_sysreg (cntpct_el0);
@@ -140,8 +127,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)switch (reg) {case ARCH_TIMER_REG_CTRL :return read_sysreg (cntp_ctl_el0); -case ARCH_TIMER_REG_TVAL : -return arch_timer_reg_read_stable (cntp_tval_el0);default :BUILD_BUG (); }
@@ -149,8 +134,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)switch (reg) {case ARCH_TIMER_REG_CTRL :return read_sysreg (cntv_ctl_el0); -case ARCH_TIMER_REG_TVAL : -return arch_timer_reg_read_stable (cntv_tval_el0);default :BUILD_BUG (); }
drivers/clocksource/arm_arch_timer.c +0 -44
98 lines not on this page · raw message
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/drivers/arm_arch_timer: Drop CNT*_TVAL read accessors
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: d72689988d67d56aebf7afb7f609373ea6b548db Gitweb: https://git.kernel.org/tip/d72689988d67d56aebf7afb7f609373ea6b548db Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:10 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Sun, 17 Oct 2021 21:46:50 +02:00
clocksource/drivers/arm_arch_timer: Drop CNT*_TVAL read accessors
The arch timer driver never reads the various TVAL registers, only writes to them. It is thus pointless to provide accessors for them and to implement errata workarounds.
Drop these read-side accessors, and add a couple of BUG() statements for the time being. These statements will be removed further down the line.
--- arch/arm/include/asm/arch_timer.h | 6 +---- arch/arm64/include/asm/arch_timer.h | 17 +---------- drivers/clocksource/arm_arch_timer.c | 44 +--------------------------- 3 files changed, 67 deletions(-)
arch/arm/include/asm/arch_timer.h +0 -6
@@ -65,9 +65,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)case ARCH_TIMER_REG_CTRL : asmvolatile ("mrc p15, 0, %0, c14, c2, 1" :"=r" (val));break ; -case ARCH_TIMER_REG_TVAL : - asmvolatile ("mrc p15, 0, %0, c14, c2, 0" :"=r" (val)); -break ;default :BUILD_BUG (); }
@@ -76,9 +73,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)case ARCH_TIMER_REG_CTRL : asmvolatile ("mrc p15, 0, %0, c14, c3, 1" :"=r" (val));break ; -case ARCH_TIMER_REG_TVAL : - asmvolatile ("mrc p15, 0, %0, c14, c3, 0" :"=r" (val)); -break ;default :BUILD_BUG (); }
arch/arm64/include/asm/arch_timer.h +0 -17
@@ -52,8 +52,6 @@ struct arch_timer_erratum_workaround {enum arch_timer_erratum_match_type match_type;const void *id;const char *desc; -u32 (*read_cntp_tval_el0)(void); -u32 (*read_cntv_tval_el0)(void);u64 (*read_cntpct_el0)(void);u64 (*read_cntvct_el0)(void);int (*set_next_event_phys)(unsigned long ,struct clock_event_device *);
@@ -64,17 +62,6 @@ struct arch_timer_erratum_workaround { DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); -/* inline sysreg accessors that make erratum_handler() work */ -static inline notrace u32 arch_timer_read_cntp_tval_el0(void) -{ -return read_sysreg (cntp_tval_el0); -} - -static inline notrace u32 arch_timer_read_cntv_tval_el0(void) -{ -return read_sysreg (cntv_tval_el0); -} - static inline notrace u64 arch_timer_read_cntpct_el0(void) {return read_sysreg (cntpct_el0);
@@ -140,8 +127,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)switch (reg) {case ARCH_TIMER_REG_CTRL :return read_sysreg (cntp_ctl_el0); -case ARCH_TIMER_REG_TVAL : -return arch_timer_reg_read_stable (cntp_tval_el0);default :BUILD_BUG (); }
@@ -149,8 +134,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)switch (reg) {case ARCH_TIMER_REG_CTRL :return read_sysreg (cntv_ctl_el0); -case ARCH_TIMER_REG_TVAL : -return arch_timer_reg_read_stable (cntv_tval_el0);default :BUILD_BUG (); }
drivers/clocksource/arm_arch_timer.c +0 -44
98 lines not on this page · raw message
Marc Zyngier
maintainerPATCH v4 3/17 clocksource/arm_arch_timer: Extend write side of timer register accessors to u64
In reply to Marc ZyngierThe various accessors for the timer sysreg and MMIO registers are currently hardwired to 32bit. However, we are about to introduce the use of the CVAL registers, which require a 64bit access.
Upgrade the write side of the accessors to take a 64bit value (the read side is left untouched as we don't plan to ever read back any of these registers).
No functional change expected.
--- arch/arm/include/asm/arch_timer.h | 10 +++++----- arch/arm64/include/asm/arch_timer.h | 2 +- drivers/clocksource/arm_arch_timer.c | 10 +++++----- 3 files changed, 11 insertions(+), 11 deletions(-)
arch/arm/include/asm/arch_timer.h +5 -5
@@ -24,15 +24,15 @@ int arch_timer_arch_init(void);* the code. At least it does so with a recent GCC (4.6.3). */ static __always_inline -void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) +void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val) {if (access ==ARCH_TIMER_PHYS_ACCESS ) {switch (reg) {case ARCH_TIMER_REG_CTRL : - asmvolatile ("mcr p15, 0, %0, c14, c2, 1" : :"r" (val)); + asmvolatile ("mcr p15, 0, %0, c14, c2, 1" : :"r" ((u32 )val));break ;case ARCH_TIMER_REG_TVAL : - asmvolatile ("mcr p15, 0, %0, c14, c2, 0" : :"r" (val)); + asmvolatile ("mcr p15, 0, %0, c14, c2, 0" : :"r" ((u32 )val));break ;default :BUILD_BUG ();
@@ -40,10 +40,10 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) }else if (access ==ARCH_TIMER_VIRT_ACCESS ) {switch (reg) {case ARCH_TIMER_REG_CTRL : - asmvolatile ("mcr p15, 0, %0, c14, c3, 1" : :"r" (val)); + asmvolatile ("mcr p15, 0, %0, c14, c3, 1" : :"r" ((u32 )val));break ;case ARCH_TIMER_REG_TVAL : - asmvolatile ("mcr p15, 0, %0, c14, c3, 0" : :"r" (val)); + asmvolatile ("mcr p15, 0, %0, c14, c3, 0" : :"r" ((u32 )val));break ;default :BUILD_BUG ();
arch/arm64/include/asm/arch_timer.h +1 -1
@@ -89,7 +89,7 @@ static inline notrace u64 arch_timer_read_cntvct_el0(void)* the code. */ static __always_inline -void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) +void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val) {if (access ==ARCH_TIMER_PHYS_ACCESS ) {switch (reg) {
drivers/clocksource/arm_arch_timer.c +5 -5
@@ -100,17 +100,17 @@ early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);*/ static __always_inline -void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, +void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,struct clock_event_device *clk) {if (access ==ARCH_TIMER_MEM_PHYS_ACCESS ) {struct arch_timer *timer =to_arch_timer (clk);switch (reg) {case ARCH_TIMER_REG_CTRL : -writel_relaxed (val, timer->base +CNTP_CTL ); +writel_relaxed ((u32 )val, timer->base +CNTP_CTL );break ;case ARCH_TIMER_REG_TVAL : -writel_relaxed (val, timer->base +CNTP_TVAL ); +writel_relaxed ((u32 )val, timer->base +CNTP_TVAL );break ;default :BUILD_BUG ();
@@ -119,10 +119,10 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,struct arch_timer *timer =to_arch_timer (clk);switch (reg) {case ARCH_TIMER_REG_CTRL : -writel_relaxed (val, timer->base +CNTV_CTL ); +writel_relaxed ((u32 )val, timer->base +CNTV_CTL );break ;case ARCH_TIMER_REG_TVAL : -writel_relaxed (val, timer->base +CNTV_TVAL ); +writel_relaxed ((u32 )val, timer->base +CNTV_TVAL );break ;default :BUILD_BUG ();
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/drivers/arm_arch_timer: Extend write side of timer register accessors to u64
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 1e8d929231cf7b397101c5e6aaaa3d9bc9832f10 Gitweb: https://git.kernel.org/tip/1e8d929231cf7b397101c5e6aaaa3d9bc9832f10 Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:11 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Sun, 17 Oct 2021 21:46:59 +02:00
clocksource/drivers/arm_arch_timer: Extend write side of timer register accessors to u64
The various accessors for the timer sysreg and MMIO registers are currently hardwired to 32bit. However, we are about to introduce the use of the CVAL registers, which require a 64bit access.
Upgrade the write side of the accessors to take a 64bit value (the read side is left untouched as we don't plan to ever read back any of these registers).
No functional change expected.
--- arch/arm/include/asm/arch_timer.h | 10 +++++----- arch/arm64/include/asm/arch_timer.h | 2 +- drivers/clocksource/arm_arch_timer.c | 10 +++++----- 3 files changed, 11 insertions(+), 11 deletions(-)
arch/arm/include/asm/arch_timer.h +5 -5
@@ -24,15 +24,15 @@ int arch_timer_arch_init(void);* the code. At least it does so with a recent GCC (4.6.3). */ static __always_inline -void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) +void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val) {if (access ==ARCH_TIMER_PHYS_ACCESS ) {switch (reg) {case ARCH_TIMER_REG_CTRL : - asmvolatile ("mcr p15, 0, %0, c14, c2, 1" : :"r" (val)); + asmvolatile ("mcr p15, 0, %0, c14, c2, 1" : :"r" ((u32 )val));break ;case ARCH_TIMER_REG_TVAL : - asmvolatile ("mcr p15, 0, %0, c14, c2, 0" : :"r" (val)); + asmvolatile ("mcr p15, 0, %0, c14, c2, 0" : :"r" ((u32 )val));break ;default :BUILD_BUG ();
@@ -40,10 +40,10 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) }else if (access ==ARCH_TIMER_VIRT_ACCESS ) {switch (reg) {case ARCH_TIMER_REG_CTRL : - asmvolatile ("mcr p15, 0, %0, c14, c3, 1" : :"r" (val)); + asmvolatile ("mcr p15, 0, %0, c14, c3, 1" : :"r" ((u32 )val));break ;case ARCH_TIMER_REG_TVAL : - asmvolatile ("mcr p15, 0, %0, c14, c3, 0" : :"r" (val)); + asmvolatile ("mcr p15, 0, %0, c14, c3, 0" : :"r" ((u32 )val));break ;default :BUILD_BUG ();
arch/arm64/include/asm/arch_timer.h +1 -1
@@ -89,7 +89,7 @@ static inline notrace u64 arch_timer_read_cntvct_el0(void)* the code. */ static __always_inline -void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) +void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val) {if (access ==ARCH_TIMER_PHYS_ACCESS ) {switch (reg) {
drivers/clocksource/arm_arch_timer.c +5 -5
@@ -100,17 +100,17 @@ early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);*/ static __always_inline -void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, +void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,struct clock_event_device *clk) {if (access ==ARCH_TIMER_MEM_PHYS_ACCESS ) {struct arch_timer *timer =to_arch_timer (clk);switch (reg) {case ARCH_TIMER_REG_CTRL : -writel_relaxed (val, timer->base +CNTP_CTL ); +writel_relaxed ((u32 )val, timer->base +CNTP_CTL );break ;case ARCH_TIMER_REG_TVAL : -writel_relaxed (val, timer->base +CNTP_TVAL ); +writel_relaxed ((u32 )val, timer->base +CNTP_TVAL );break ;default :BUILD_BUG ();
@@ -119,10 +119,10 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,struct arch_timer *timer =to_arch_timer (clk);switch (reg) {case ARCH_TIMER_REG_CTRL : -writel_relaxed (val, timer->base +CNTV_CTL ); +writel_relaxed ((u32 )val, timer->base +CNTV_CTL );break ;case ARCH_TIMER_REG_TVAL : -writel_relaxed (val, timer->base +CNTV_TVAL ); +writel_relaxed ((u32 )val, timer->base +CNTV_TVAL );break ;default :BUILD_BUG ();
Marc Zyngier
maintainerPATCH v4 4/17 clocksource/arm_arch_timer: Move system register timer programming over to CVAL
In reply to Marc ZyngierIn order to cope better with high frequency counters, move the programming of the timers from the countdown timer (TVAL) over to the comparator (CVAL).
The programming model is slightly different, as we now need to read the current counter value to have an absolute deadline instead of a relative one.
There is a small overhead to this change, which we will address in the following patches.
--- arch/arm/include/asm/arch_timer.h | 8 ++++---- arch/arm64/include/asm/arch_timer.h | 10 +++++----- drivers/clocksource/arm_arch_timer.c | 26 +++++++++++++++++++++++--- include/clocksource/arm_arch_timer.h | 1 + 4 files changed, 33 insertions(+), 12 deletions(-)
arch/arm/include/asm/arch_timer.h +4 -4
@@ -31,8 +31,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)case ARCH_TIMER_REG_CTRL : asmvolatile ("mcr p15, 0, %0, c14, c2, 1" : :"r" ((u32 )val));break ; -case ARCH_TIMER_REG_TVAL : - asmvolatile ("mcr p15, 0, %0, c14, c2, 0" : :"r" ((u32 )val)); +case ARCH_TIMER_REG_CVAL : + asmvolatile ("mcrr p15, 2, %Q0, %R0, c14" : :"r" (val));break ;default :BUILD_BUG ();
@@ -42,8 +42,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)case ARCH_TIMER_REG_CTRL : asmvolatile ("mcr p15, 0, %0, c14, c3, 1" : :"r" ((u32 )val));break ; -case ARCH_TIMER_REG_TVAL : - asmvolatile ("mcr p15, 0, %0, c14, c3, 0" : :"r" ((u32 )val)); +case ARCH_TIMER_REG_CVAL : + asmvolatile ("mcrr p15, 3, %Q0, %R0, c14" : :"r" (val));break ;default :BUILD_BUG ();
arch/arm64/include/asm/arch_timer.h +5 -5
@@ -96,8 +96,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)case ARCH_TIMER_REG_CTRL :write_sysreg (val, cntp_ctl_el0);break ; -case ARCH_TIMER_REG_TVAL : -write_sysreg (val, cntp_tval_el0); +case ARCH_TIMER_REG_CVAL : +write_sysreg (val, cntp_cval_el0);break ;default :BUILD_BUG ();
@@ -107,8 +107,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)case ARCH_TIMER_REG_CTRL :write_sysreg (val, cntv_ctl_el0);break ; -case ARCH_TIMER_REG_TVAL : -write_sysreg (val, cntv_tval_el0); +case ARCH_TIMER_REG_CVAL : +write_sysreg (val, cntv_cval_el0);break ;default :BUILD_BUG ();
@@ -121,7 +121,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val) }static __always_inline -u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) +u64 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) {if (access ==ARCH_TIMER_PHYS_ACCESS ) {switch (reg) {
drivers/clocksource/arm_arch_timer.c +23 -3
@@ -691,10 +691,18 @@ static __always_inline void set_next_event(const int access, unsigned long evt, struct clock_event_device *clk) {unsigned long ctrl; +u64 cnt; + ctrl =arch_timer_reg_read (access,ARCH_TIMER_REG_CTRL , clk); ctrl |=ARCH_TIMER_CTRL_ENABLE ; ctrl &= ~ARCH_TIMER_CTRL_IT_MASK ; -arch_timer_reg_write (access,ARCH_TIMER_REG_TVAL , evt, clk); + +if (access ==ARCH_TIMER_PHYS_ACCESS ) + cnt =__arch_counter_get_cntpct (); +else + cnt =__arch_counter_get_cntvct (); + +arch_timer_reg_write (access,ARCH_TIMER_REG_CVAL , evt + cnt, clk);arch_timer_reg_write (access,ARCH_TIMER_REG_CTRL , ctrl, clk); }
@@ -712,17 +720,29 @@ static int arch_timer_set_next_event_phys(unsigned long evt,return 0 ; } +static __always_inline void set_next_event_mem(const int access, unsigned long evt, +struct clock_event_device *clk) +{ +unsigned long ctrl; + ctrl =arch_timer_reg_read (access,ARCH_TIMER_REG_CTRL , clk); + ctrl |=ARCH_TIMER_CTRL_ENABLE ; + ctrl &= ~ARCH_TIMER_CTRL_IT_MASK ; + +arch_timer_reg_write (access,ARCH_TIMER_REG_TVAL , evt, clk); +arch_timer_reg_write (access,ARCH_TIMER_REG_CTRL , ctrl, clk); +} +static int arch_timer_set_next_event_virt_mem (unsigned long evt,struct clock_event_device *clk) { -set_next_event (ARCH_TIMER_MEM_VIRT_ACCESS , evt, clk); +set_next_event_mem (ARCH_TIMER_MEM_VIRT_ACCESS , evt, clk);return 0 ; }static int arch_timer_set_next_event_phys_mem (unsigned long evt,struct clock_event_device *clk) { -set_next_event (ARCH_TIMER_MEM_PHYS_ACCESS , evt, clk); +set_next_event_mem (ARCH_TIMER_MEM_PHYS_ACCESS , evt, clk);return 0 ; }
include/clocksource/arm_arch_timer.h +1 -0
@@ -25,6 +25,7 @@enum arch_timer_reg {ARCH_TIMER_REG_CTRL ,ARCH_TIMER_REG_TVAL , +ARCH_TIMER_REG_CVAL , };enum arch_timer_ppi_nr {
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: a38b71b0833eb2fabd2b1fa37d665c0a88b8b7e4 Gitweb: https://git.kernel.org/tip/a38b71b0833eb2fabd2b1fa37d665c0a88b8b7e4 Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:12 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Sun, 17 Oct 2021 21:47:05 +02:00
clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL
In order to cope better with high frequency counters, move the programming of the timers from the countdown timer (TVAL) over to the comparator (CVAL).
The programming model is slightly different, as we now need to read the current counter value to have an absolute deadline instead of a relative one.
There is a small overhead to this change, which we will address in the following patches.
--- arch/arm/include/asm/arch_timer.h | 8 ++++---- arch/arm64/include/asm/arch_timer.h | 10 +++++----- drivers/clocksource/arm_arch_timer.c | 26 +++++++++++++++++++++++--- include/clocksource/arm_arch_timer.h | 1 + 4 files changed, 33 insertions(+), 12 deletions(-)
arch/arm/include/asm/arch_timer.h +4 -4
@@ -31,8 +31,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)case ARCH_TIMER_REG_CTRL : asmvolatile ("mcr p15, 0, %0, c14, c2, 1" : :"r" ((u32 )val));break ; -case ARCH_TIMER_REG_TVAL : - asmvolatile ("mcr p15, 0, %0, c14, c2, 0" : :"r" ((u32 )val)); +case ARCH_TIMER_REG_CVAL : + asmvolatile ("mcrr p15, 2, %Q0, %R0, c14" : :"r" (val));break ;default :BUILD_BUG ();
@@ -42,8 +42,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)case ARCH_TIMER_REG_CTRL : asmvolatile ("mcr p15, 0, %0, c14, c3, 1" : :"r" ((u32 )val));break ; -case ARCH_TIMER_REG_TVAL : - asmvolatile ("mcr p15, 0, %0, c14, c3, 0" : :"r" ((u32 )val)); +case ARCH_TIMER_REG_CVAL : + asmvolatile ("mcrr p15, 3, %Q0, %R0, c14" : :"r" (val));break ;default :BUILD_BUG ();
arch/arm64/include/asm/arch_timer.h +5 -5
@@ -96,8 +96,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)case ARCH_TIMER_REG_CTRL :write_sysreg (val, cntp_ctl_el0);break ; -case ARCH_TIMER_REG_TVAL : -write_sysreg (val, cntp_tval_el0); +case ARCH_TIMER_REG_CVAL : +write_sysreg (val, cntp_cval_el0);break ;default :BUILD_BUG ();
@@ -107,8 +107,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)case ARCH_TIMER_REG_CTRL :write_sysreg (val, cntv_ctl_el0);break ; -case ARCH_TIMER_REG_TVAL : -write_sysreg (val, cntv_tval_el0); +case ARCH_TIMER_REG_CVAL : +write_sysreg (val, cntv_cval_el0);break ;default :BUILD_BUG ();
@@ -121,7 +121,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val) }static __always_inline -u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) +u64 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) {if (access ==ARCH_TIMER_PHYS_ACCESS ) {switch (reg) {
drivers/clocksource/arm_arch_timer.c +23 -3
@@ -691,10 +691,18 @@ static __always_inline void set_next_event(const int access, unsigned long evt, struct clock_event_device *clk) {unsigned long ctrl; +u64 cnt; + ctrl =arch_timer_reg_read (access,ARCH_TIMER_REG_CTRL , clk); ctrl |=ARCH_TIMER_CTRL_ENABLE ; ctrl &= ~ARCH_TIMER_CTRL_IT_MASK ; -arch_timer_reg_write (access,ARCH_TIMER_REG_TVAL , evt, clk); + +if (access ==ARCH_TIMER_PHYS_ACCESS ) + cnt =__arch_counter_get_cntpct (); +else + cnt =__arch_counter_get_cntvct (); + +arch_timer_reg_write (access,ARCH_TIMER_REG_CVAL , evt + cnt, clk);arch_timer_reg_write (access,ARCH_TIMER_REG_CTRL , ctrl, clk); }
@@ -712,17 +720,29 @@ static int arch_timer_set_next_event_phys(unsigned long evt,return 0 ; } +static __always_inline void set_next_event_mem(const int access, unsigned long evt, +struct clock_event_device *clk) +{ +unsigned long ctrl; + ctrl =arch_timer_reg_read (access,ARCH_TIMER_REG_CTRL , clk); + ctrl |=ARCH_TIMER_CTRL_ENABLE ; + ctrl &= ~ARCH_TIMER_CTRL_IT_MASK ; + +arch_timer_reg_write (access,ARCH_TIMER_REG_TVAL , evt, clk); +arch_timer_reg_write (access,ARCH_TIMER_REG_CTRL , ctrl, clk); +} +static int arch_timer_set_next_event_virt_mem (unsigned long evt,struct clock_event_device *clk) { -set_next_event (ARCH_TIMER_MEM_VIRT_ACCESS , evt, clk); +set_next_event_mem (ARCH_TIMER_MEM_VIRT_ACCESS , evt, clk);return 0 ; }static int arch_timer_set_next_event_phys_mem (unsigned long evt,struct clock_event_device *clk) { -set_next_event (ARCH_TIMER_MEM_PHYS_ACCESS , evt, clk); +set_next_event_mem (ARCH_TIMER_MEM_PHYS_ACCESS , evt, clk);return 0 ; }
include/clocksource/arm_arch_timer.h +1 -0
@@ -25,6 +25,7 @@enum arch_timer_reg {ARCH_TIMER_REG_CTRL ,ARCH_TIMER_REG_TVAL , +ARCH_TIMER_REG_CVAL , };enum arch_timer_ppi_nr {
Marc Zyngier
maintainerPATCH v4 5/17 clocksource/arm_arch_timer: Move drop _tval from erratum function names
In reply to Marc ZyngierThe '_tval' name in the erratum handling function names doesn't make much sense anymore (and they were using CVAL the first place).
Drop the _tval tag.
--- drivers/clocksource/arm_arch_timer.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-)
drivers/clocksource/arm_arch_timer.c +13 -13
@@ -369,7 +369,7 @@ EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);static atomic_t timer_unstable_counter_workaround_in_use =ATOMIC_INIT (0 ); -static void erratum_set_next_event_tval_generic (const int access,unsigned long evt, +static void erratum_set_next_event_generic (const int access,unsigned long evt,struct clock_event_device *clk) {unsigned long ctrl;
@@ -390,17 +390,17 @@ static void erratum_set_next_event_tval_generic(const int access, unsigned longarch_timer_reg_write (access,ARCH_TIMER_REG_CTRL , ctrl, clk); } -static __maybe_unused int erratum_set_next_event_tval_virt (unsigned long evt, +static __maybe_unused int erratum_set_next_event_virt (unsigned long evt,struct clock_event_device *clk) { -erratum_set_next_event_tval_generic (ARCH_TIMER_VIRT_ACCESS , evt, clk); +erratum_set_next_event_generic (ARCH_TIMER_VIRT_ACCESS , evt, clk);return 0 ; } -static __maybe_unused int erratum_set_next_event_tval_phys (unsigned long evt, +static __maybe_unused int erratum_set_next_event_phys (unsigned long evt,struct clock_event_device *clk) { -erratum_set_next_event_tval_generic (ARCH_TIMER_PHYS_ACCESS , evt, clk); +erratum_set_next_event_generic (ARCH_TIMER_PHYS_ACCESS , evt, clk);return 0 ; }
@@ -412,8 +412,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .desc = "Freescale erratum a005858", .read_cntpct_el0 = fsl_a008585_read_cntpct_el0, .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, - .set_next_event_phys = erratum_set_next_event_tval_phys, - .set_next_event_virt = erratum_set_next_event_tval_virt, + .set_next_event_phys = erratum_set_next_event_phys, + .set_next_event_virt = erratum_set_next_event_virt, },#endif #ifdef CONFIG_HISILICON_ERRATUM_161010101
@@ -423,8 +423,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .desc = "HiSilicon erratum 161010101", .read_cntpct_el0 = hisi_161010101_read_cntpct_el0, .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, - .set_next_event_phys = erratum_set_next_event_tval_phys, - .set_next_event_virt = erratum_set_next_event_tval_virt, + .set_next_event_phys = erratum_set_next_event_phys, + .set_next_event_virt = erratum_set_next_event_virt, }, { .match_type = ate_match_acpi_oem_info,
@@ -432,8 +432,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .desc = "HiSilicon erratum 161010101", .read_cntpct_el0 = hisi_161010101_read_cntpct_el0, .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, - .set_next_event_phys = erratum_set_next_event_tval_phys, - .set_next_event_virt = erratum_set_next_event_tval_virt, + .set_next_event_phys = erratum_set_next_event_phys, + .set_next_event_virt = erratum_set_next_event_virt, },#endif #ifdef CONFIG_ARM64_ERRATUM_858921
@@ -452,8 +452,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .desc = "Allwinner erratum UNKNOWN1", .read_cntpct_el0 = sun50i_a64_read_cntpct_el0, .read_cntvct_el0 = sun50i_a64_read_cntvct_el0, - .set_next_event_phys = erratum_set_next_event_tval_phys, - .set_next_event_virt = erratum_set_next_event_tval_virt, + .set_next_event_phys = erratum_set_next_event_phys, + .set_next_event_virt = erratum_set_next_event_virt, },#endif #ifdef CONFIG_ARM64_ERRATUM_1418040
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/drivers/arm_arch_timer: Move drop _tval from erratum function names
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: ac9ef4f24cb2313fb047f2097396204b033799b8 Gitweb: https://git.kernel.org/tip/ac9ef4f24cb2313fb047f2097396204b033799b8 Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:13 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Sun, 17 Oct 2021 21:47:10 +02:00
clocksource/drivers/arm_arch_timer: Move drop _tval from erratum function names
The '_tval' name in the erratum handling function names doesn't make much sense anymore (and they were using CVAL the first place).
Drop the _tval tag.
--- drivers/clocksource/arm_arch_timer.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-)
drivers/clocksource/arm_arch_timer.c +13 -13
@@ -369,7 +369,7 @@ EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);static atomic_t timer_unstable_counter_workaround_in_use =ATOMIC_INIT (0 ); -static void erratum_set_next_event_tval_generic (const int access,unsigned long evt, +static void erratum_set_next_event_generic (const int access,unsigned long evt,struct clock_event_device *clk) {unsigned long ctrl;
@@ -390,17 +390,17 @@ static void erratum_set_next_event_tval_generic(const int access, unsigned longarch_timer_reg_write (access,ARCH_TIMER_REG_CTRL , ctrl, clk); } -static __maybe_unused int erratum_set_next_event_tval_virt (unsigned long evt, +static __maybe_unused int erratum_set_next_event_virt (unsigned long evt,struct clock_event_device *clk) { -erratum_set_next_event_tval_generic (ARCH_TIMER_VIRT_ACCESS , evt, clk); +erratum_set_next_event_generic (ARCH_TIMER_VIRT_ACCESS , evt, clk);return 0 ; } -static __maybe_unused int erratum_set_next_event_tval_phys (unsigned long evt, +static __maybe_unused int erratum_set_next_event_phys (unsigned long evt,struct clock_event_device *clk) { -erratum_set_next_event_tval_generic (ARCH_TIMER_PHYS_ACCESS , evt, clk); +erratum_set_next_event_generic (ARCH_TIMER_PHYS_ACCESS , evt, clk);return 0 ; }
@@ -412,8 +412,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .desc = "Freescale erratum a005858", .read_cntpct_el0 = fsl_a008585_read_cntpct_el0, .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, - .set_next_event_phys = erratum_set_next_event_tval_phys, - .set_next_event_virt = erratum_set_next_event_tval_virt, + .set_next_event_phys = erratum_set_next_event_phys, + .set_next_event_virt = erratum_set_next_event_virt, },#endif #ifdef CONFIG_HISILICON_ERRATUM_161010101
@@ -423,8 +423,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .desc = "HiSilicon erratum 161010101", .read_cntpct_el0 = hisi_161010101_read_cntpct_el0, .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, - .set_next_event_phys = erratum_set_next_event_tval_phys, - .set_next_event_virt = erratum_set_next_event_tval_virt, + .set_next_event_phys = erratum_set_next_event_phys, + .set_next_event_virt = erratum_set_next_event_virt, }, { .match_type = ate_match_acpi_oem_info,
@@ -432,8 +432,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .desc = "HiSilicon erratum 161010101", .read_cntpct_el0 = hisi_161010101_read_cntpct_el0, .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, - .set_next_event_phys = erratum_set_next_event_tval_phys, - .set_next_event_virt = erratum_set_next_event_tval_virt, + .set_next_event_phys = erratum_set_next_event_phys, + .set_next_event_virt = erratum_set_next_event_virt, },#endif #ifdef CONFIG_ARM64_ERRATUM_858921
@@ -452,8 +452,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .desc = "Allwinner erratum UNKNOWN1", .read_cntpct_el0 = sun50i_a64_read_cntpct_el0, .read_cntvct_el0 = sun50i_a64_read_cntvct_el0, - .set_next_event_phys = erratum_set_next_event_tval_phys, - .set_next_event_virt = erratum_set_next_event_tval_virt, + .set_next_event_phys = erratum_set_next_event_phys, + .set_next_event_virt = erratum_set_next_event_virt, },#endif #ifdef CONFIG_ARM64_ERRATUM_1418040
Marc Zyngier
maintainerPATCH v4 6/17 clocksource/arm_arch_timer: Fix MMIO base address vs callback ordering issue
In reply to Marc ZyngierThe MMIO timer base address gets published after we have registered the callbacks and the interrupt handler, which is... a bit dangerous.
Fix this by moving the base address publication to the point where we register the timer, and expose a pointer to the timer structure itself rather than a naked value.
--- drivers/clocksource/arm_arch_timer.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-)
drivers/clocksource/arm_arch_timer.c +13 -14
@@ -54,13 +54,13 @@static unsigned arch_timers_present__initdata ; -static void __iomem *arch_counter_base__ro_after_init ; -struct arch_timer {void __iomem *base;struct clock_event_device evt; }; +static struct arch_timer *arch_timer_mem__ro_after_init ; +#define to_arch_timer (e) container_of(e, struct arch_timer, evt)static u32 arch_timer_rate__ro_after_init ;
@@ -973,9 +973,9 @@ static u64 arch_counter_get_cntvct_mem(void)u32 vct_lo, vct_hi, tmp_hi;do { - vct_hi =readl_relaxed (arch_counter_base +CNTVCT_HI ); - vct_lo =readl_relaxed (arch_counter_base +CNTVCT_LO ); - tmp_hi =readl_relaxed (arch_counter_base +CNTVCT_HI ); + vct_hi =readl_relaxed (arch_timer_mem->base +CNTVCT_HI ); + vct_lo =readl_relaxed (arch_timer_mem->base +CNTVCT_LO ); + tmp_hi =readl_relaxed (arch_timer_mem->base +CNTVCT_HI ); }while (vct_hi != tmp_hi);return ((u64 ) vct_hi <<32 ) | vct_lo;
@@ -1166,25 +1166,25 @@ static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) {int ret;irq_handler_t func; -struct arch_timer *t; - t =kzalloc (sizeof (*t),GFP_KERNEL ); -if (!t) + arch_timer_mem =kzalloc (sizeof (*arch_timer_mem),GFP_KERNEL ); +if (!arch_timer_mem)return -ENOMEM ; - t->base = base; - t->evt.irq = irq; -__arch_timer_setup (ARCH_TIMER_TYPE_MEM , &t->evt); + arch_timer_mem->base = base; + arch_timer_mem->evt.irq = irq; +__arch_timer_setup (ARCH_TIMER_TYPE_MEM , &arch_timer_mem->evt);if (arch_timer_mem_use_virtual) func = arch_timer_handler_virt_mem;else func = arch_timer_handler_phys_mem; - ret =request_irq (irq, func,IRQF_TIMER ,"arch_mem_timer" , &t->evt); + ret =request_irq (irq, func,IRQF_TIMER ,"arch_mem_timer" , &arch_timer_mem->evt);if (ret) {pr_err ("Failed to request mem timer irq\n" ); -kfree (t); +kfree (arch_timer_mem); + arch_timer_mem =NULL ; }return ret;
@@ -1442,7 +1442,6 @@ arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)return ret; } - arch_counter_base = base; arch_timers_present |=ARCH_TIMER_TYPE_MEM ;return 0 ;
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/drivers/arm_arch_timer: Fix MMIO base address vs callback ordering issue
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 72f47a3f0ea4cda4ca5d90c0d6043f697b9b0647 Gitweb: https://git.kernel.org/tip/72f47a3f0ea4cda4ca5d90c0d6043f697b9b0647 Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:14 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Sun, 17 Oct 2021 21:47:15 +02:00
clocksource/drivers/arm_arch_timer: Fix MMIO base address vs callback ordering issue
The MMIO timer base address gets published after we have registered the callbacks and the interrupt handler, which is... a bit dangerous.
Fix this by moving the base address publication to the point where we register the timer, and expose a pointer to the timer structure itself rather than a naked value.
--- drivers/clocksource/arm_arch_timer.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-)
drivers/clocksource/arm_arch_timer.c +13 -14
@@ -54,13 +54,13 @@static unsigned arch_timers_present__initdata ; -static void __iomem *arch_counter_base__ro_after_init ; -struct arch_timer {void __iomem *base;struct clock_event_device evt; }; +static struct arch_timer *arch_timer_mem__ro_after_init ; +#define to_arch_timer (e) container_of(e, struct arch_timer, evt)static u32 arch_timer_rate__ro_after_init ;
@@ -973,9 +973,9 @@ static u64 arch_counter_get_cntvct_mem(void)u32 vct_lo, vct_hi, tmp_hi;do { - vct_hi =readl_relaxed (arch_counter_base +CNTVCT_HI ); - vct_lo =readl_relaxed (arch_counter_base +CNTVCT_LO ); - tmp_hi =readl_relaxed (arch_counter_base +CNTVCT_HI ); + vct_hi =readl_relaxed (arch_timer_mem->base +CNTVCT_HI ); + vct_lo =readl_relaxed (arch_timer_mem->base +CNTVCT_LO ); + tmp_hi =readl_relaxed (arch_timer_mem->base +CNTVCT_HI ); }while (vct_hi != tmp_hi);return ((u64 ) vct_hi <<32 ) | vct_lo;
@@ -1166,25 +1166,25 @@ static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) {int ret;irq_handler_t func; -struct arch_timer *t; - t =kzalloc (sizeof (*t),GFP_KERNEL ); -if (!t) + arch_timer_mem =kzalloc (sizeof (*arch_timer_mem),GFP_KERNEL ); +if (!arch_timer_mem)return -ENOMEM ; - t->base = base; - t->evt.irq = irq; -__arch_timer_setup (ARCH_TIMER_TYPE_MEM , &t->evt); + arch_timer_mem->base = base; + arch_timer_mem->evt.irq = irq; +__arch_timer_setup (ARCH_TIMER_TYPE_MEM , &arch_timer_mem->evt);if (arch_timer_mem_use_virtual) func = arch_timer_handler_virt_mem;else func = arch_timer_handler_phys_mem; - ret =request_irq (irq, func,IRQF_TIMER ,"arch_mem_timer" , &t->evt); + ret =request_irq (irq, func,IRQF_TIMER ,"arch_mem_timer" , &arch_timer_mem->evt);if (ret) {pr_err ("Failed to request mem timer irq\n" ); -kfree (t); +kfree (arch_timer_mem); + arch_timer_mem =NULL ; }return ret;
@@ -1442,7 +1442,6 @@ arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)return ret; } - arch_counter_base = base; arch_timers_present |=ARCH_TIMER_TYPE_MEM ;return 0 ;
Marc Zyngier
maintainerPATCH v4 7/17 clocksource/arm_arch_timer: Move MMIO timer programming over to CVAL
In reply to Marc ZyngierSimilarily to the sysreg-based timer, move the MMIO over to using the CVAL registers instead of TVAL. Note that there is no warranty that the 64bit MMIO access will be atomic, but the timer is always disabled at the point where we program CVAL.
--- arch/arm/include/asm/arch_timer.h | 1 + drivers/clocksource/arm_arch_timer.c | 50 +++++++++++++++++++++------- 2 files changed, 39 insertions(+), 12 deletions(-)
arch/arm/include/asm/arch_timer.h +1 -0
@@ -7,6 +7,7 @@#include <asm/hwcap.h> #include <linux/clocksource.h> #include <linux/init.h> +#include <linux/io-64-nonatomic-lo-hi.h> #include <linux/types.h> #include <clocksource/arm_arch_timer.h>
drivers/clocksource/arm_arch_timer.c +38 -12
91 lines not on this page · raw message
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 8b82c4f883a7b22660464c0232fbdb7a6deb3061 Gitweb: https://git.kernel.org/tip/8b82c4f883a7b22660464c0232fbdb7a6deb3061 Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:15 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Sun, 17 Oct 2021 21:47:21 +02:00
clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL
Similarily to the sysreg-based timer, move the MMIO over to using the CVAL registers instead of TVAL. Note that there is no warranty that the 64bit MMIO access will be atomic, but the timer is always disabled at the point where we program CVAL.
--- arch/arm/include/asm/arch_timer.h | 1 +- drivers/clocksource/arm_arch_timer.c | 50 ++++++++++++++++++++------- 2 files changed, 39 insertions(+), 12 deletions(-)
arch/arm/include/asm/arch_timer.h +1 -0
@@ -7,6 +7,7 @@#include <asm/hwcap.h> #include <linux/clocksource.h> #include <linux/init.h> +#include <linux/io-64-nonatomic-lo-hi.h> #include <linux/types.h> #include <clocksource/arm_arch_timer.h>
drivers/clocksource/arm_arch_timer.c +38 -12
91 lines not on this page · raw message
Marc Zyngier
maintainerPATCH v4 8/17 clocksource/arm_arch_timer: Advertise 56bit timer to the core code
In reply to Marc ZyngierProudly tell the code code that we have a timer able to handle 56 bits deltas.
--- drivers/clocksource/arm_arch_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clocksource/arm_arch_timer.c +1 -1
@@ -834,7 +834,7 @@ static void __arch_timer_setup(unsigned type, clk->set_state_shutdown (clk); -clockevents_config_and_register (clk, arch_timer_rate,0xf ,0x7fffffff ); +clockevents_config_and_register (clk, arch_timer_rate,0xf ,CLOCKSOURCE_MASK (56 )); }static void arch_timer_evtstrm_enable (int divider)
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/drivers/arm_arch_timer: Advertise 56bit timer to the core code
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 30aa08da35e07a51a81d489517a3f6fb5164b09c Gitweb: https://git.kernel.org/tip/30aa08da35e07a51a81d489517a3f6fb5164b09c Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:16 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Sun, 17 Oct 2021 21:47:27 +02:00
clocksource/drivers/arm_arch_timer: Advertise 56bit timer to the core code
Proudly tell the code code that we have a timer able to handle 56 bits deltas.
--- drivers/clocksource/arm_arch_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clocksource/arm_arch_timer.c +1 -1
@@ -834,7 +834,7 @@ static void __arch_timer_setup(unsigned type, clk->set_state_shutdown (clk); -clockevents_config_and_register (clk, arch_timer_rate,0xf ,0x7fffffff ); +clockevents_config_and_register (clk, arch_timer_rate,0xf ,CLOCKSOURCE_MASK (56 )); }static void arch_timer_evtstrm_enable (int divider)
Marc Zyngier
maintainerPATCH v4 9/17 clocksource/arm_arch_timer: Work around broken CVAL implementations
In reply to Marc ZyngierThe Applied Micro XGene-1 SoC has a busted implementation of the CVAL register: it looks like it is based on TVAL instead of the other way around. The net effect of this implementation blunder is that the maximum deadline you can program in the timer is 32bit wide.
Use a MIDR check to notice the broken CPU, and reduce the width of the timer to 32bit.
--- drivers/clocksource/arm_arch_timer.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-)
drivers/clocksource/arm_arch_timer.c +27 -1
@@ -780,9 +780,32 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,return 0 ; } +static u64 __arch_timer_check_delta (void ) +{ +#ifdef CONFIG_ARM64 +const struct midr_range broken_cval_midrs[] = { +/* +* XGene-1 implements CVAL in terms of TVAL, meaning +* that the maximum timer range is 32bit. Shame on them. +*/ +MIDR_ALL_VERSIONS (MIDR_CPU_MODEL (ARM_CPU_IMP_APM , +APM_CPU_PART_POTENZA )), + {}, + }; + +if (is_midr_in_range_list (read_cpuid_id (), broken_cval_midrs)) { +pr_warn_once ("Broken CNTx_CVAL_EL1, limiting width to 32bits" ); +return CLOCKSOURCE_MASK (32 ); + } +#endif +return CLOCKSOURCE_MASK (56 ); +} +static void __arch_timer_setup (unsigned type,struct clock_event_device *clk) { +u64 max_delta; + clk->features =CLOCK_EVT_FEAT_ONESHOT ;if (type ==ARCH_TIMER_TYPE_CP15 ) {
@@ -814,6 +837,7 @@ static void __arch_timer_setup(unsigned type, } clk->set_next_event = sne; + max_delta =__arch_timer_check_delta (); }else { clk->features |=CLOCK_EVT_FEAT_DYNIRQ ; clk->name ="arch_mem_timer" ;
@@ -830,11 +854,13 @@ static void __arch_timer_setup(unsigned type, clk->set_next_event = arch_timer_set_next_event_phys_mem; } + + max_delta =CLOCKSOURCE_MASK (56 ); } clk->set_state_shutdown (clk); -clockevents_config_and_register (clk, arch_timer_rate,0xf ,CLOCKSOURCE_MASK (56 )); +clockevents_config_and_register (clk, arch_timer_rate,0xf , max_delta); }static void arch_timer_evtstrm_enable (int divider)
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/drivers/arm_arch_timer: Work around broken CVAL implementations
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 012f188504528b8cb32f441ac3bd9ea2eba39c9e Gitweb: https://git.kernel.org/tip/012f188504528b8cb32f441ac3bd9ea2eba39c9e Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:17 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Sun, 17 Oct 2021 21:47:31 +02:00
clocksource/drivers/arm_arch_timer: Work around broken CVAL implementations
The Applied Micro XGene-1 SoC has a busted implementation of the CVAL register: it looks like it is based on TVAL instead of the other way around. The net effect of this implementation blunder is that the maximum deadline you can program in the timer is 32bit wide.
Use a MIDR check to notice the broken CPU, and reduce the width of the timer to 32bit.
--- drivers/clocksource/arm_arch_timer.c | 28 ++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-)
drivers/clocksource/arm_arch_timer.c +27 -1
@@ -780,9 +780,32 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,return 0 ; } +static u64 __arch_timer_check_delta (void ) +{ +#ifdef CONFIG_ARM64 +const struct midr_range broken_cval_midrs[] = { +/* +* XGene-1 implements CVAL in terms of TVAL, meaning +* that the maximum timer range is 32bit. Shame on them. +*/ +MIDR_ALL_VERSIONS (MIDR_CPU_MODEL (ARM_CPU_IMP_APM , +APM_CPU_PART_POTENZA )), + {}, + }; + +if (is_midr_in_range_list (read_cpuid_id (), broken_cval_midrs)) { +pr_warn_once ("Broken CNTx_CVAL_EL1, limiting width to 32bits" ); +return CLOCKSOURCE_MASK (32 ); + } +#endif +return CLOCKSOURCE_MASK (56 ); +} +static void __arch_timer_setup (unsigned type,struct clock_event_device *clk) { +u64 max_delta; + clk->features =CLOCK_EVT_FEAT_ONESHOT ;if (type ==ARCH_TIMER_TYPE_CP15 ) {
@@ -814,6 +837,7 @@ static void __arch_timer_setup(unsigned type, } clk->set_next_event = sne; + max_delta =__arch_timer_check_delta (); }else { clk->features |=CLOCK_EVT_FEAT_DYNIRQ ; clk->name ="arch_mem_timer" ;
@@ -830,11 +854,13 @@ static void __arch_timer_setup(unsigned type, clk->set_next_event = arch_timer_set_next_event_phys_mem; } + + max_delta =CLOCKSOURCE_MASK (56 ); } clk->set_state_shutdown (clk); -clockevents_config_and_register (clk, arch_timer_rate,0xf ,CLOCKSOURCE_MASK (56 )); +clockevents_config_and_register (clk, arch_timer_rate,0xf , max_delta); }static void arch_timer_evtstrm_enable (int divider)
Marc Zyngier
maintainerPATCH v4 10/17 clocksource/arm_arch_timer: Remove any trace of the TVAL programming interface
In reply to Marc ZyngierTVAL usage is now long gone, get rid of the leftovers.
--- drivers/clocksource/arm_arch_timer.c | 8 -------- include/clocksource/arm_arch_timer.h | 1 - 2 files changed, 9 deletions(-)
drivers/clocksource/arm_arch_timer.c +0 -8
@@ -48,10 +48,8 @@#define CNTPCT_LO 0x08#define CNTFRQ 0x10#define CNTP_CVAL_LO 0x20 -#define CNTP_TVAL 0x28#define CNTP_CTL 0x2c#define CNTV_CVAL_LO 0x30 -#define CNTV_TVAL 0x38#define CNTV_CTL 0x3cstatic unsigned arch_timers_present__initdata ;
@@ -111,9 +109,6 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,case ARCH_TIMER_REG_CTRL :writel_relaxed ((u32 )val, timer->base +CNTP_CTL );break ; -case ARCH_TIMER_REG_TVAL : -writel_relaxed ((u32 )val, timer->base +CNTP_TVAL ); -break ;case ARCH_TIMER_REG_CVAL :/* * Not guaranteed to be atomic, so the timer
@@ -130,9 +125,6 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,case ARCH_TIMER_REG_CTRL :writel_relaxed ((u32 )val, timer->base +CNTV_CTL );break ; -case ARCH_TIMER_REG_TVAL : -writel_relaxed ((u32 )val, timer->base +CNTV_TVAL ); -break ;case ARCH_TIMER_REG_CVAL :/* Same restriction as above */ writeq_relaxed (val, timer->base +CNTV_CVAL_LO );
include/clocksource/arm_arch_timer.h +0 -1
@@ -24,7 +24,6 @@enum arch_timer_reg {ARCH_TIMER_REG_CTRL , -ARCH_TIMER_REG_TVAL ,ARCH_TIMER_REG_CVAL , };
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/drivers/arm_arch_timer: Remove any trace of the TVAL programming interface
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 41f8d02a6a558f80775bf61fe6312a14eeabbca0 Gitweb: https://git.kernel.org/tip/41f8d02a6a558f80775bf61fe6312a14eeabbca0 Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:18 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Sun, 17 Oct 2021 21:47:39 +02:00
clocksource/drivers/arm_arch_timer: Remove any trace of the TVAL programming interface
TVAL usage is now long gone, get rid of the leftovers.
--- drivers/clocksource/arm_arch_timer.c | 8 -------- include/clocksource/arm_arch_timer.h | 1 - 2 files changed, 9 deletions(-)
drivers/clocksource/arm_arch_timer.c +0 -8
@@ -48,10 +48,8 @@#define CNTPCT_LO 0x08#define CNTFRQ 0x10#define CNTP_CVAL_LO 0x20 -#define CNTP_TVAL 0x28#define CNTP_CTL 0x2c#define CNTV_CVAL_LO 0x30 -#define CNTV_TVAL 0x38#define CNTV_CTL 0x3cstatic unsigned arch_timers_present__initdata ;
@@ -111,9 +109,6 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,case ARCH_TIMER_REG_CTRL :writel_relaxed ((u32 )val, timer->base +CNTP_CTL );break ; -case ARCH_TIMER_REG_TVAL : -writel_relaxed ((u32 )val, timer->base +CNTP_TVAL ); -break ;case ARCH_TIMER_REG_CVAL :/* * Not guaranteed to be atomic, so the timer
@@ -130,9 +125,6 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,case ARCH_TIMER_REG_CTRL :writel_relaxed ((u32 )val, timer->base +CNTV_CTL );break ; -case ARCH_TIMER_REG_TVAL : -writel_relaxed ((u32 )val, timer->base +CNTV_TVAL ); -break ;case ARCH_TIMER_REG_CVAL :/* Same restriction as above */ writeq_relaxed (val, timer->base +CNTV_CVAL_LO );
include/clocksource/arm_arch_timer.h +0 -1
@@ -24,7 +24,6 @@enum arch_timer_reg {ARCH_TIMER_REG_CTRL , -ARCH_TIMER_REG_TVAL ,ARCH_TIMER_REG_CVAL , };
Marc Zyngier
maintainerPATCH v4 11/17 clocksource/arm_arch_timer: Drop unnecessary ISB on CVAL programming
In reply to Marc ZyngierSwitching from TVAL to CVAL has a small drawback: we need an ISB before reading the counter. We cannot get rid of it, but we can instead remove the one that comes just after writing to CVAL.
This reduces the number of ISBs from 3 to 2 when programming the timer.
--- arch/arm/include/asm/arch_timer.h | 4 ++-- arch/arm64/include/asm/arch_timer.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/include/asm/arch_timer.h +2 -2
@@ -31,6 +31,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)switch (reg) {case ARCH_TIMER_REG_CTRL : asmvolatile ("mcr p15, 0, %0, c14, c2, 1" : :"r" ((u32 )val)); +isb ();break ;case ARCH_TIMER_REG_CVAL : asmvolatile ("mcrr p15, 2, %Q0, %R0, c14" : :"r" (val));
@@ -42,6 +43,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)switch (reg) {case ARCH_TIMER_REG_CTRL : asmvolatile ("mcr p15, 0, %0, c14, c3, 1" : :"r" ((u32 )val)); +isb ();break ;case ARCH_TIMER_REG_CVAL : asmvolatile ("mcrr p15, 3, %Q0, %R0, c14" : :"r" (val));
@@ -52,8 +54,6 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val) }else {BUILD_BUG (); } - -isb (); } static __always_inline
arch/arm64/include/asm/arch_timer.h +2 -2
@@ -95,6 +95,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)switch (reg) {case ARCH_TIMER_REG_CTRL :write_sysreg (val, cntp_ctl_el0); +isb ();break ;case ARCH_TIMER_REG_CVAL :write_sysreg (val, cntp_cval_el0);
@@ -106,6 +107,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)switch (reg) {case ARCH_TIMER_REG_CTRL :write_sysreg (val, cntv_ctl_el0); +isb ();break ;case ARCH_TIMER_REG_CVAL :write_sysreg (val, cntv_cval_el0);
@@ -116,8 +118,6 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val) }else {BUILD_BUG (); } - -isb (); } static __always_inline
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/drivers/arm_arch_timer: Drop unnecessary ISB on CVAL programming
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: ec8f7f3342c88780d682cc2464daf0fe43259c4f Gitweb: https://git.kernel.org/tip/ec8f7f3342c88780d682cc2464daf0fe43259c4f Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:19 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Sun, 17 Oct 2021 21:47:44 +02:00
clocksource/drivers/arm_arch_timer: Drop unnecessary ISB on CVAL programming
Switching from TVAL to CVAL has a small drawback: we need an ISB before reading the counter. We cannot get rid of it, but we can instead remove the one that comes just after writing to CVAL.
This reduces the number of ISBs from 3 to 2 when programming the timer.
--- arch/arm/include/asm/arch_timer.h | 4 ++-- arch/arm64/include/asm/arch_timer.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/include/asm/arch_timer.h +2 -2
@@ -31,6 +31,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)switch (reg) {case ARCH_TIMER_REG_CTRL : asmvolatile ("mcr p15, 0, %0, c14, c2, 1" : :"r" ((u32 )val)); +isb ();break ;case ARCH_TIMER_REG_CVAL : asmvolatile ("mcrr p15, 2, %Q0, %R0, c14" : :"r" (val));
@@ -42,6 +43,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)switch (reg) {case ARCH_TIMER_REG_CTRL : asmvolatile ("mcr p15, 0, %0, c14, c3, 1" : :"r" ((u32 )val)); +isb ();break ;case ARCH_TIMER_REG_CVAL : asmvolatile ("mcrr p15, 3, %Q0, %R0, c14" : :"r" (val));
@@ -52,8 +54,6 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val) }else {BUILD_BUG (); } - -isb (); } static __always_inline
arch/arm64/include/asm/arch_timer.h +2 -2
@@ -95,6 +95,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)switch (reg) {case ARCH_TIMER_REG_CTRL :write_sysreg (val, cntp_ctl_el0); +isb ();break ;case ARCH_TIMER_REG_CVAL :write_sysreg (val, cntp_cval_el0);
@@ -106,6 +107,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)switch (reg) {case ARCH_TIMER_REG_CTRL :write_sysreg (val, cntv_ctl_el0); +isb ();break ;case ARCH_TIMER_REG_CVAL :write_sysreg (val, cntv_cval_el0);
@@ -116,8 +118,6 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val) }else {BUILD_BUG (); } - -isb (); } static __always_inline
Marc Zyngier
maintainerPATCH v4 12/17 clocksource/arm_arch_timer: Fix masking for high freq counters
In reply to Marc ZyngierFrom: Oliver Upton <[email protected]>
Unfortunately, the architecture provides no means to determine the bit width of the system counter. However, we do know the following from the specification:
- the system counter is at least 56 bits wide
- Roll-over time of not less than 40 years
To date, the arch timer driver has depended on the first property, assuming any system counter to be 56 bits wide and masking off the rest. However, combining a narrow clocksource mask with a high frequency counter could result in prematurely wrapping the system counter by a significant margin. For example, a 56 bit wide, 1GHz system counter would wrap in a mere 2.28 years!
This is a problem for two reasons: v8.6+ implementations are required to provide a 64 bit, 1GHz system counter. Furthermore, before v8.6, implementers may select a counter frequency of their choosing.
Fix the issue by deriving a valid clock mask based on the second property from above. Set the floor at 56 bits, since we know no system counter is narrower than that.
[maz: fixed width computation not to lose the last bit, added
max delta generation for the timer]
--- drivers/clocksource/arm_arch_timer.c | 34 ++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 5 deletions(-)
drivers/clocksource/arm_arch_timer.c +29 -5
@@ -52,6 +52,12 @@#define CNTV_CVAL_LO 0x30#define CNTV_CTL 0x3c +/* +* The minimum amount of time a generic counter is guaranteed to not roll over +* (40 years) +*/ +#define MIN_ROLLOVER_SECS (40ULL * 365 * 24 * 3600) +static unsigned arch_timers_present__initdata ;struct arch_timer {
@@ -95,6 +101,22 @@ static int __init early_evtstrm_cfg(char *buf) }early_param ("clocksource.arm_arch_timer.evtstrm" , early_evtstrm_cfg); +/* +* Makes an educated guess at a valid counter width based on the Generic Timer +* specification. Of note: +* 1) the system counter is at least 56 bits wide +* 2) a roll-over time of not less than 40 years +* +* See 'ARM DDI 0487G.a D11.1.2 ("The system counter")' for more details. +*/ +static int arch_counter_get_width (void ) +{ +u64 min_cycles =MIN_ROLLOVER_SECS * arch_timer_rate; + +/* guarantee the returned width is within the valid range */ +return clamp_val (ilog2 (min_cycles -1 ) +1 ,56 ,64 ); +} +/* * Architected system timer support. */
@@ -212,13 +234,11 @@ static struct clocksource clocksource_counter = { .id = CSID_ARM_ARCH_COUNTER, .rating = 400, .read = arch_counter_read, - .mask = CLOCKSOURCE_MASK(56), .flags = CLOCK_SOURCE_IS_CONTINUOUS, };static struct cyclecounter cyclecounter__ro_after_init = { .read = arch_counter_read_cc, - .mask =CLOCKSOURCE_MASK (56 ), };struct ate_acpi_oem_info {
@@ -790,7 +810,7 @@ static u64 __arch_timer_check_delta(void)return CLOCKSOURCE_MASK (32 ); }#endif -return CLOCKSOURCE_MASK (56 ); +return CLOCKSOURCE_MASK (arch_counter_get_width ()); } static void __arch_timer_setup(unsigned type,
@@ -1035,6 +1055,7 @@ struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)static void __init arch_counter_register (unsigned type) {u64 start_count; +int width;/* Register the CP15 based counter if we have one */ if (type &ARCH_TIMER_TYPE_CP15 ) {
@@ -1059,6 +1080,10 @@ static void __init arch_counter_register(unsigned type) arch_timer_read_counter = arch_counter_get_cntvct_mem; } + width =arch_counter_get_width (); + clocksource_counter.mask =CLOCKSOURCE_MASK (width); + cyclecounter.mask =CLOCKSOURCE_MASK (width); +if (!arch_counter_suspend_stop) clocksource_counter.flags |=CLOCK_SOURCE_SUSPEND_NONSTOP ; start_count =arch_timer_read_counter ();
@@ -1068,8 +1093,7 @@ static void __init arch_counter_register(unsigned type)timecounter_init (&arch_timer_kvm_info.timecounter, &cyclecounter, start_count); -/* 56 bits minimum, so we assume worst case rollover */ -sched_clock_register (arch_timer_read_counter,56 , arch_timer_rate); +sched_clock_register (arch_timer_read_counter, width, arch_timer_rate); }static void arch_timer_stop (struct clock_event_device *clk)
Signature · 1 line
2.30.2
Marc Zyngier
maintainerPATCH v4 13/17 clocksource/arch_arm_timer: Move workaround synchronisation around
In reply to Marc ZyngierWe currently handle synchronisation when workarounds are enabled by having an ISB in the __arch_counter_get_cnt?ct_stable() helpers.
While this works, this prevents us from relaxing this synchronisation.
Instead, move it closer to the point where the synchronisation is actually needed. Further patches will subsequently relax this.
--- arch/arm64/include/asm/arch_timer.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
arch/arm64/include/asm/arch_timer.h +3 -3
@@ -32,7 +32,7 @@ ({ \ const struct arch_timer_erratum_workaround *__wa; \ __wa = __this_cpu_read(timer_unstable_counter_workaround); \ - (__wa && __wa->h) ? __wa->h : arch_timer_##h; \ + (__wa && __wa->h) ? ({ isb(); __wa->h;}) : arch_timer_##h; \ }) #else
@@ -64,11 +64,13 @@ DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *, static inline notrace u64 arch_timer_read_cntpct_el0(void) { +isb ();return read_sysreg (cntpct_el0); } static inline notrace u64 arch_timer_read_cntvct_el0(void) { +isb ();return read_sysreg (cntvct_el0); }
@@ -163,7 +165,6 @@ static __always_inline u64 __arch_counter_get_cntpct_stable(void) {u64 cnt; -isb (); cnt =arch_timer_reg_read_stable (cntpct_el0);arch_counter_enforce_ordering (cnt);return cnt;
@@ -183,7 +184,6 @@ static __always_inline u64 __arch_counter_get_cntvct_stable(void) {u64 cnt; -isb (); cnt =arch_timer_reg_read_stable (cntvct_el0);arch_counter_enforce_ordering (cnt);return cnt;
Signature · 1 line
2.30.2
[tip: timers/core] clocksource/drivers/arch_arm_timer: Move workaround synchronisation around
The following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: db26f8f2da92471e9f7f71ec78d6fa455cd9c821 Gitweb: https://git.kernel.org/tip/db26f8f2da92471e9f7f71ec78d6fa455cd9c821 Author: Marc Zyngier <[email protected]> AuthorDate: Sun, 17 Oct 2021 13:42:21 +01:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Mon, 18 Oct 2021 09:20:57 +02:00
clocksource/drivers/arch_arm_timer: Move workaround synchronisation around
We currently handle synchronisation when workarounds are enabled by having an ISB in the __arch_counter_get_cnt?ct_stable() helpers.
While this works, this prevents us from relaxing this synchronisation.
Instead, move it closer to the point where the synchronisation is actually needed. Further patches will subsequently relax this.
--- arch/arm64/include/asm/arch_timer.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
arch/arm64/include/asm/arch_timer.h +3 -3
@@ -32,7 +32,7 @@ ({ \ const struct arch_timer_erratum_workaround *__wa; \ __wa = __this_cpu_read(timer_unstable_counter_workaround); \ - (__wa && __wa->h) ? __wa->h : arch_timer_##h; \ + (__wa && __wa->h) ? ({ isb(); __wa->h;}) : arch_timer_##h; \ }) #else
@@ -64,11 +64,13 @@ DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *, static inline notrace u64 arch_timer_read_cntpct_el0(void) { +isb ();return read_sysreg (cntpct_el0); } static inline notrace u64 arch_timer_read_cntvct_el0(void) { +isb ();return read_sysreg (cntvct_el0); }
@@ -163,7 +165,6 @@ static __always_inline u64 __arch_counter_get_cntpct_stable(void) {u64 cnt; -isb (); cnt =arch_timer_reg_read_stable (cntpct_el0);arch_counter_enforce_ordering (cnt);return cnt;
@@ -183,7 +184,6 @@ static __always_inline u64 __arch_counter_get_cntvct_stable(void) {u64 cnt; -isb (); cnt =arch_timer_reg_read_stable (cntvct_el0);arch_counter_enforce_ordering (cnt);return cnt;
Marc Zyngier
maintainerPATCH v4 14/17 arm64: Add a capability for FEAT_ECV
In reply to Marc ZyngierAdd a new capability to detect the Enhanced Counter Virtualization feature (FEAT_ECV).
--- arch/arm64/kernel/cpufeature.c | 10 ++++++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 11 insertions(+)
arch/arm64/kernel/cpufeature.c +10 -0
@@ -1926,6 +1926,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .min_field_value = 1, }, + { + .desc = "Enhanced Counter Virtualization", + .capability = ARM64_HAS_ECV, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .matches = has_cpuid_feature, + .sys_reg = SYS_ID_AA64MMFR0_EL1, + .field_pos = ID_AA64MMFR0_ECV_SHIFT, + .sign = FTR_UNSIGNED, + .min_field_value = 1, + }, #ifdef CONFIG_ARM64_PAN { .desc = "Privileged Access Never",
arch/arm64/tools/cpucaps +1 -0
@@ -18,6 +18,7 @@ HAS_CRC32 HAS_DCPODP HAS_DCPOP HAS_E0PD +HAS_ECV HAS_EPAN HAS_GENERIC_AUTH HAS_GENERIC_AUTH_ARCH
Signature · 1 line
2.30.2
Marc Zyngier
maintainerPATCH v4 15/17 arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0
In reply to Marc ZyngierCNTPCTSS_EL0 and CNTVCTSS_EL0 are alternatives to the usual CNTPCT_EL0 and CNTVCT_EL0 that do not require a previous ISB to be synchronised (SS stands for Self-Synchronising).
Use the ARM64_HAS_ECV capability to control alternative sequences that switch to these low(er)-cost primitives. Note that the counter access in the VDSO is for now left alone until we decide whether we want to allow this.
--- arch/arm64/include/asm/arch_timer.h | 32 +++++++++++++++++++++-------- arch/arm64/include/asm/sysreg.h | 3 +++ 2 files changed, 27 insertions(+), 8 deletions(-)
arch/arm64/include/asm/arch_timer.h +24 -8
@@ -64,14 +64,26 @@ DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *, static inline notrace u64 arch_timer_read_cntpct_el0(void) { -isb (); -return read_sysreg (cntpct_el0); +u64 cnt; + + asm volatile(ALTERNATIVE("isb\n mrs %0, cntpct_el0", + "nop\n" __mrs_s("%0", SYS_CNTPCTSS_EL0), + ARM64_HAS_ECV) + : "=r" (cnt)); + +return cnt; } static inline notrace u64 arch_timer_read_cntvct_el0(void) { -isb (); -return read_sysreg (cntvct_el0); +u64 cnt; + + asm volatile(ALTERNATIVE("isb\n mrs %0, cntvct_el0", + "nop\n" __mrs_s("%0", SYS_CNTVCTSS_EL0), + ARM64_HAS_ECV) + : "=r" (cnt)); + +return cnt; }#define arch_timer_reg_read_stable (reg) \
@@ -174,8 +186,10 @@ static __always_inline u64 __arch_counter_get_cntpct(void) {u64 cnt; -isb (); - cnt =read_sysreg (cntpct_el0); + asm volatile(ALTERNATIVE("isb\n mrs %0, cntpct_el0", + "nop\n" __mrs_s("%0", SYS_CNTPCTSS_EL0), + ARM64_HAS_ECV) + : "=r" (cnt));arch_counter_enforce_ordering (cnt);return cnt; }
@@ -193,8 +207,10 @@ static __always_inline u64 __arch_counter_get_cntvct(void) {u64 cnt; -isb (); - cnt =read_sysreg (cntvct_el0); + asm volatile(ALTERNATIVE("isb\n mrs %0, cntvct_el0", + "nop\n" __mrs_s("%0", SYS_CNTVCTSS_EL0), + ARM64_HAS_ECV) + : "=r" (cnt));arch_counter_enforce_ordering (cnt);return cnt; }
arch/arm64/include/asm/sysreg.h +3 -0
@@ -507,6 +507,9 @@#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) +#define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5) +#define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6) +#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)#define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)#define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
Signature · 1 line
2.30.2
Marc Zyngier
maintainerPATCH v4 16/17 arm64: Add handling of CNTVCTSS traps
In reply to Marc ZyngierSince CNTVCTSS obey the same control bits as CNTVCT, add the necessary decoding to the hook table. Note that there is no known user of this at the moment.
--- arch/arm64/include/asm/esr.h | 6 ++++++ arch/arm64/kernel/traps.c | 11 +++++++++++ 2 files changed, 17 insertions(+)
arch/arm64/include/asm/esr.h +6 -0
@@ -227,6 +227,9 @@#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ ESR_ELx_SYS64_ISS_DIR_READ) +#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \ + ESR_ELx_SYS64_ISS_DIR_READ) +#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ ESR_ELx_SYS64_ISS_DIR_READ)
@@ -317,6 +320,9 @@#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ ESR_ELx_CP15_64_ISS_DIR_READ) +#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \ + ESR_ELx_CP15_64_ISS_DIR_READ) +#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ ESR_ELx_CP15_32_ISS_DIR_READ)
arch/arm64/kernel/traps.c +11 -0
@@ -653,6 +653,12 @@ static const struct sys64_hook sys64_hooks[] = { .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, .handler = cntvct_read_handler, }, + { +/* Trap read access to CNTVCTSS_EL0 */ + .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, + .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCTSS, + .handler = cntvct_read_handler, + }, {/* Trap read access to CNTFRQ_EL0 */ .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
@@ -729,6 +735,11 @@ static const struct sys64_hook cp15_64_hooks[] = { .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, .handler = compat_cntvct_read_handler, }, + { + .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, + .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS, + .handler = compat_cntvct_read_handler, + }, {}, };
Signature · 1 line
2.30.2
Marc Zyngier
maintainerPATCH v4 17/17 arm64: Add HWCAP for self-synchronising virtual counter
In reply to Marc ZyngierSince userspace can make use of the CNTVSS_EL0 instruction, expose it via a HWCAP.
--- Documentation/arm64/cpu-feature-registers.rst | 12 ++++++++++-- Documentation/arm64/elf_hwcaps.rst | 4 ++++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 3 ++- arch/arm64/kernel/cpuinfo.c | 1 + 6 files changed, 19 insertions(+), 3 deletions(-)
Documentation/arm64/cpu-feature-registers.rst +10 -2
@@ -235,7 +235,15 @@ infrastructure: | DPB | [3-0] | y | +------------------------------+---------+---------+ - 6) ID_AA64MMFR2_EL1 - Memory model feature register 2 + 6) ID_AA64MMFR0_EL1 - Memory model feature register 0 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | ECV | [63-60] | y | + +------------------------------+---------+---------+ + + 7) ID_AA64MMFR2_EL1 - Memory model feature register 2 +------------------------------+---------+---------+ | Name | bits | visible |
@@ -243,7 +251,7 @@ infrastructure: | AT | [35-32] | y | +------------------------------+---------+---------+ - 7) ID_AA64ZFR0_EL1 - SVE feature ID register 0 + 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0 +------------------------------+---------+---------+ | Name | bits | visible |
Documentation/arm64/elf_hwcaps.rst +4 -0
@@ -247,6 +247,10 @@ HWCAP2_MTE Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described by Documentation/arm64/memory-tagging-extension.rst. +HWCAP2_ECV + + Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. + 4. Unused AT_HWCAP bits -----------------------
arch/arm64/include/asm/hwcap.h +1 -0
@@ -105,6 +105,7 @@#define KERNEL_HWCAP_RNG __khwcap2_feature(RNG)#define KERNEL_HWCAP_BTI __khwcap2_feature(BTI)#define KERNEL_HWCAP_MTE __khwcap2_feature(MTE) +#define KERNEL_HWCAP_ECV __khwcap2_feature(ECV)/* * This yields a mask that user programs can use to figure out what
arch/arm64/include/uapi/asm/hwcap.h +1 -0
@@ -75,5 +75,6 @@#define HWCAP2_RNG (1 << 16)#define HWCAP2_BTI (1 << 17)#define HWCAP2_MTE (1 << 18) +#define HWCAP2_ECV (1 << 19)#endif /* _UAPI__ASM_HWCAP_H */
arch/arm64/kernel/cpufeature.c +2 -1
@@ -279,7 +279,7 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { };static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { -ARM64_FTR_BITS (FTR_HIDDEN ,FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64MMFR0_ECV_SHIFT ,4 ,0 ), +ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64MMFR0_ECV_SHIFT ,4 ,0 ),ARM64_FTR_BITS (FTR_HIDDEN ,FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64MMFR0_FGT_SHIFT ,4 ,0 ),ARM64_FTR_BITS (FTR_HIDDEN ,FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64MMFR0_EXS_SHIFT ,4 ,0 ),/*
@@ -2457,6 +2457,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {#ifdef CONFIG_ARM64_MTE HWCAP_CAP (SYS_ID_AA64PFR1_EL1 ,ID_AA64PFR1_MTE_SHIFT ,FTR_UNSIGNED ,ID_AA64PFR1_MTE ,CAP_HWCAP ,KERNEL_HWCAP_MTE ), #endif /* CONFIG_ARM64_MTE */ + HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), {}, };
arch/arm64/kernel/cpuinfo.c +1 -0
@@ -94,6 +94,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_RNG] = "rng", [KERNEL_HWCAP_BTI] = "bti", [KERNEL_HWCAP_MTE] = "mte", + [KERNEL_HWCAP_ECV] = "ecv", };#ifdef CONFIG_COMPAT
Signature · 1 line
2.30.2
Will Deacon
maintainerQuoted 11 lines · Marc Zyngier
This is v4 (final?) of the series enabling ARMv8.6 support for timer subsystem, and was prompted by a discussion with Oliver around the fact that an ARMv8.6 implementation must have a 1GHz counter, which leads to a number of things to break in the timer code:
- the counter rollover can come pretty quickly as we only advertise a 56bit counter,
- the maximum timer delta can be remarkably small, as we use the countdown interface which is limited to 32bit...[...]
Applied 14-17 to arm64 (for-next/8.6-timers), thanks!
[14/17] arm64: Add a capability for FEAT_ECV
https://git.kernel.org/arm64/c/fdf865988b5a [15/17] arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0 https://git.kernel.org/arm64/c/9ee840a96042 [16/17] arm64: Add handling of CNTVCTSS traps https://git.kernel.org/arm64/c/ae976f063b60 [17/17] arm64: Add HWCAP for self-synchronising virtual counter https://git.kernel.org/arm64/c/fee29f008aa3
Cheers,
Signature · 5 lines
Will https://fixes.arm64.dev https://next.arm64.dev https://will.arm64.dev
[tip: timers/core] Merge branch 'timers/drivers/armv8.6_arch_timer' into timers/drivers/next
In reply to Marc ZyngierThe following commit has been merged into the timers/core branch of tip:
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 32cf6d0ae0d86a31aa21b5d8ce6820486027c254 Gitweb: https://git.kernel.org/tip/32cf6d0ae0d86a31aa21b5d8ce6820486027c254 Author: Daniel Lezcano <[email protected]> AuthorDate: Tue, 19 Oct 2021 10:07:28 +02:00 Committer: Daniel Lezcano <[email protected]> CommitterDate: Tue, 19 Oct 2021 10:07:28 +02:00
Merge branch 'timers/drivers/armv8.6_arch_timer' into timers/drivers/next
The branch is a stable branch shared with ARM maintainers for the first 13th patches of the series:
It is based on v5.14-rc3.
As stated by the changelog:
" [... ] enabling ARMv8.6 support for timer subsystem, and was prompted by a discussion with Oliver around the fact that an ARMv8.6 implementation must have a 1GHz counter, which leads to a number of things to break in the timer code:
- the counter rollover can come pretty quickly as we only advertise a 56bit counter,
- the maximum timer delta can be remarkably small, as we use the countdown interface which is limited to 32bit...
Thankfully, there is a way out: we can compute the minimal width of the counter based on the guarantees that the architecture gives us, and we can use the 64bit comparator interface instead of the countdown to program the timer.
Finally, we start making use of the ARMv8.6 ECV features by switching accesses to the counters to a self-synchronising register, removing the need for an ISB. Hopefully, implementations will *not* just stick an invisible ISB there...
A side effect of the switch to CVAL is that XGene-1 breaks. I have added a workaround to keep it alive.
I have added Oliver's original patch[0] to the series and tweaked a couple of things. Blame me if I broke anything.
The whole things has been tested on Juno (sysreg + MMIO timers), XGene-1 (broken sysreg timers), FVP (FEAT_ECV, CNT*CTSS_EL0). "
---