Add Sunplus SP7021 SoC Support
Subsystems (7)
Qin Jian
maintainerv2 cover Add Sunplus SP7021 SoC Support
This patch series add Sunplus SP7021 SoC support.
Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates many peripherals (ex: UART, I2C, SPI, SDIO, eMMC, USB, SD card and etc.) into a single chip. It is designed for industrial control.
SP7021 consists of two chips (dies) in a package. One is called C-chip (computing chip). It is a 4-core ARM Cortex A7 CPU. It adopts high-level process (22 nm) for high performance computing. The other is called P- chip (peripheral chip). It has many peripherals and an ARM A926 added especially for real-time control. P-chip is made for customers. It adopts low-level process (ex: 0.11 um) to reduce cost.
Refer to (for documentations):
https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
Refer to (applications):
https://tibbo.com/store/plus1.html
Refer to (applications):
http://www.sinovoip.com.cn/ecp_view.asp?id=586
Changes in v2:
- sunplus,sp7021-intc.yaml: add descrption for "#interrupt-cells", interrupts
- sunplus,sp7021-intc.yaml: drop "ext0-mask"/"ext1-mask" from DT
- sunplus,sp7021-intc.yaml: fix example.dt too long error
- irq-sp7021-intc.c: major rewrite
- all files with dual license
Qin Jian (8):
dt-bindings: vendor-prefixes: Add Sunplus
dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards
dt-bindings: reset: Add bindings for SP7021 reset driver
reset: Add Sunplus SP7021 reset driver
dt-bindings: clock: Add bindings for SP7021 clock driver
clk: Add Sunplus SP7021 clock driver
dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt
controller
irqchip: Add support for Sunplus SP7021 interrupt controller
.../bindings/arm/sunplus,sp7021.yaml | 27 + .../bindings/clock/sunplus,sp7021-clkc.yaml | 38 + .../sunplus,sp7021-intc.yaml | 59 ++ .../bindings/reset/sunplus,reset.yaml | 40 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + MAINTAINERS | 16 + drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk-sp7021.c | 770 ++++++++++++++++++ drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sp7021-intc.c | 324 ++++++++ drivers/reset/Kconfig | 9 + drivers/reset/Makefile | 1 + drivers/reset/reset-sunplus.c | 159 ++++ include/dt-bindings/clock/sp-sp7021.h | 112 +++ .../interrupt-controller/sp7021-intc.h | 24 + include/dt-bindings/reset/sp-sp7021.h | 99 +++ 18 files changed, 1699 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml create mode 100644 drivers/clk/clk-sp7021.c create mode 100644 drivers/irqchip/irq-sp7021-intc.c create mode 100644 drivers/reset/reset-sunplus.c create mode 100644 include/dt-bindings/clock/sp-sp7021.h create mode 100644 include/dt-bindings/interrupt-controller/sp7021-intc.h create mode 100644 include/dt-bindings/reset/sp-sp7021.h
--
2.33.1
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Qin Jian
maintainerPATCH v2 1/8 dt-bindings: vendor-prefixes: Add Sunplus
Add vendor prefix for Sunplus Technology Co., Ltd. (http://www.sunplus.com)
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/vendor-prefixes.yaml +2 -0
@@ -1131,6 +1131,8 @@ patternProperties: description: Summit microelectronics "^sunchip,.*": description: Shenzhen Sunchip Technology Co., Ltd + "^sunplus,.*": + description: Sunplus Technology Co., Ltd. "^SUNW,.*": description: Sun Microsystems, Inc "^supermicro,.*":
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Qin Jian
maintainerPATCH v2 2/8 dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards
In reply to Qin JianThis introduces bindings for boards based Sunplus SP7021 SoC.
--- .../bindings/arm/sunplus,sp7021.yaml | 27 +++++++++++++++++++ MAINTAINERS | 7 +++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml new file +27 -0
@@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Boards Device Tree Bindings + +maintainers: + - qinjian <[email protected]> + +description: | + ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC. + Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sunplus,sp7021-achip + +additionalProperties: true + +...
MAINTAINERS +7 -0
@@ -2655,6 +2655,13 @@ F: drivers/clocksource/armv7m_systick.c N: stm32 N: stm +ARM/SUNPLUS SP7021 SOC SUPPORT +M: Qin Jian <[email protected]> +L: [email protected] (moderated for mon-subscribers) +S: Maintained +W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview +F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml + ARM/Synaptics SoC support M: Jisheng Zhang <[email protected]> M: Sebastian Hesselbarth <[email protected]>
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2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Qin Jian
maintainerPATCH v2 3/8 dt-bindings: reset: Add bindings for SP7021 reset driver
In reply to Qin JianAdd documentation to describe Sunplus SP7021 reset driver bindings.
--- .../bindings/reset/sunplus,reset.yaml | 40 ++++++++ MAINTAINERS | 2 + include/dt-bindings/reset/sp-sp7021.h | 99 +++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml create mode 100644 include/dt-bindings/reset/sp-sp7021.h
Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file +40 -0
@@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Sunplus SoC Reset Controller + +maintainers: + - Qin Jian <[email protected]> + +properties: + compatible: + enum: + - sunplus,sp7021-reset # Reset Controller on SP7021 and compatible SoCs + - sunplus,q645-reset # Reset Controller on Q645 and compatible SoCs + + "#reset-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#reset-cells" + - reg + +additionalProperties: false + +examples: + - | + rstc: reset@9c000054 { + compatible = "sunplus,sp7021-reset"; + #reset-cells = <1>; + reg = <0x9c000054 0x28>; + }; + +...
MAINTAINERS +2 -0
@@ -2661,6 +2661,8 @@ L: [email protected] (moderated for mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support M: Jisheng Zhang <[email protected]>
include/dt-bindings/reset/sp-sp7021.h new file +99 -0
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2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Qin Jian
maintainerPATCH v2 4/8 reset: Add Sunplus SP7021 reset driver
In reply to Qin JianAdd reset driver for Sunplus SP7021 SoC.
--- MAINTAINERS | 1 + drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-sunplus.c | 159 ++++++++++++++++++++++++++++++++++ 4 files changed, 170 insertions(+) create mode 100644 drivers/reset/reset-sunplus.c
MAINTAINERS +1 -0
@@ -2662,6 +2662,7 @@ S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: drivers/reset/reset-sunplus.c F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support
drivers/reset/Kconfig +9 -0
@@ -249,6 +249,15 @@ config RESET_TI_SYSCON you wish to use the reset framework for such memory-mapped devices, say Y here. Otherwise, say N. +config RESET_SUNPLUS + bool "Sunplus SoCs Reset Driver" + default ARCH_PENTAGRAM + help + This enables the reset driver support for Sunplus SP7021 SoC family. + Say Y if you want to control reset signals by the reset controller. + Otherwise, say N. + This driver is selected automatically by platform config. + config RESET_UNIPHIER tristate "Reset controller driver for UniPhier SoCs" depends on ARCH_UNIPHIER || COMPILE_TEST
drivers/reset/Makefile +1 -0
@@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
drivers/reset/reset-sunplus.c new file +159 -0
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kernel test robot
build botRe: [PATCH v2 4/8] reset: Add Sunplus SP7021 reset driver
I love your patch! Yet something to improve:
Hi Qin,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on pza/reset/next clk/clk-next tip/irq/core linus/master v5.15-rc7 next-20211029] [If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/Add-Sunplus-SP7021-SoC-Support/20211029-171054 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: arc-allyesconfig (attached as .config) compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/45fff7c04fb4d0ccfbd1ed11f73277d1f8742499
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/Add-Sunplus-SP7021-SoC-Support/20211029-171054 git checkout 45fff7c04fb4d0ccfbd1ed11f73277d1f8742499
# save the attached .config to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arc SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
drivers/reset/reset-sunplus.c: In function 'sp_restart':
>> drivers/reset/reset-sunplus.c:98:42: error: 'RST_SYSTEM' undeclared (first use in this function)
98 | sp_reset_assert(&sp_reset.rcdev, RST_SYSTEM);
| ^~~~~~~~~~
drivers/reset/reset-sunplus.c:98:42: note: each undeclared identifier is reported only once for each function it appears in
drivers/reset/reset-sunplus.c: In function 'sp_reset_probe':
>> drivers/reset/reset-sunplus.c:135:33: error: 'RST_MAX' undeclared (first use in this function); did you mean 'S8_MAX'?
135 | data->rcdev.nr_resets = RST_MAX;
| ^~~~~~~
| S8_MAXvim +/RST_SYSTEM +98 drivers/reset/reset-sunplus.c
94
95 static int sp_restart(struct notifier_block *this, unsigned long mode,
96 void *cmd)
97 {
> 98 sp_reset_assert(&sp_reset.rcdev, RST_SYSTEM);
99 sp_reset_deassert(&sp_reset.rcdev, RST_SYSTEM);
100
101 return NOTIFY_DONE;
102 }
103
104 static struct notifier_block sp_restart_nb = {
105 .notifier_call = sp_restart,
106 .priority = 192,
107 };
108
109 static const struct reset_control_ops sp_reset_ops = {
110 .assert = sp_reset_assert,
111 .deassert = sp_reset_deassert,
112 .status = sp_reset_status,
113 };
114
115 static const struct of_device_id sp_reset_dt_ids[] = {
116 { .compatible = "sunplus,sp7021-reset", },
117 { .compatible = "sunplus,q645-reset", },
118 { /* sentinel */ },
119 };
120
121 static int sp_reset_probe(struct platform_device *pdev)
122 {
123 struct device *dev = &pdev->dev;
124 struct sp_reset_data *data = &sp_reset;
125 void __iomem *membase;
126 struct resource *res;
127
128 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
129 membase = devm_ioremap(dev, res->start, resource_size(res));
130 if (IS_ERR(membase))
131 return PTR_ERR(membase);
132
133 data->membase = membase;
134 data->rcdev.owner = THIS_MODULE;
> 135 data->rcdev.nr_resets = RST_MAX; 136 data->rcdev.ops = &sp_reset_ops;
137 data->rcdev.of_node = dev->of_node;
138 register_restart_handler(&sp_restart_nb);
139
140 return devm_reset_controller_register(dev, &data->rcdev);
141 }
142
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
Qin Jian
maintainerPATCH v2 5/8 dt-bindings: clock: Add bindings for SP7021 clock driver
In reply to Qin JianAdd documentation to describe Sunplus SP7021 clock driver bindings.
--- .../bindings/clock/sunplus,sp7021-clkc.yaml | 38 ++++++ MAINTAINERS | 2 + include/dt-bindings/clock/sp-sp7021.h | 112 ++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 include/dt-bindings/clock/sp-sp7021.h
Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file +38 -0
@@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Clock Controller Binding + +maintainers: + - Qin Jian <[email protected]> + +properties: + compatible: + const: sunplus,sp7021-clkc + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + clkc: clkc@9c000000 { + compatible = "sunplus,sp7021-clkc"; + #clock-cells = <1>; + reg = <0x9c000000 0x280>; + }; + +...
MAINTAINERS +2 -0
@@ -2661,8 +2661,10 @@ L: [email protected] (moderated for mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/reset/reset-sunplus.c +F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support
include/dt-bindings/clock/sp-sp7021.h new file +112 -0
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2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Qin Jian
maintainerPATCH v2 6/8 clk: Add Sunplus SP7021 clock driver
In reply to Qin JianAdd clock driver for Sunplus SP7021 SoC.
--- MAINTAINERS | 1 + drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk-sp7021.c | 770 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 780 insertions(+) create mode 100644 drivers/clk/clk-sp7021.c
MAINTAINERS +1 -0
@@ -2663,6 +2663,7 @@ W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: drivers/clk/clk-sp7021.c F: drivers/reset/reset-sunplus.c F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h
drivers/clk/Kconfig +8 -0
@@ -334,6 +334,14 @@ config COMMON_CLK_VC5 This driver supports the IDT VersaClock 5 and VersaClock 6 programmable clock generators. +config COMMON_CLK_SP7021 + def_bool OF && COMMON_CLK && SOC_SP7021 + help + This driver supports the Sunplus SP7021 SoC clocks. + It implemented SP7021 PLLs/gate. + Not all features of the PLL are currently supported + by the driver. + config COMMON_CLK_STM32MP157 def_bool COMMON_CLK && MACH_STM32MP157 help
drivers/clk/Makefile +1 -0
@@ -60,6 +60,7 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o obj-$(CONFIG_COMMON_CLK_SI544) += clk-si544.o obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o +obj-$(CONFIG_COMMON_CLK_SP7021) += clk-sp7021.o obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o
drivers/clk/clk-sp7021.c new file +770 -0
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2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Qin Jian
maintainerPATCH v2 7/8 dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller
In reply to Qin JianAdd documentation to describe Sunplus SP7021 interrupt controller bindings.
--- .../sunplus,sp7021-intc.yaml | 59 +++++++++++++++++++ MAINTAINERS | 2 + .../interrupt-controller/sp7021-intc.h | 24 ++++++++ 3 files changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml create mode 100644 include/dt-bindings/interrupt-controller/sp7021-intc.h
Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml new file +59 -0
@@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Interrupt Controller Device Tree Bindings + +maintainers: + - Qin Jian <[email protected]> + +properties: + compatible: + items: + - const: sunplus,sp7021-intc + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + description: + The first cell is the IRQ number, the second cell the trigger + type as defined in interrupt.txt in this directory. + The MSB of second cell also indicate route to which EXT_INT. + + reg: + maxItems: 2 + + interrupts: + maxItems: 2 + description: + EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt + controller. + +required: + - compatible + - interrupt-controller + - "#interrupt-cells" + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + intc: interrupt-controller@9c000780 { + compatible = "sunplus,sp7021-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9c000780 0x80>, <0x9c000a80 0x80>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */ + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */ + }; + +...
MAINTAINERS +2 -0
@@ -2662,10 +2662,12 @@ S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml +F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/clk/clk-sp7021.c F: drivers/reset/reset-sunplus.c F: include/dt-bindings/clock/sp-sp7021.h +F: include/dt-bindings/interrupt-controller/sp7021-intc.h F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support
include/dt-bindings/interrupt-controller/sp7021-intc.h new file +24 -0
@@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* +* Copyright (C) Sunplus Technology Co., Ltd. +* All rights reserved. +* +* +* This header provides constants for the SP7021 INTC +*/ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_SP7021_INTC_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_SP7021_INTC_H + +#include <dt-bindings/interrupt-controller/irq.h> + +/* +* Interrupt specifier cell 1. +* The flags in irq.h are valid, plus those below. +*/ +#define SP_INTC_EXT_INT0 0x00000 +#define SP_INTC_EXT_INT1 0x01000 +#define SP_INTC_EXT_INT_MASK 0xff000 +#define SP_INTC_EXT_INT_SHFIT 12 + +#endif
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Qin Jian
maintainerPATCH v2 8/8 irqchip: Add support for Sunplus SP7021 interrupt controller
In reply to Qin JianAdd interrupt driver for Sunplus SP7021 SoC.
This is the interrupt controller in P chip which collects all interrupt sources in P-chip and routes them to C-chip. C-chip adopts ARM CA7 interrupt controller (compitable = "arm,cortex-a7-gic"). It is a parent interrupt controller of P-chip interrupt controller.
--- MAINTAINERS | 1 + drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sp7021-intc.c | 324 ++++++++++++++++++++++++++++++ 4 files changed, 335 insertions(+) create mode 100644 drivers/irqchip/irq-sp7021-intc.c
MAINTAINERS +1 -0
@@ -2665,6 +2665,7 @@ F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/clk/clk-sp7021.c +F: drivers/irqchip/irq-sp7021-intc.c F: drivers/reset/reset-sunplus.c F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/interrupt-controller/sp7021-intc.h
drivers/irqchip/Kconfig +9 -0
@@ -602,4 +602,13 @@ config APPLE_AIC Support for the Apple Interrupt Controller found on Apple Silicon SoCs, such as the M1. +config SUNPLUS_SP7021_INTC + bool "Sunplus SP7021 interrupt controller" + default SOC_SP7021 + help + Support for the Sunplus SP7021 Interrupt Controller IP core. + This is used as a primary controller with SP7021 ChipP and can also + be used as a secondary chained controller on SP7021 ChipC. + This is selected automatically by platform config. + endmenu
drivers/irqchip/Makefile +1 -0
@@ -116,3 +116,4 @@ obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o obj-$(CONFIG_WPCM450_AIC) += irq-wpcm450-aic.o obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o +obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
drivers/irqchip/irq-sp7021-intc.c new file +324 -0
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2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH v2 8/8] irqchip: Add support for Sunplus SP7021 interrupt controller
Quoted 6 lines · Qin Jian
Add interrupt driver for Sunplus SP7021 SoC.
This is the interrupt controller in P chip which collects all interrupt sources in P-chip and routes them to C-chip. C-chip adopts ARM CA7 interrupt controller (compitable = "arm,cortex-a7-gic"). It is a parent
This information isn't relevant.
Quoted 29 lines
interrupt controller of P-chip interrupt controller.
Signed-off-by Qin Jian <[email protected]>--- MAINTAINERS | 1 + drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sp7021-intc.c | 324 ++++++++++++++++++++++++++++++ 4 files changed, 335 insertions(+) create mode 100644 drivers/irqchip/irq-sp7021-intc.cMAINTAINERS +1
-0@@ -2665,6 +2665,7 @@ F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/clk/clk-sp7021.c +F: drivers/irqchip/irq-sp7021-intc.c F: drivers/reset/reset-sunplus.c F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/interrupt-controller/sp7021-intc.hdrivers/irqchip/Kconfig +0
-0@@ -602,4 +602,13 @@ config APPLE_AIC Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
drivers/irqchip/Kconfig config APPLE_AIC · line 612
Quoted 10 lines
drivers/irqchip/Kconfig +8
-0such as the M1. +config SUNPLUS_SP7021_INTC + bool "Sunplus SP7021 interrupt controller" + default SOC_SP7021 + help + Support for the Sunplus SP7021 Interrupt Controller IP core. + This is used as a primary controller with SP7021 ChipP and can also + be used as a secondary chained controller on SP7021 ChipC. + This is selected automatically by platform config.
If it is selected, drop the default.
Quoted 28 lines
drivers/irqchip/Kconfig +1
-0+ endmenudrivers/irqchip/Makefile +1
-0@@ -116,3 +116,4 @@ obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o obj-$(CONFIG_WPCM450_AIC) += irq-wpcm450-aic.o obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o +obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.odrivers/irqchip/irq-sp7021-intc.c new file +11
-0@@ -0,0 +1,324 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* +* Copyright (C) Sunplus Technology Co., Ltd. +* All rights reserved. +*/ +#include <linux/irq.h> +#include <linux/irqdomain.h> +#include <linux/io.h> +#include <linux/irqchip.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/of_address.h>
drivers/irqchip/irq-sp7021-intc.c line 21
Quoted 10 lines
drivers/irqchip/irq-sp7021-intc.c new file +10
-0+#include <linux/of_irq.h> + +#include <asm/exception.h> +#include <dt-bindings/interrupt-controller/sp7021-intc.h> + +#define SP_INTC_HWIRQ_MIN 0 +#define SP_INTC_HWIRQ_MAX 223 + +/* Interrupt G0/G1 offset */ +#define INTR_REG_SIZE (7 * 4)
Why isn't that derived from the number of interrupts?
Quoted 7 lines
drivers/irqchip/irq-sp7021-intc.c new file +7
-0+ +#define G0_INTR_TYPE (0) +#define G0_INTR_POLARITY (G0_INTR_TYPE + INTR_REG_SIZE) +#define G0_INTR_PRIORITY (G0_INTR_POLARITY + INTR_REG_SIZE) +#define G0_INTR_MASK (G0_INTR_PRIORITY + INTR_REG_SIZE) + +#define G1_INTR_CLR (0)
drivers/irqchip/irq-sp7021-intc.c line 38
Quoted 10 lines
drivers/irqchip/irq-sp7021-intc.c new file +10
-0+#define G1_MASKED_EXT1 (G1_INTR_CLR + INTR_REG_SIZE) +#define G1_MASKED_EXT0 (G1_MASKED_EXT1 + INTR_REG_SIZE) +#define G1_INTR_GROUP (31 * 4) +#define G1_INTR_MASK (0x7F) +#define G1_EXT1_SHIFT (0) +#define G1_EXT0_SHIFT (8) + +static struct sp_intctl { + void __iomem *g0; + void __iomem *g1;
What is G0? what is G1?
Quoted 5 lines
drivers/irqchip/irq-sp7021-intc.c new file +5
-0+struct irq_domain *domain; +struct device_node *node; +raw_spinlock_t lock; +int virq[2 ]; +} sp_intc;
drivers/irqchip/irq-sp7021-intc.c line 53
Quoted 10 lines
drivers/irqchip/irq-sp7021-intc.c new file +10
-0+ +/* GPIO INT EDGE BUG WORKAROUND */ +#define GPIO_INT0_HWIRQ 120 +#define GPIO_INT7_HWIRQ 127 +#define GPIO_INT_EDGE_ACTIVE BIT(31) +#define IS_GPIO_INT (n) (((n) >= GPIO_INT0_HWIRQ) && ((n) <= GPIO_INT7_HWIRQ)) +/* array to hold which interrupt needs to workaround the bug +* INT_TYPE_NONE: no need +* INT_TYPE_EDGE_FALLING/INT_TYPE_EDGE_RISING: need to workaround +* GPIO_INT_EDGE_ACTIVING: workaround is on going
Please describe the nature of the workaround. s/ACTIVING/ACTIVE/.
drivers/irqchip/irq-sp7021-intc.c line 55
Quoted 2 lines
drivers/irqchip/irq-sp7021-intc.c new file +2
-0+*/ +static u32 edge_trigger[SP_INTC_HWIRQ_MAX ];
4 states per interrupt, and yet you use a u32 for each of them... Also, why isn't this part of your sp_intc data structure? You also have enough space for 200+ interrupts (ignoring the obvious off-by-one bug), and yet you are only concerned with 8 of them. Do you spot a trend here?
drivers/irqchip/irq-sp7021-intc.c line 59
Quoted 4 lines
drivers/irqchip/irq-sp7021-intc.c new file +4
-0+ +static struct irq_chip sp_intc_chip; + +static void sp_intc_assign_bit (u32 hwirq,void __iomem *base,u32 value)
If value describes a single bit, why is it a u32?
Quoted 13 lines
drivers/irqchip/irq-sp7021-intc.c new file +13
-0+{ +u32 offset, mask; +unsigned long flags; +void __iomem *reg; + + offset = (hwirq /32 ) *4 ; + reg = base + offset; + +raw_spin_lock_irqsave (&sp_intc.lock, flags); + mask =readl_relaxed (reg); +if (value) + mask |=BIT (hwirq %32 ); +else
drivers/irqchip/irq-sp7021-intc.c line 82
Quoted 10 lines
drivers/irqchip/irq-sp7021-intc.c new file +10
-0+ mask &= ~BIT (hwirq %32 ); +writel_relaxed (mask, reg); +raw_spin_unlock_irqrestore (&sp_intc.lock, flags); +} + +static void sp_intc_ack_irq (struct irq_data *d) +{ +u32 hwirq = d->hwirq; + +if (edge_trigger[hwirq] !=IRQ_TYPE_NONE ) {
Why don't you just check the irq number instead?
drivers/irqchip/irq-sp7021-intc.c line 85
Quoted 3 lines
drivers/irqchip/irq-sp7021-intc.c new file +3
-0+sp_intc_assign_bit (hwirq, sp_intc.g0 +G0_INTR_POLARITY , + (edge_trigger[hwirq] ==IRQ_TYPE_EDGE_RISING )); + edge_trigger[hwirq] |=GPIO_INT_EDGE_ACTIVE ;
The whole thing is terrible. For each of the 8 interrupts, you only need to know whether:
- it is rising or falling
- it is active or not
That's a grand total of 16 bits instead of almost a 1kB worth of nothing. Use atomic bitops, and this is done.
Quoted 14 lines
drivers/irqchip/irq-sp7021-intc.c new file +14
-0+ } + +sp_intc_assign_bit (hwirq, sp_intc.g1 +G1_INTR_CLR ,1 ); +} + +static void sp_intc_mask_irq (struct irq_data *d) +{ +sp_intc_assign_bit (d->hwirq, sp_intc.g0 +G0_INTR_MASK ,0 ); +} + +static void sp_intc_unmask_irq (struct irq_data *d) +{ +sp_intc_assign_bit (d->hwirq, sp_intc.g0 +G0_INTR_MASK ,1 ); +}
drivers/irqchip/irq-sp7021-intc.c line 109
Quoted 10 lines
drivers/irqchip/irq-sp7021-intc.c new file +10
-0+ +static void sp_intc_set_priority (u32 hwirq,u32 priority) +{ +sp_intc_assign_bit (hwirq, sp_intc.g0 +G0_INTR_PRIORITY , priority); +} + +static int sp_intc_set_type (struct irq_data *d,unsigned int type) +{ +u32 intr_type;/* 0: level 1: edge */ +u32 intr_polarity;/* 0: high/rising 1: low/falling */
So how about giving the variables sensible names and types:
bool is_level, is_high;
Quoted 9 lines
drivers/irqchip/irq-sp7021-intc.c new file +9
-0+u32 hwirq = d->hwirq; + +/* update the chip/handler */ +if (type &IRQ_TYPE_LEVEL_MASK ) +irq_set_chip_handler_name_locked (d, &sp_intc_chip, + handle_level_irq,NULL ); +else +irq_set_chip_handler_name_locked (d, &sp_intc_chip, + handle_edge_irq,NULL );
drivers/irqchip/irq-sp7021-intc.c line 128
Quoted 10 lines
drivers/irqchip/irq-sp7021-intc.c new file +10
-0+ + edge_trigger[hwirq] =IRQ_TYPE_NONE ; + +if (type &IRQ_TYPE_LEVEL_MASK ) + intr_type =0 ; +else if (IS_GPIO_INT (hwirq)) { + intr_type =0 ; + edge_trigger[hwirq] = type; + }else + intr_type =1 ;
Coding style.
Quoted 20 lines
drivers/irqchip/irq-sp7021-intc.c new file +20
-0+ + intr_polarity = (type ==IRQ_TYPE_LEVEL_LOW || type ==IRQ_TYPE_EDGE_FALLING ); + +sp_intc_assign_bit (hwirq, sp_intc.g0 +G0_INTR_TYPE , intr_type); +sp_intc_assign_bit (hwirq, sp_intc.g0 +G0_INTR_POLARITY , intr_polarity); + +return IRQ_SET_MASK_OK ; +} + +static int sp_intc_get_ext_irq (int ext_num) +{ +u32 hwirq, mask; +u32 i; + + i =readl_relaxed (sp_intc.g1 +G1_INTR_GROUP ); +if (ext_num) + mask = (i >>G1_EXT1_SHIFT ) &G1_INTR_MASK ; +else + mask = (i >>G1_EXT0_SHIFT ) &G1_INTR_MASK ; +if (mask) {
drivers/irqchip/irq-sp7021-intc.c line 158
Quoted 10 lines
drivers/irqchip/irq-sp7021-intc.c new file +10
-0+ i =fls (mask) -1 ; +if (ext_num) + mask =readl_relaxed (sp_intc.g1 +G1_MASKED_EXT1 + i *4 ); +else + mask =readl_relaxed (sp_intc.g1 +G1_MASKED_EXT0 + i *4 ); +if (mask) { + hwirq = (i <<5 ) +fls (mask) -1 ; +return hwirq; + } + }
What a terrible control flow. Also, variable names are cheap, and you don't need to reuse them when they mean something different.
if (ext_num) {
shift = G1_EXT1_SHIFT;
offset = G1_MASKED_EXT1;
} else {
[[ same thing with G0 ]
}
status = readl_relaxed();
pending_summary = (status >> shift) & G1_INTR_MASK;
if (!pending_summary)
return -1;
index = fls(pending_summary) - 1;
pending = readl_relaxed(g1 + offset + index * 4);
if (!pending)
return -1;
return (index << 5) | (fls(pending) - 1);Look: no nesting, obvious names, anyone can understand it.
Quoted 8 lines
drivers/irqchip/irq-sp7021-intc.c new file +8
-0+return -1 ;/* No interrupt */ +} + +static void sp_intc_handle_ext_cascaded (struct irq_desc *desc) +{ +struct irq_chip *host_chip =irq_desc_get_chip (desc); +int ext_num = (int )irq_desc_get_handler_data (desc); +int hwirq;
drivers/irqchip/irq-sp7021-intc.c line 176
Quoted 10 lines
drivers/irqchip/irq-sp7021-intc.c new file +10
-0+ +chained_irq_enter (host_chip, desc); + +while ((hwirq =sp_intc_get_ext_irq (ext_num)) >=0 ) { +if (edge_trigger[hwirq] &GPIO_INT_EDGE_ACTIVE ) { + edge_trigger[hwirq] &= ~GPIO_INT_EDGE_ACTIVE ; +sp_intc_assign_bit (hwirq, sp_intc.g0 +G0_INTR_POLARITY , + (edge_trigger[hwirq] !=IRQ_TYPE_EDGE_RISING )); + }else +generic_handle_domain_irq (sp_intc.domain, hwirq);
Coding style.
Quoted 37 lines
drivers/irqchip/irq-sp7021-intc.c new file +37
-0+ } + +chained_irq_exit (host_chip, desc); +} + +static void __exception_irq_entry sp_intc_handle_irq(struct pt_regs *regs) +{ +int hwirq; + +while ((hwirq =sp_intc_get_ext_irq (0 )) >=0 ) +generic_handle_domain_irq (sp_intc.domain, hwirq); +} + +static void __init sp_intc_chip_init (void __iomem *base0,void __iomem *base1) +{ +int i; + + sp_intc.g0 = base0; + sp_intc.g1 = base1; + +for (i =0 ; i <7 ; i++) { +/* all mask */ +writel_relaxed (0 , sp_intc.g0 +G0_INTR_MASK + i *4 ); +/* all edge */ +writel_relaxed (~0 , sp_intc.g0 +G0_INTR_TYPE + i *4 ); +/* all high-active */ +writel_relaxed (0 , sp_intc.g0 +G0_INTR_POLARITY + i *4 ); +/* all irq */ +writel_relaxed (~0 , sp_intc.g0 +G0_INTR_PRIORITY + i *4 ); +/* all clear */ +writel_relaxed (~0 , sp_intc.g1 +G1_INTR_CLR + i *4 ); + } +} + +int sp_intc_xlate_of (struct irq_domain *d,struct device_node *node, +const u32 *intspec,unsigned int intsize, +irq_hw_number_t *out_hwirq,unsigned int *out_type)
drivers/irqchip/irq-sp7021-intc.c line 223
Quoted 10 lines
drivers/irqchip/irq-sp7021-intc.c new file +10
-0+{ +int ret; + + ret =irq_domain_xlate_twocell (d, node, + intspec, intsize, out_hwirq, out_type); +if (!ret) { +/* intspec[1]: IRQ_TYPE | SP_INTC_EXT_INT +* SP_INTC_EXT_INT: 0-1, +* to indicate route to which parent irq: EXT_INT0/EXT_INT1 +*/
Why is that in the DT? If that's a SW decision, it doesn't belong there.
drivers/irqchip/irq-sp7021-intc.c line 229
Quoted 6 lines
drivers/irqchip/irq-sp7021-intc.c new file +6
-0+u32 ext_int = (intspec[1 ] &SP_INTC_EXT_INT_MASK ) >>SP_INTC_EXT_INT_SHFIT ; + +/* priority = 0, route to EXT_INT1 +* otherwise, route to EXT_INT0 +*/ +sp_intc_set_priority (*out_hwirq,1 - ext_int);
I already said in the initial review that changing the HW didn't belong in the translate callback, but should be done at map() time.
Quoted 19 lines
drivers/irqchip/irq-sp7021-intc.c new file +19
-0+ } + +return ret; +} + +static struct irq_chip sp_intc_chip = { + .name ="sp_intc" , + .irq_ack = sp_intc_ack_irq, + .irq_mask = sp_intc_mask_irq, + .irq_unmask = sp_intc_unmask_irq, + .irq_set_type = sp_intc_set_type, +}; + +static int sp_intc_irq_domain_map (struct irq_domain *domain, +unsigned int irq,irq_hw_number_t hwirq) +{ +irq_set_chip_and_handler (irq, &sp_intc_chip, handle_level_irq); +irq_set_chip_data (irq, &sp_intc_chip); +irq_set_noprobe (irq);
drivers/irqchip/irq-sp7021-intc.c line 258
Quoted 10 lines
drivers/irqchip/irq-sp7021-intc.c new file +10
-0+ +return 0 ; +} + +static const struct irq_domain_ops sp_intc_dm_ops = { + .xlate = sp_intc_xlate_of, + .map = sp_intc_irq_domain_map, +}; + +#ifdef CONFIG_OF
Why the #ifdef? This thing doesn't work without OF anyway.
drivers/irqchip/irq-sp7021-intc.c line 263
Quoted 5 lines
drivers/irqchip/irq-sp7021-intc.c new file +5
-0+static int sp_intc_irq_map (struct device_node *node,int i) +{ + sp_intc.virq[i] =irq_of_parse_and_map (node, i); +if (!sp_intc.virq[i]) { +pr_err ("%s: missed EXT_INT%d in DT\n" , __func__, i);
-ENOENT is enough, no need to shout on the console.
drivers/irqchip/irq-sp7021-intc.c line 267
Quoted 4 lines
drivers/irqchip/irq-sp7021-intc.c new file +4
-0+return -ENOENT ; + } + +pr_info ("%s: EXT_INT%d = %d\n" , __func__, i, sp_intc.virq[i]);
Nobody cares about this. Get rid of it.
drivers/irqchip/irq-sp7021-intc.c line 275
Quoted 8 lines
drivers/irqchip/irq-sp7021-intc.c new file +8
-0+irq_set_chained_handler_and_data (sp_intc.virq[i], + sp_intc_handle_ext_cascaded, (void *)i); + +return 0 ; +} + +int __init sp_intc_init_dt ( +struct device_node *node,struct device_node *parent)
Single line.
Quoted 14 lines
drivers/irqchip/irq-sp7021-intc.c new file +14
-0+{ +void __iomem *base0, *base1; + + base0 =of_iomap (node,0 ); +if (!base0) { +pr_err ("unable to map sp-intc base 0\n" ); +return -EINVAL ; + } + + base1 =of_iomap (node,1 ); +if (!base1) { +pr_err ("unable to map sp-intc base 1\n" ); +return -EINVAL ; + }
drivers/irqchip/irq-sp7021-intc.c line 299
Quoted 10 lines
drivers/irqchip/irq-sp7021-intc.c new file +10
-0+ + sp_intc.node = node; + +sp_intc_chip_init (base0, base1); + + sp_intc.domain =irq_domain_add_linear (node, +SP_INTC_HWIRQ_MAX -SP_INTC_HWIRQ_MIN , + &sp_intc_dm_ops, &sp_intc); +if (!sp_intc.domain) { +pr_err ("%s: unable to create linear domain\n" , __func__);
Drop the error message.
drivers/irqchip/irq-sp7021-intc.c line 308
Quoted 9 lines
drivers/irqchip/irq-sp7021-intc.c new file +9
-0+return -EINVAL ; + } + +raw_spin_lock_init (&sp_intc.lock); + +if (parent) { +/* secondary chained controller */ +if (sp_intc_irq_map (node,0 ))// EXT_INT0 +return -ENOENT ;
Just return whatever the helper returned. You don't need to reinterpret it.
drivers/irqchip/irq-sp7021-intc.c line 315
Quoted 7 lines
drivers/irqchip/irq-sp7021-intc.c new file +7
-0+ +if (sp_intc_irq_map (node,1 ))// EXT_INT1 +return -ENOENT ; + }else { +/* primary controller */ +set_handle_irq (sp_intc_handle_irq); + }
So what happens if you have *two* of these blocks? One as the root controller, and another implementing the chained stuff?
drivers/irqchip/irq-sp7021-intc.c line 324
Quoted 9 lines
drivers/irqchip/irq-sp7021-intc.c new file +9
-0+ + return 0; +} +IRQCHIP_DECLARE (sp_intc,"sunplus,sp7021-intc" , sp_intc_init_dt); +#endif + +MODULE_AUTHOR ("Qin Jian <[email protected]>" ); +MODULE_DESCRIPTION ("Sunplus SP7021 Interrupt Controller Driver" ); +MODULE_LICENSE ("GPL v2" );
You are using IRQCHIP_DECLARE(), so this isn't a module. Drop this.
Thankfully, it is too late for 5.16, so you have a full cycle to give this code another major cleanup.
M.
Signature · 1 line
Without deviation from the norm, progress is not possible.
Qin Jian
maintainerv3 cover Add Sunplus SP7021 SoC Support
This patch series add Sunplus SP7021 SoC support.
Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates many peripherals (ex: UART, I2C, SPI, SDIO, eMMC, USB, SD card and etc.) into a single chip. It is designed for industrial control.
SP7021 consists of two chips (dies) in a package. One is called C-chip (computing chip). It is a 4-core ARM Cortex A7 CPU. It adopts high-level process (22 nm) for high performance computing. The other is called P- chip (peripheral chip). It has many peripherals and an ARM A926 added especially for real-time control. P-chip is made for customers. It adopts low-level process (ex: 0.11 um) to reduce cost.
Refer to (for documentations):
https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
Refer to (applications):
https://tibbo.com/store/plus1.html
Refer to (applications):
http://www.sinovoip.com.cn/ecp_view.asp?id=586
Changes in v3:
- sp7021-intc: remove primary controller mode due to P-chip running Linux not supported any more.
- sp7021-intc.h: removed, not set ext through the DT but sp_intc_set_ext()
- sunplus,sp7021-intc.yaml: update descriptions for above changes
- irq-sp7021-intc.c: more cleanup based on Marc's review
- all driver's Kconfig removed default, it's selected by platform config
Changes in v2:
- sunplus,sp7021-intc.yaml: add descrption for "#interrupt-cells", interrupts
- sunplus,sp7021-intc.yaml: drop "ext0-mask"/"ext1-mask" from DT
- sunplus,sp7021-intc.yaml: fix example.dt too long error
- irq-sp7021-intc.c: major rewrite
- all files with dual license
Qin Jian (8):
dt-bindings: vendor-prefixes: Add Sunplus
dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards
dt-bindings: reset: Add bindings for SP7021 reset driver
reset: Add Sunplus SP7021 reset driver
dt-bindings: clock: Add bindings for SP7021 clock driver
clk: Add Sunplus SP7021 clock driver
dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt
controller
irqchip: Add Sunplus SP7021 interrupt controller driver
.../bindings/arm/sunplus,sp7021.yaml | 27 + .../bindings/clock/sunplus,sp7021-clkc.yaml | 38 + .../sunplus,sp7021-intc.yaml | 62 ++ .../bindings/reset/sunplus,reset.yaml | 40 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + MAINTAINERS | 15 + drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-sp7021.c | 770 ++++++++++++++++++ drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sp7021-intc.c | 279 +++++++ drivers/reset/Kconfig | 8 + drivers/reset/Makefile | 1 + drivers/reset/reset-sunplus.c | 159 ++++ include/dt-bindings/clock/sp-sp7021.h | 112 +++ include/dt-bindings/reset/sp-sp7021.h | 99 +++ 17 files changed, 1632 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml create mode 100644 drivers/clk/clk-sp7021.c create mode 100644 drivers/irqchip/irq-sp7021-intc.c create mode 100644 drivers/reset/reset-sunplus.c create mode 100644 include/dt-bindings/clock/sp-sp7021.h create mode 100644 include/dt-bindings/reset/sp-sp7021.h
Signature · 7 lines
2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Qin Jian
maintainerPATCH v3 1/8 dt-bindings: vendor-prefixes: Add Sunplus
Add vendor prefix for Sunplus Technology Co., Ltd. (http://www.sunplus.com)
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/vendor-prefixes.yaml +2 -0
@@ -1131,6 +1131,8 @@ patternProperties: description: Summit microelectronics "^sunchip,.*": description: Shenzhen Sunchip Technology Co., Ltd + "^sunplus,.*": + description: Sunplus Technology Co., Ltd. "^SUNW,.*": description: Sun Microsystems, Inc "^supermicro,.*":
Signature · 7 lines
2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH v3 1/8] dt-bindings: vendor-prefixes: Add Sunplus
Quoted 7 lines · Qin Jian
Add vendor prefix for Sunplus Technology Co., Ltd. (http://www.sunplus.com)
Signed-off-by Qin Jian <[email protected]>--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Qin Jian
maintainerPATCH v3 2/8 dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards
In reply to Qin JianThis introduces bindings for boards based Sunplus SP7021 SoC.
--- .../bindings/arm/sunplus,sp7021.yaml | 27 +++++++++++++++++++ MAINTAINERS | 7 +++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml new file +27 -0
@@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Boards Device Tree Bindings + +maintainers: + - qinjian <[email protected]> + +description: | + ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC. + Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sunplus,sp7021-achip + +additionalProperties: true + +...
MAINTAINERS +7 -0
@@ -2655,6 +2655,13 @@ F: drivers/clocksource/armv7m_systick.c N: stm32 N: stm +ARM/SUNPLUS SP7021 SOC SUPPORT +M: Qin Jian <[email protected]> +L: [email protected] (moderated for mon-subscribers) +S: Maintained +W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview +F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml + ARM/Synaptics SoC support M: Jisheng Zhang <[email protected]> M: Sebastian Hesselbarth <[email protected]>
Signature · 7 lines
2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH v3 2/8] dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards
Quoted 9 lines · Qin Jian
This introduces bindings for boards based Sunplus SP7021 SoC.
Signed-off-by Qin Jian <[email protected]>--- .../bindings/arm/sunplus,sp7021.yaml | 27 +++++++++++++++++++ MAINTAINERS | 7 +++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
Qin Jian
maintainerPATCH v3 3/8 dt-bindings: reset: Add bindings for SP7021 reset driver
In reply to Qin JianAdd documentation to describe Sunplus SP7021 reset driver bindings.
--- .../bindings/reset/sunplus,reset.yaml | 40 ++++++++ MAINTAINERS | 2 + include/dt-bindings/reset/sp-sp7021.h | 99 +++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml create mode 100644 include/dt-bindings/reset/sp-sp7021.h
Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file +40 -0
@@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Sunplus SoC Reset Controller + +maintainers: + - Qin Jian <[email protected]> + +properties: + compatible: + enum: + - sunplus,sp7021-reset # Reset Controller on SP7021 and compatible SoCs + - sunplus,q645-reset # Reset Controller on Q645 and compatible SoCs + + "#reset-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#reset-cells" + - reg + +additionalProperties: false + +examples: + - | + rstc: reset@9c000054 { + compatible = "sunplus,sp7021-reset"; + #reset-cells = <1>; + reg = <0x9c000054 0x28>; + }; + +...
MAINTAINERS +2 -0
@@ -2661,6 +2661,8 @@ L: [email protected] (moderated for mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support M: Jisheng Zhang <[email protected]>
include/dt-bindings/reset/sp-sp7021.h new file +99 -0
99 lines not on this page · raw message
Signature · 7 lines
2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Philipp Zabel
maintainerRe: [PATCH v3 3/8] dt-bindings: reset: Add bindings for SP7021 reset driver
Quoted 24 lines · Qin Jian
Add documentation to describe Sunplus SP7021 reset driver bindings.
Signed-off-by Qin Jian <[email protected]>---
.../bindings/reset/sunplus,reset.yaml | 40 ++++++++ MAINTAINERS | 2 + include/dt-bindings/reset/sp-sp7021.h | 99 +++++++++++++++++++ 3 files changed, 141 insertions(+)create mode 100644
Documentation/devicetree/bindings/reset/sunplus,reset.yamlcreate mode 100644include/dt-bindings/reset/sp-sp7021.hDocumentation/devicetree/bindings/reset/sunplus,reset.yaml new file +7
-0@@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" +
Documentation/devicetree/bindings/reset/sunplus,reset.yaml line 17
Quoted 10 lines
Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file +10
-0+title: Sunplus SoC Reset Controller + +maintainers: + - Qin Jian <[email protected]> + +properties: + compatible: + enum: + - sunplus,sp7021-reset # Reset Controller on SP7021 and compatible SoCs + - sunplus,q645-reset # Reset Controller on Q645 and compatible SoCs
The commit message only mentions SP7021. Should Q645 be added later, or is this patch missing the binding header for Q655?
regards
Philipp
qinjian[覃健]
maintainer答复: [PATCH v3 3/8] dt-bindings: reset: Add bindings for SP7021 reset driver
Quoted 9 lines
Documentation/devicetree/bindings/reset/sunplus,reset.yaml line 17
Quoted 5 lines
Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file +5
-0+properties: + compatible: + enum: + - sunplus,sp7021-reset # Reset Controller on SP7021 and compatible SoCs + - sunplus,q645-reset # Reset Controller on Q645 and compatible SoCsThe commit message only mentions SP7021. Should Q645 be added later, or is this patch missing the binding header for Q655?
I'll remove the Q645 entry, which will be added later when submitting Q645 support. Thanks for your review.
Qin Jian
maintainerPATCH v3 4/8 reset: Add Sunplus SP7021 reset driver
In reply to Qin JianAdd reset driver for Sunplus SP7021 SoC.
--- MAINTAINERS | 1 + drivers/reset/Kconfig | 8 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-sunplus.c | 159 ++++++++++++++++++++++++++++++++++ 4 files changed, 169 insertions(+) create mode 100644 drivers/reset/reset-sunplus.c
MAINTAINERS +1 -0
@@ -2662,6 +2662,7 @@ S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: drivers/reset/reset-sunplus.c F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support
drivers/reset/Kconfig +8 -0
@@ -249,6 +249,14 @@ config RESET_TI_SYSCON you wish to use the reset framework for such memory-mapped devices, say Y here. Otherwise, say N. +config RESET_SUNPLUS + bool "Sunplus SoCs Reset Driver" + help + This enables the reset driver support for Sunplus SP7021 SoC family. + Say Y if you want to control reset signals by the reset controller. + Otherwise, say N. + This driver is selected automatically by platform config. + config RESET_UNIPHIER tristate "Reset controller driver for UniPhier SoCs" depends on ARCH_UNIPHIER || COMPILE_TEST
drivers/reset/Makefile +1 -0
@@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
drivers/reset/reset-sunplus.c new file +159 -0
159 lines not on this page · raw message
Signature · 7 lines
2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Philipp Zabel
maintainerRe: [PATCH v3 4/8] reset: Add Sunplus SP7021 reset driver
Quoted 1 line · Qin Jian
Add reset driver for Sunplus SP7021 SoC.
You don't mention Q645 here, it appears this driver supports both SoCs?
[...]
Quoted 10 lines
drivers/reset/Kconfig +0
-0@@ -249,6 +249,14 @@ config RESET_TI_SYSCON you wish to use the reset framework for such memory-mapped devices,say Y here. Otherwise, say N.
+config
RESET_SUNPLUS
Please add these entries in alphabetical order.
drivers/reset/Kconfig config RESET_TI_SYSCON · line 253
Quoted 1 line
drivers/reset/Kconfig +1
-0+ bool "Sunplus SoCs Reset Driver"
Can this be made:
depends SOC_SP7021 || SOC_Q645 || COMPILE_TEST
?
drivers/reset/Kconfig config RESET_TI_SYSCON · line 258
Quoted 5 lines
drivers/reset/Kconfig +5
-0+ help + This enables the reset driver support for Sunplus SP7021 SoC family. + Say Y if you want to control reset signals by the reset controller. + Otherwise, say N. + This driver is selected automatically by platform config.
Which platform config?
[...]
Quoted 12 lines
drivers/reset/reset-sunplus.c new file +6
-0@@ -0,0 +1,159 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* +* SP7021 reset driver +* +* Copyright (C) Sunplus Technology Co., Ltd. +* All rights reserved.
drivers/reset/reset-sunplus.c line 16
Quoted 10 lines
drivers/reset/reset-sunplus.c new file +10
-0+* +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed "as is" WITHOUT ANY WARRANTY of any +* kind, whether express or implied; without even the implied warranty +* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details.
Drop this boilerplate, this is not required with the SPDX identifier above.
Quoted 6 lines
drivers/reset/reset-sunplus.c new file +6
-0+*/ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/io.h>
drivers/reset/reset-sunplus.c line 32
Quoted 10 lines
drivers/reset/reset-sunplus.c new file +10
-0+#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> +#include <linux/reboot.h> + +#if defined(CONFIG_SOC_SP7021 ) +#include <dt-bindings/reset/sp-sp7021.h> +#elif defined(CONFIG_SOC_Q645 ) +#include <dt-bindings/reset/sp-q645.h> +#endif
I'd prefer if you added namespace prefixes to the defines and included both headers unconditionally.
These are just required for RST_MAX, correct?
drivers/reset/reset-sunplus.c line 40
Quoted 8 lines
drivers/reset/reset-sunplus.c new file +8
-0+ +#define BITASSERT (id, val) ((1 << (16 + id)) | (val << id)) + + +struct sp_reset_data { +struct reset_controller_dev rcdev; +void __iomem *membase; +} sp_reset;
Please allocate this with devm_kzalloc in the probe function instead.
Quoted 13 lines
drivers/reset/reset-sunplus.c new file +13
-0+ + +static inline struct sp_reset_data * +to_sp_reset_data (struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct sp_reset_data, rcdev); +} + +static int sp_reset_update (struct reset_controller_dev *rcdev, +unsigned long id,bool assert) +{ +struct sp_reset_data *data =to_sp_reset_data (rcdev); +int reg_width =sizeof (u32)/2 ;
drivers/reset/reset-sunplus.c line 63
Quoted 10 lines
drivers/reset/reset-sunplus.c new file +10
-0+int bank = id / (reg_width *BITS_PER_BYTE ); +int offset = id % (reg_width *BITS_PER_BYTE ); +void __iomem *addr; + + addr = data->membase + (bank *4 ); + +if (assert) +writel (BITASSERT (offset,1 ), addr); +else +writel (BITASSERT (offset,0 ), addr);
Could be
writel(BITASSERT(offset, assert), addr);
Quoted 62 lines
drivers/reset/reset-sunplus.c new file +62
-0+ +return 0 ; +} + +static int sp_reset_assert (struct reset_controller_dev *rcdev, +unsigned long id) +{ +return sp_reset_update (rcdev, id, true); +} + + +static int sp_reset_deassert (struct reset_controller_dev *rcdev, +unsigned long id) +{ +return sp_reset_update (rcdev, id, false); +} + +static int sp_reset_status (struct reset_controller_dev *rcdev, +unsigned long id) +{ +struct sp_reset_data *data =to_sp_reset_data (rcdev); +int reg_width =sizeof (u32)/2 ; +int bank = id / (reg_width *BITS_PER_BYTE ); +int offset = id % (reg_width *BITS_PER_BYTE ); +u32 reg; + + reg =readl (data->membase + (bank *4 )); + +return !!(reg &BIT (offset)); +} + +static int sp_restart (struct notifier_block *this,unsigned long mode, +void *cmd) +{ +sp_reset_assert (&sp_reset.rcdev,RST_SYSTEM ); +sp_reset_deassert (&sp_reset.rcdev,RST_SYSTEM ); + +return NOTIFY_DONE ; +} + +static struct notifier_block sp_restart_nb = { + .notifier_call = sp_restart, + .priority =192 , +}; + +static const struct reset_control_ops sp_reset_ops = { + .assert = sp_reset_assert, + .deassert = sp_reset_deassert, + .status = sp_reset_status, +}; + +static const struct of_device_id sp_reset_dt_ids[] = { + { .compatible ="sunplus,sp7021-reset" , }, + { .compatible ="sunplus,q645-reset" , }, + {/* sentinel */ }, +}; + +static int sp_reset_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +struct sp_reset_data *data = &sp_reset; +void __iomem *membase;
drivers/reset/reset-sunplus.c line 135
Quoted 10 lines
drivers/reset/reset-sunplus.c new file +10
-0+struct resource *res; + + res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); + membase =devm_ioremap (dev, res->start,resource_size (res)); +if (IS_ERR (membase)) +return PTR_ERR (membase); + + data->membase = membase; + data->rcdev.owner =THIS_MODULE ; + data->rcdev.nr_resets =RST_MAX ;
Use of_device_get_match_data() to determine the correct number of resets.
regards
Philipp
qinjian[覃健]
maintainer答复: [PATCH v3 4/8] reset: Add Sunplus SP7021 reset driver
Quoted 8 lines
drivers/reset/Kconfig config RESET_TI_SYSCON · line 258
Quoted 6 lines
drivers/reset/Kconfig +5
-0+ help + This enables the reset driver support for Sunplus SP7021 SoC family. + Say Y if you want to control reset signals by the reset controller. + Otherwise, say N. + This driver is selected automatically by platform config.Which platform config?
arch/arm/mach-sunplus/Kconfig, which will be submit later.
Thanks for your review, I'll submit the new version based on your advice.
Qin Jian
maintainerPATCH v3 5/8 dt-bindings: clock: Add bindings for SP7021 clock driver
In reply to Qin JianAdd documentation to describe Sunplus SP7021 clock driver bindings.
--- .../bindings/clock/sunplus,sp7021-clkc.yaml | 38 ++++++ MAINTAINERS | 2 + include/dt-bindings/clock/sp-sp7021.h | 112 ++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 include/dt-bindings/clock/sp-sp7021.h
Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file +38 -0
@@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Clock Controller Binding + +maintainers: + - Qin Jian <[email protected]> + +properties: + compatible: + const: sunplus,sp7021-clkc + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + clkc: clkc@9c000000 { + compatible = "sunplus,sp7021-clkc"; + #clock-cells = <1>; + reg = <0x9c000000 0x280>; + }; + +...
MAINTAINERS +2 -0
@@ -2661,8 +2661,10 @@ L: [email protected] (moderated for mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/reset/reset-sunplus.c +F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support
include/dt-bindings/clock/sp-sp7021.h new file +112 -0
112 lines not on this page · raw message
Signature · 7 lines
2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH v3 5/8] dt-bindings: clock: Add bindings for SP7021 clock driver
Quoted 11 lines · Qin Jian
Add documentation to describe Sunplus SP7021 clock driver bindings.
Signed-off-by Qin Jian <[email protected]>--- .../bindings/clock/sunplus,sp7021-clkc.yaml | 38 ++++++ MAINTAINERS | 2 + include/dt-bindings/clock/sp-sp7021.h | 112 ++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 include/dt-bindings/clock/sp-sp7021.h
Qin Jian
maintainerPATCH v3 6/8 clk: Add Sunplus SP7021 clock driver
In reply to Qin JianAdd clock driver for Sunplus SP7021 SoC.
--- MAINTAINERS | 1 + drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-sp7021.c | 770 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 781 insertions(+) create mode 100644 drivers/clk/clk-sp7021.c
MAINTAINERS +1 -0
@@ -2663,6 +2663,7 @@ W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: drivers/clk/clk-sp7021.c F: drivers/reset/reset-sunplus.c F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h
drivers/clk/Kconfig +9 -0
@@ -334,6 +334,15 @@ config COMMON_CLK_VC5 This driver supports the IDT VersaClock 5 and VersaClock 6 programmable clock generators. +config COMMON_CLK_SP7021 + bool "Clock driver for Sunplus SP7021 SoC" + help + This driver supports the Sunplus SP7021 SoC clocks. + It implemented SP7021 PLLs/gate. + Not all features of the PLL are currently supported + by the driver. + This driver is selected automatically by platform config. + config COMMON_CLK_STM32MP157 def_bool COMMON_CLK && MACH_STM32MP157 help
drivers/clk/Makefile +1 -0
@@ -60,6 +60,7 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o obj-$(CONFIG_COMMON_CLK_SI544) += clk-si544.o obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o +obj-$(CONFIG_COMMON_CLK_SP7021) += clk-sp7021.o obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o
drivers/clk/clk-sp7021.c new file +770 -0
770 lines not on this page · raw message
Signature · 7 lines
2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
kernel test robot
build botRe: [PATCH v3 6/8] clk: Add Sunplus SP7021 clock driver
I love your patch! Perhaps something to improve:
Hi Qin,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pza/reset/next]
[also build test WARNING on robh/for-next clk/clk-next tip/irq/core linus/master v5.15 next-20211029] [If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211101-140155 base: https://git.pengutronix.de/git/pza/linux reset/next config: openrisc-randconfig-r015-20211101 (attached as .config) compiler: or1k-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/9767714cf5c22192f99adb0d8e344cb5e38a2e33
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211101-140155 git checkout 9767714cf5c22192f99adb0d8e344cb5e38a2e33
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=openrisc
If you fix the issue, kindly add following tag as appropriate
All warnings (new ones prefixed by >>):
>> drivers/clk/clk-sp7021.c:663:13: warning: no previous prototype for 'clk_register_sp_pll' [-Wmissing-prototypes]
663 | struct clk *clk_register_sp_pll(const char *name, const char *parent,
| ^~~~~~~~~~~~~~~~~~~
vim +/clk_register_sp_pll +663 drivers/clk/clk-sp7021.c
662
> 663 struct clk *clk_register_sp_pll(const char *name, const char *parent,
664 void __iomem *reg, int pd_bit, int bp_bit,
665 unsigned long brate, int shift, int width,
666 spinlock_t *lock)
667 {
668 struct sp_pll *pll;
669 struct clk *clk;
670 //unsigned long flags = 0;
671 struct clk_init_data initd = {
672 .name = name,
673 .parent_names = &parent,
674 .ops = (bp_bit >= 0) ? &sp_pll_ops : &sp_pll_sub_ops,
675 .num_parents = 1,
676 .flags = CLK_IGNORE_UNUSED
677 };
678
679 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
680 if (!pll)
681 return ERR_PTR(-ENOMEM);
682
683 if (reg == PLLSYS_CTL)
684 initd.flags |= CLK_IS_CRITICAL;
685
686 pll->hw.init = &initd;
687 pll->reg = reg;
688 pll->pd_bit = pd_bit;
689 pll->bp_bit = bp_bit;
690 pll->brate = brate;
691 pll->div_shift = shift;
692 pll->div_width = width;
693 pll->lock = lock;
694
695 clk = clk_register(NULL, &pll->hw);
696 if (WARN_ON(IS_ERR(clk))) {
697 kfree(pll);
698 } else {
699 pr_info("%-20s%lu\n", name, clk_get_rate(clk));
700 clk_register_clkdev(clk, NULL, name);
701 }
702
703 return clk;
704 }
705
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
Qin Jian
maintainerPATCH v3 7/8 dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller
In reply to Qin JianAdd documentation to describe Sunplus SP7021 interrupt controller bindings.
--- .../sunplus,sp7021-intc.yaml | 62 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml new file +62 -0
@@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Interrupt Controller Device Tree Bindings + +maintainers: + - Qin Jian <[email protected]> + +properties: + compatible: + items: + - const: sunplus,sp7021-intc + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + description: + The first cell is the IRQ number, the second cell is the trigger + type as defined in interrupt.txt in this directory. + + reg: + maxItems: 2 + description: + Specifies base physical address(s) and size of the controller regs. + The 1st region include type/polarity/priority/mask regs. + The 2nd region include clear/masked_ext0/masked_ext1/group regs. + + interrupts: + maxItems: 2 + description: + EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt + controller. + +required: + - compatible + - interrupt-controller + - "#interrupt-cells" + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + intc: interrupt-controller@9c000780 { + compatible = "sunplus,sp7021-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9c000780 0x80>, <0x9c000a80 0x80>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */ + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */ + }; + +...
MAINTAINERS +1 -0
@@ -2662,6 +2662,7 @@ S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml +F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/clk/clk-sp7021.c F: drivers/reset/reset-sunplus.c
Signature · 7 lines
2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH v3 7/8] dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller
Quoted 9 lines · Qin Jian
Add documentation to describe Sunplus SP7021 interrupt controller bindings.
Signed-off-by Qin Jian <[email protected]>--- .../sunplus,sp7021-intc.yaml | 62 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
Qin Jian
maintainerPATCH v3 8/8 irqchip: Add Sunplus SP7021 interrupt controller driver
In reply to Qin JianAdd interrupt controller driver for Sunplus SP7021 SoC.
This is the interrupt controller in P-chip which collects all interrupt sources in P-chip and routes them to parent interrupt controller in C-chip.
--- MAINTAINERS | 1 + drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sp7021-intc.c | 279 ++++++++++++++++++++++++++++++ 4 files changed, 290 insertions(+) create mode 100644 drivers/irqchip/irq-sp7021-intc.c
MAINTAINERS +1 -0
@@ -2665,6 +2665,7 @@ F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/clk/clk-sp7021.c +F: drivers/irqchip/irq-sp7021-intc.c F: drivers/reset/reset-sunplus.c F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h
drivers/irqchip/Kconfig +9 -0
@@ -602,4 +602,13 @@ config APPLE_AIC Support for the Apple Interrupt Controller found on Apple Silicon SoCs, such as the M1. +config SUNPLUS_SP7021_INTC + bool "Sunplus SP7021 interrupt controller" + help + Support for the Sunplus SP7021 Interrupt Controller IP core. + SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a + chained controller, routed all interrupt source in P-Chip to + the primary controller on C-Chip. + This is selected automatically by platform config. + endmenu
drivers/irqchip/Makefile +1 -0
@@ -116,3 +116,4 @@ obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o obj-$(CONFIG_WPCM450_AIC) += irq-wpcm450-aic.o obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o +obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
drivers/irqchip/irq-sp7021-intc.c new file +279 -0
279 lines not on this page · raw message
Signature · 7 lines
2.33.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
kernel test robot
build botRe: [PATCH v3 8/8] irqchip: Add Sunplus SP7021 interrupt controller driver
I love your patch! Perhaps something to improve:
Hi Qin,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pza/reset/next]
[also build test WARNING on robh/for-next clk/clk-next linus/master v5.15] [cannot apply to tip/irq/core next-20211029]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211101-140155 base: https://git.pengutronix.de/git/pza/linux reset/next config: sparc-randconfig-r011-20211101 (attached as .config) compiler: sparc64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/ca53c40693bc90c44e3ec4c95c7758d7342229e2
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211101-140155 git checkout ca53c40693bc90c44e3ec4c95c7758d7342229e2
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=sparc
If you fix the issue, kindly add following tag as appropriate
All warnings (new ones prefixed by >>):
drivers/irqchip/irq-sp7021-intc.c: In function 'sp_intc_handle_ext_cascaded':
>> drivers/irqchip/irq-sp7021-intc.c:154:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
154 | int ext_num = (int)irq_desc_get_handler_data(desc);
| ^
drivers/irqchip/irq-sp7021-intc.c: In function 'sp_intc_irq_map':
>> drivers/irqchip/irq-sp7021-intc.c:212:76: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
212 | irq_set_chained_handler_and_data(irq, sp_intc_handle_ext_cascaded, (void *)i);
| ^
drivers/irqchip/irq-sp7021-intc.c: At top level:
drivers/irqchip/irq-sp7021-intc.c:217:6: warning: no previous prototype for 'sp_intc_set_ext' [-Wmissing-prototypes]
217 | void sp_intc_set_ext(u32 hwirq, int ext_num)
| ^~~~~~~~~~~~~~~ drivers/irqchip/irq-sp7021-intc.c:223:12: warning: no previous prototype for 'sp_intc_init_dt' [-Wmissing-prototypes]
223 | int __init sp_intc_init_dt(struct device_node *node, struct device_node *parent)
| ^~~~~~~~~~~~~~~
vim +154 drivers/irqchip/irq-sp7021-intc.c
150
151 static void sp_intc_handle_ext_cascaded(struct irq_desc *desc)
152 {
153 struct irq_chip *chip = irq_desc_get_chip(desc);
> 154 int ext_num = (int)irq_desc_get_handler_data(desc);
155 int hwirq;
156
157 chained_irq_enter(chip, desc);
158
159 while ((hwirq = sp_intc_get_ext_irq(ext_num)) >= 0) {
160 if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_ACTIVE))) { // WORKAROUND
161 ASSIGN_STATE(hwirq, _IS_ACTIVE, false);
162 sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, TEST_STATE(hwirq, _IS_LOW));
163 } else {
164 generic_handle_domain_irq(sp_intc.domain, hwirq);
165 }
166 }
167
168 chained_irq_exit(chip, desc);
169 }
170
171 #ifdef CONFIG_SMP
172 static int sp_intc_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
173 {
174 return -EINVAL;
175 }
176 #endif
177
178 static struct irq_chip sp_intc_chip = {
179 .name = "sp_intc",
180 .irq_ack = sp_intc_ack_irq,
181 .irq_mask = sp_intc_mask_irq,
182 .irq_unmask = sp_intc_unmask_irq,
183 .irq_set_type = sp_intc_set_type,
184 #ifdef CONFIG_SMP
185 .irq_set_affinity = sp_intc_set_affinity,
186 #endif
187 };
188
189 static int sp_intc_irq_domain_map(struct irq_domain *domain,
190 unsigned int irq, irq_hw_number_t hwirq)
191 {
192 irq_set_chip_and_handler(irq, &sp_intc_chip, handle_level_irq);
193 irq_set_chip_data(irq, &sp_intc_chip);
194 irq_set_noprobe(irq);
195
196 return 0;
197 }
198
199 static const struct irq_domain_ops sp_intc_dm_ops = {
200 .xlate = irq_domain_xlate_twocell,
201 .map = sp_intc_irq_domain_map,
202 };
203
204 static int sp_intc_irq_map(struct device_node *node, int i)
205 {
206 unsigned int irq;
207
208 irq = irq_of_parse_and_map(node, i);
209 if (!irq)
210 return -ENOENT;
211
> 212 irq_set_chained_handler_and_data(irq, sp_intc_handle_ext_cascaded, (void *)i); 213
214 return 0;
215 }
216
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
kernel test robot
build botRe: [PATCH v3 8/8] irqchip: Add Sunplus SP7021 interrupt controller driver
In reply to Qin JianI love your patch! Perhaps something to improve:
Hi Qin,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pza/reset/next]
[also build test WARNING on robh/for-next clk/clk-next linus/master v5.15] [cannot apply to tip/irq/core next-20211029]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211101-140155 base: https://git.pengutronix.de/git/pza/linux reset/next config: arc-randconfig-r016-20211101 (attached as .config) compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/ca53c40693bc90c44e3ec4c95c7758d7342229e2
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211101-140155 git checkout ca53c40693bc90c44e3ec4c95c7758d7342229e2
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
All warnings (new ones prefixed by >>):
>> drivers/irqchip/irq-sp7021-intc.c:217:6: warning: no previous prototype for 'sp_intc_set_ext' [-Wmissing-prototypes]
217 | void sp_intc_set_ext(u32 hwirq, int ext_num)
| ^~~~~~~~~~~~~~~
>> drivers/irqchip/irq-sp7021-intc.c:223:12: warning: no previous prototype for 'sp_intc_init_dt' [-Wmissing-prototypes] 223 | int __init sp_intc_init_dt(struct device_node *node, struct device_node *parent)
| ^~~~~~~~~~~~~~~
vim +/sp_intc_set_ext +217 drivers/irqchip/irq-sp7021-intc.c
216
> 217 void sp_intc_set_ext(u32 hwirq, int ext_num)
218 {
219 sp_intc_assign_bit(hwirq, REG_INTR_PRIORITY, !ext_num);
220 }
221 EXPORT_SYMBOL_GPL(sp_intc_set_ext);
222
> 223 int __init sp_intc_init_dt(struct device_node *node, struct device_node *parent)---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
kernel test robot
build botRe: [PATCH v2 8/8] irqchip: Add support for Sunplus SP7021 interrupt controller
In reply to Qin JianI love your patch! Yet something to improve:
Hi Qin,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on pza/reset/next clk/clk-next linus/master v5.15-rc7] [cannot apply to tip/irq/core next-20211029]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/Add-Sunplus-SP7021-SoC-Support/20211029-171054 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: arc-allyesconfig (attached as .config) compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/91ab876ddb6d1a596c50c43a79d3e06b9695dee7
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/Add-Sunplus-SP7021-SoC-Support/20211029-171054 git checkout 91ab876ddb6d1a596c50c43a79d3e06b9695dee7
# save the attached .config to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arc SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
>> drivers/irqchip/irq-sp7021-intc.c:14:10: fatal error: asm/exception.h: No such file or directory
14 | #include <asm/exception.h>
| ^~~~~~~~~~~~~~~~~compilation terminated.
vim +14 drivers/irqchip/irq-sp7021-intc.c
13
> 14 #include <asm/exception.h>
15 #include <dt-bindings/interrupt-controller/sp7021-intc.h>
16 ---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
kernel test robot
build botRe: [PATCH v2 8/8] irqchip: Add support for Sunplus SP7021 interrupt controller
In reply to Qin JianI love your patch! Yet something to improve:
Hi Qin,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on pza/reset/next clk/clk-next linus/master v5.15-rc7] [cannot apply to tip/irq/core next-20211029]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/Add-Sunplus-SP7021-SoC-Support/20211029-171054 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: arm-allyesconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/91ab876ddb6d1a596c50c43a79d3e06b9695dee7
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/Add-Sunplus-SP7021-SoC-Support/20211029-171054 git checkout 91ab876ddb6d1a596c50c43a79d3e06b9695dee7
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
>> drivers/irqchip/irq-sp7021-intc.c:211:5: error: no previous prototype for 'sp_intc_xlate_of' [-Werror=missing-prototypes]
211 | int sp_intc_xlate_of(struct irq_domain *d, struct device_node *node,
| ^~~~~~~~~~~~~~~~
>> drivers/irqchip/irq-sp7021-intc.c:274:12: error: no previous prototype for 'sp_intc_init_dt' [-Werror=missing-prototypes]
274 | int __init sp_intc_init_dt(
| ^~~~~~~~~~~~~~~cc1: all warnings being treated as errors
vim +/sp_intc_xlate_of +211 drivers/irqchip/irq-sp7021-intc.c
210
> 211 int sp_intc_xlate_of(struct irq_domain *d, struct device_node *node,
212 const u32 *intspec, unsigned int intsize,
213 irq_hw_number_t *out_hwirq, unsigned int *out_type)
214 {
215 int ret;
216
217 ret = irq_domain_xlate_twocell(d, node,
218 intspec, intsize, out_hwirq, out_type);
219 if (!ret) {
220 /* intspec[1]: IRQ_TYPE | SP_INTC_EXT_INT
221 * SP_INTC_EXT_INT: 0-1,
222 * to indicate route to which parent irq: EXT_INT0/EXT_INT1
223 */
224 u32 ext_int = (intspec[1] & SP_INTC_EXT_INT_MASK) >> SP_INTC_EXT_INT_SHFIT;
225
226 /* priority = 0, route to EXT_INT1
227 * otherwise, route to EXT_INT0
228 */
229 sp_intc_set_priority(*out_hwirq, 1 - ext_int);
230 }
231
232 return ret;
233 }
234
235 static struct irq_chip sp_intc_chip = {
236 .name = "sp_intc",
237 .irq_ack = sp_intc_ack_irq,
238 .irq_mask = sp_intc_mask_irq,
239 .irq_unmask = sp_intc_unmask_irq,
240 .irq_set_type = sp_intc_set_type,
241 };
242
243 static int sp_intc_irq_domain_map(struct irq_domain *domain,
244 unsigned int irq, irq_hw_number_t hwirq)
245 {
246 irq_set_chip_and_handler(irq, &sp_intc_chip, handle_level_irq);
247 irq_set_chip_data(irq, &sp_intc_chip);
248 irq_set_noprobe(irq);
249
250 return 0;
251 }
252
253 static const struct irq_domain_ops sp_intc_dm_ops = {
254 .xlate = sp_intc_xlate_of,
255 .map = sp_intc_irq_domain_map,
256 };
257
258 #ifdef CONFIG_OF
259 static int sp_intc_irq_map(struct device_node *node, int i)
260 {
261 sp_intc.virq[i] = irq_of_parse_and_map(node, i);
262 if (!sp_intc.virq[i]) {
263 pr_err("%s: missed EXT_INT%d in DT\n", __func__, i);
264 return -ENOENT;
265 }
266
267 pr_info("%s: EXT_INT%d = %d\n", __func__, i, sp_intc.virq[i]);
268 irq_set_chained_handler_and_data(sp_intc.virq[i],
269 sp_intc_handle_ext_cascaded, (void *)i);
270
271 return 0;
272 }
273
> 274 int __init sp_intc_init_dt( 275 struct device_node *node, struct device_node *parent)
276 {
277 void __iomem *base0, *base1;
278
279 base0 = of_iomap(node, 0);
280 if (!base0) {
281 pr_err("unable to map sp-intc base 0\n");
282 return -EINVAL;
283 }
284
285 base1 = of_iomap(node, 1);
286 if (!base1) {
287 pr_err("unable to map sp-intc base 1\n");
288 return -EINVAL;
289 }
290
291 sp_intc.node = node;
292
293 sp_intc_chip_init(base0, base1);
294
295 sp_intc.domain = irq_domain_add_linear(node,
296 SP_INTC_HWIRQ_MAX - SP_INTC_HWIRQ_MIN,
297 &sp_intc_dm_ops, &sp_intc);
298 if (!sp_intc.domain) {
299 pr_err("%s: unable to create linear domain\n", __func__);
300 return -EINVAL;
301 }
302
303 raw_spin_lock_init(&sp_intc.lock);
304
305 if (parent) {
306 /* secondary chained controller */
307 if (sp_intc_irq_map(node, 0)) // EXT_INT0
308 return -ENOENT;
309
310 if (sp_intc_irq_map(node, 1)) // EXT_INT1
311 return -ENOENT;
312 } else {
313 /* primary controller */
314 set_handle_irq(sp_intc_handle_irq);
315 }
316
317 return 0;
318 }
319 IRQCHIP_DECLARE(sp_intc, "sunplus,sp7021-intc", sp_intc_init_dt);
320 #endif
321
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
Qin Jian
maintainerv4 cover Add Sunplus SP7021 SoC Support
In reply to Qin JianThis patch series add Sunplus SP7021 SoC support.
Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates many peripherals (ex: UART, I2C, SPI, SDIO, eMMC, USB, SD card and etc.) into a single chip. It is designed for industrial control.
SP7021 consists of two chips (dies) in a package. One is called C-chip (computing chip). It is a 4-core ARM Cortex A7 CPU. It adopts high-level process (22 nm) for high performance computing. The other is called P- chip (peripheral chip). It has many peripherals and an ARM A926 added especially for real-time control. P-chip is made for customers. It adopts low-level process (ex: 0.11 um) to reduce cost.
Refer to (for documentations):
https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
Refer to (applications):
https://tibbo.com/store/plus1.html
Refer to (applications):
http://www.sinovoip.com.cn/ecp_view.asp?id=586
Changes in v4:
- mach-sunplus: add initial support for SP7021
- sp7021_defconfig: add generic SP7021 defconfig
- reset-sunplus: remove Q645 support
- reset-sunplus.c: refine code based on Philipp's review
- clk-sp7021: clock defines add prefix, more clean up
Changes in v3:
- sp7021-intc: remove primary controller mode due to P-chip running Linux not supported any more.
- sp7021-intc.h: removed, not set ext through the DT but sp_intc_set_ext()
- sunplus,sp7021-intc.yaml: update descriptions for above changes
- irq-sp7021-intc.c: more cleanup based on Marc's review
- all driver's Kconfig removed default, it's selected by platform config
Changes in v2:
- sunplus,sp7021-intc.yaml: add descrption for "#interrupt-cells", interrupts
- sunplus,sp7021-intc.yaml: drop "ext0-mask"/"ext1-mask" from DT
- sunplus,sp7021-intc.yaml: fix example.dt too long error
- irq-sp7021-intc.c: major rewrite
- all files with dual license
Qin Jian (10):
dt-bindings: vendor-prefixes: Add Sunplus
dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards
dt-bindings: reset: Add bindings for SP7021 reset driver
reset: Add Sunplus SP7021 reset driver
dt-bindings: clock: Add bindings for SP7021 clock driver
clk: Add Sunplus SP7021 clock driver
dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt
controller
irqchip: Add Sunplus SP7021 interrupt controller driver
ARM: sunplus: Add initial support for Sunplus SP7021 SoC
ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig
.../bindings/arm/sunplus,sp7021.yaml | 27 + .../bindings/clock/sunplus,sp7021-clkc.yaml | 38 + .../sunplus,sp7021-intc.yaml | 62 ++ .../bindings/reset/sunplus,reset.yaml | 38 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + MAINTAINERS | 17 + arch/arm/Kconfig | 20 + arch/arm/Makefile | 2 + arch/arm/configs/sp7021_defconfig | 176 +++++ arch/arm/mach-sunplus/Kconfig | 20 + arch/arm/mach-sunplus/Makefile | 9 + arch/arm/mach-sunplus/Makefile.boot | 3 + arch/arm/mach-sunplus/sp7021.c | 16 + drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-sp7021.c | 725 ++++++++++++++++++ drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sp7021-intc.c | 279 +++++++ drivers/reset/Kconfig | 9 + drivers/reset/Makefile | 1 + drivers/reset/reset-sunplus.c | 133 ++++ include/dt-bindings/clock/sp-sp7021.h | 112 +++ include/dt-bindings/reset/sp-sp7021.h | 97 +++ 24 files changed, 1806 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml create mode 100644 arch/arm/configs/sp7021_defconfig create mode 100644 arch/arm/mach-sunplus/Kconfig create mode 100644 arch/arm/mach-sunplus/Makefile create mode 100644 arch/arm/mach-sunplus/Makefile.boot create mode 100644 arch/arm/mach-sunplus/sp7021.c create mode 100644 drivers/clk/clk-sp7021.c create mode 100644 drivers/irqchip/irq-sp7021-intc.c create mode 100644 drivers/reset/reset-sunplus.c create mode 100644 include/dt-bindings/clock/sp-sp7021.h create mode 100644 include/dt-bindings/reset/sp-sp7021.h
--
2.33.1
Qin Jian
maintainerPATCH v4 1/10 dt-bindings: vendor-prefixes: Add Sunplus
Add vendor prefix for Sunplus Technology Co., Ltd. (http://www.sunplus.com)
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/vendor-prefixes.yaml +2 -0
@@ -1131,6 +1131,8 @@ patternProperties: description: Summit microelectronics "^sunchip,.*": description: Shenzhen Sunchip Technology Co., Ltd + "^sunplus,.*": + description: Sunplus Technology Co., Ltd. "^SUNW,.*": description: Sun Microsystems, Inc "^supermicro,.*":
Signature · 1 line
2.33.1
Rob Herring
maintainerRe: [PATCH v4 01/10] dt-bindings: vendor-prefixes: Add Sunplus
Quoted 7 lines · Qin Jian
Add vendor prefix for Sunplus Technology Co., Ltd. (http://www.sunplus.com)
Signed-off-by Qin Jian <[email protected]>--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
Qin Jian
maintainerPATCH v4 2/10 dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards
In reply to Qin JianThis introduces bindings for boards based Sunplus SP7021 SoC.
--- .../bindings/arm/sunplus,sp7021.yaml | 27 +++++++++++++++++++ MAINTAINERS | 7 +++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml new file +27 -0
@@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Boards Device Tree Bindings + +maintainers: + - qinjian <[email protected]> + +description: | + ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC. + Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sunplus,sp7021-achip + +additionalProperties: true + +...
MAINTAINERS +7 -0
@@ -2655,6 +2655,13 @@ F: drivers/clocksource/armv7m_systick.c N: stm32 N: stm +ARM/SUNPLUS SP7021 SOC SUPPORT +M: Qin Jian <[email protected]> +L: [email protected] (moderated for mon-subscribers) +S: Maintained +W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview +F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml + ARM/Synaptics SoC support M: Jisheng Zhang <[email protected]> M: Sebastian Hesselbarth <[email protected]>
Signature · 1 line
2.33.1
Rob Herring
maintainerRe: [PATCH v4 02/10] dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards
Quoted 9 lines · Qin Jian
This introduces bindings for boards based Sunplus SP7021 SoC.
Signed-off-by Qin Jian <[email protected]>--- .../bindings/arm/sunplus,sp7021.yaml | 27 +++++++++++++++++++ MAINTAINERS | 7 +++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
Qin Jian
maintainerPATCH v4 3/10 dt-bindings: reset: Add bindings for SP7021 reset driver
In reply to Qin JianAdd documentation to describe Sunplus SP7021 reset driver bindings.
--- .../bindings/reset/sunplus,reset.yaml | 38 ++++++++ MAINTAINERS | 2 + include/dt-bindings/reset/sp-sp7021.h | 97 +++++++++++++++++++ 3 files changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml create mode 100644 include/dt-bindings/reset/sp-sp7021.h
Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file +38 -0
@@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Sunplus SoC Reset Controller + +maintainers: + - Qin Jian <[email protected]> + +properties: + compatible: + const: sunplus,sp7021-reset + + "#reset-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#reset-cells" + - reg + +additionalProperties: false + +examples: + - | + rstc: reset@9c000054 { + compatible = "sunplus,sp7021-reset"; + #reset-cells = <1>; + reg = <0x9c000054 0x28>; + }; + +...
MAINTAINERS +2 -0
@@ -2661,6 +2661,8 @@ L: [email protected] (moderated for mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support M: Jisheng Zhang <[email protected]>
include/dt-bindings/reset/sp-sp7021.h new file +97 -0
97 lines not on this page · raw message
Signature · 1 line
2.33.1
Re: [PATCH v4 03/10] dt-bindings: reset: Add bindings for SP7021 reset driver
Quoted 11 lines · Qin Jian
Add documentation to describe Sunplus SP7021 reset driver bindings.
Signed-off-by Qin Jian <[email protected]>--- .../bindings/reset/sunplus,reset.yaml | 38 ++++++++ MAINTAINERS | 2 + include/dt-bindings/reset/sp-sp7021.h | 97 +++++++++++++++++++ 3 files changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml create mode 100644 include/dt-bindings/reset/sp-sp7021.h
Qin Jian
maintainerPATCH v4 4/10 reset: Add Sunplus SP7021 reset driver
In reply to Qin JianAdd reset driver for Sunplus SP7021 SoC.
--- MAINTAINERS | 1 + drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-sunplus.c | 133 ++++++++++++++++++++++++++++++++++ 4 files changed, 144 insertions(+) create mode 100644 drivers/reset/reset-sunplus.c
MAINTAINERS +1 -0
@@ -2662,6 +2662,7 @@ S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: drivers/reset/reset-sunplus.c F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support
drivers/reset/Kconfig +9 -0
@@ -224,6 +224,15 @@ config RESET_SOCFPGA This enables the reset driver for the SoCFPGA ARMv7 platforms. This driver gets initialized early during platform init calls. +config RESET_SUNPLUS + bool "Sunplus SoCs Reset Driver" + depends on ARCH_SUNPLUS || COMPILE_TEST + help + This enables the reset driver support for Sunplus SP7021 SoC family. + Say Y if you want to control reset signals by the reset controller. + Otherwise, say N. + This driver is selected automatically by arm/mach-sunplus platform config. + config RESET_SUNXI bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI default ARCH_SUNXI
drivers/reset/Makefile +1 -0
@@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
drivers/reset/reset-sunplus.c new file +133 -0
133 lines not on this page · raw message
Signature · 1 line
2.33.1
Qin Jian
maintainerPATCH v4 5/10 dt-bindings: clock: Add bindings for SP7021 clock driver
In reply to Qin JianAdd documentation to describe Sunplus SP7021 clock driver bindings.
--- .../bindings/clock/sunplus,sp7021-clkc.yaml | 38 ++++++ MAINTAINERS | 2 + include/dt-bindings/clock/sp-sp7021.h | 112 ++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 include/dt-bindings/clock/sp-sp7021.h
Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file +38 -0
@@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Clock Controller Binding + +maintainers: + - Qin Jian <[email protected]> + +properties: + compatible: + const: sunplus,sp7021-clkc + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + clkc: clkc@9c000000 { + compatible = "sunplus,sp7021-clkc"; + #clock-cells = <1>; + reg = <0x9c000000 0x280>; + }; + +...
MAINTAINERS +2 -0
@@ -2661,8 +2661,10 @@ L: [email protected] (moderated for mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/reset/reset-sunplus.c +F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support
include/dt-bindings/clock/sp-sp7021.h new file +112 -0
112 lines not on this page · raw message
Signature · 1 line
2.33.1
Rob Herring
maintainerRe: [PATCH v4 05/10] dt-bindings: clock: Add bindings for SP7021 clock driver
Quoted 11 lines · Qin Jian
Add documentation to describe Sunplus SP7021 clock driver bindings.
Signed-off-by Qin Jian <[email protected]>--- .../bindings/clock/sunplus,sp7021-clkc.yaml | 38 ++++++ MAINTAINERS | 2 + include/dt-bindings/clock/sp-sp7021.h | 112 ++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 include/dt-bindings/clock/sp-sp7021.h
Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
Qin Jian
maintainerPATCH v4 6/10 clk: Add Sunplus SP7021 clock driver
In reply to Qin JianAdd clock driver for Sunplus SP7021 SoC.
--- MAINTAINERS | 1 + drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-sp7021.c | 725 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 736 insertions(+) create mode 100644 drivers/clk/clk-sp7021.c
MAINTAINERS +1 -0
@@ -2663,6 +2663,7 @@ W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: drivers/clk/clk-sp7021.c F: drivers/reset/reset-sunplus.c F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h
drivers/clk/Kconfig +9 -0
@@ -334,6 +334,15 @@ config COMMON_CLK_VC5 This driver supports the IDT VersaClock 5 and VersaClock 6 programmable clock generators. +config COMMON_CLK_SP7021 + bool "Clock driver for Sunplus SP7021 SoC" + help + This driver supports the Sunplus SP7021 SoC clocks. + It implemented SP7021 PLLs/gate. + Not all features of the PLL are currently supported + by the driver. + This driver is selected automatically by platform config. + config COMMON_CLK_STM32MP157 def_bool COMMON_CLK && MACH_STM32MP157 help
drivers/clk/Makefile +1 -0
@@ -60,6 +60,7 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o obj-$(CONFIG_COMMON_CLK_SI544) += clk-si544.o obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o +obj-$(CONFIG_COMMON_CLK_SP7021) += clk-sp7021.o obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o
drivers/clk/clk-sp7021.c new file +725 -0
725 lines not on this page · raw message
Signature · 1 line
2.33.1
Re: [PATCH v4 06/10] clk: Add Sunplus SP7021 clock driver
drivers/clk/Kconfig config COMMON_CLK_VC5 · line 341
Quoted 13 lines · Qin Jian
drivers/clk/Kconfig +5
-0@@ -334,6 +334,15 @@ config COMMON_CLK_VC5 This driver supports the IDT VersaClock 5 and VersaClock 6 programmable clock generators. +config COMMON_CLK_SP7021 + bool "Clock driver for Sunplus SP7021 SoC" + help + This driver supports the Sunplus SP7021 SoC clocks. + It implemented SP7021 PLLs/gate.
implements
Quoted 3 lines
drivers/clk/Kconfig +3
-0+ Not all features of the PLL are currently supported + by the driver. + This driver is selected automatically by platform config.
Signature · 1 line
~Randy
kernel test robot
build botRe: [PATCH v4 06/10] clk: Add Sunplus SP7021 clock driver
In reply to Qin JianI love your patch! Perhaps something to improve:
Hi Qin,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pza/reset/next]
[also build test WARNING on robh/for-next clk/clk-next tip/irq/core linus/master v5.15 next-20211104] [If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746 base: https://git.pengutronix.de/git/pza/linux reset/next config: xtensa-randconfig-r012-20211104 (attached as .config) compiler: xtensa-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/604141a9aad536dff720a6337561171d72d63d74
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746 git checkout 604141a9aad536dff720a6337561171d72d63d74
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=xtensa
If you fix the issue, kindly add following tag as appropriate
All warnings (new ones prefixed by >>):
drivers/clk/clk-sp7021.c: In function 'plltv_fractional_div':
>> drivers/clk/clk-sp7021.c:292:13: warning: variable 'diff_min_sign' set but not used [-Wunused-but-set-variable]
292 | u32 diff_min_sign = 0;
| ^~~~~~~~~~~~~ drivers/clk/clk-sp7021.c: At top level:
drivers/clk/clk-sp7021.c:625:13: warning: no previous prototype for 'clk_register_sp_pll' [-Wmissing-prototypes]
625 | struct clk *clk_register_sp_pll(const char *name, const char *parent,
| ^~~~~~~~~~~~~~~~~~~
vim +/diff_min_sign +292 drivers/clk/clk-sp7021.c
286
287 static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq)
288 {
289 u32 m, r;
290 u32 nint, nfra;
291 u32 diff_min_quotient = 210000000, diff_min_remainder = 0;
> 292 u32 diff_min_sign = 0;
293 unsigned long fvco, nf, f, fout = 0;
294 int sdm, ph;
295
296 /* check freq */
297 if (freq < F_MIN) {
298 pr_warn("%s: %s freq:%lu < F_MIN:%lu, round up\n",
299 __func__, clk_hw_get_name(&clk->hw), freq, F_MIN);
300 freq = F_MIN;
301 } else if (freq > F_MAX) {
302 pr_warn("%s: %s freq:%lu > F_MAX:%lu, round down\n",
303 __func__, clk_hw_get_name(&clk->hw), freq, F_MAX);
304 freq = F_MAX;
305 }
306
307 /* DIVR 0~3 */
308 for (r = 0; r <= 3; r++) {
309 fvco = freq << r;
310 if (fvco <= FVCO_MAX)
311 break;
312 }
313 f = F_27M >> r;
314
315 /* PH_SEL 1/0 */
316 for (ph = 1; ph >= 0; ph--) {
317 const u32 *pp = pt[ph];
318 u32 ms = 1;
319
320 /* SDM_MOD 0/1 */
321 for (sdm = 0; sdm <= 1; sdm++) {
322 u32 mod = mods[sdm];
323
324 /* DIVM 1~32 */
325 for (m = ms; m <= 32; m++) {
326 u32 diff_freq;
327 u32 diff_freq_quotient = 0, diff_freq_remainder = 0;
328 u32 diff_freq_sign = 0; /* 0:Positive number, 1:Negative number */
329
330 nf = fvco * m;
331 nint = nf / pp[3];
332
333 if (nint < pp[1])
334 continue;
335 if (nint > pp[1])
336 break;
337
338 nfra = (((nf % pp[3]) * mod * pp[4]) + (F_27M / 2)) / F_27M;
339 if (nfra)
340 diff_freq = (f * (nint + pp[2]) / pp[0]) -
341 (f * (mod - nfra) / mod / pp[4]);
342 else
343 diff_freq = (f * (nint) / pp[0]);
344
345 diff_freq_quotient = diff_freq / m;
346 diff_freq_remainder = ((diff_freq % m) * 1000) / m;
347
348 if (freq > diff_freq_quotient) {
349 diff_freq_quotient = freq - diff_freq_quotient - 1;
350 diff_freq_remainder = 1000 - diff_freq_remainder;
351 diff_freq_sign = 1;
352 } else {
353 diff_freq_quotient = diff_freq_quotient - freq;
354 diff_freq_sign = 0;
355 }
356
357 if ((diff_min_quotient > diff_freq_quotient) ||
358 ((diff_min_quotient == diff_freq_quotient) &&
359 (diff_min_remainder > diff_freq_remainder))) {
360
361 /* found a closer freq, save parameters */
362 clk->p[SEL_FRA] = 1;
363 clk->p[SDM_MOD] = sdm;
364 clk->p[PH_SEL] = ph;
365 clk->p[NFRA] = nfra;
366 clk->p[DIVR] = r;
367 clk->p[DIVM] = m; 368
369 fout = diff_freq / m;
370 diff_min_quotient = diff_freq_quotient;
371 diff_min_remainder = diff_freq_remainder;
372 diff_min_sign = diff_freq_sign;
373 }
374 }
375 }
376 }
377
378 if (!fout) {
379 pr_err("%s: %s freq:%lu not found a valid setting\n",
380 __func__, clk_hw_get_name(&clk->hw), freq);
381 return -EINVAL;
382 }
383
384 return fout;
385 }
386
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
kernel test robot
build botRe: [PATCH v4 06/10] clk: Add Sunplus SP7021 clock driver
In reply to Qin JianI love your patch! Yet something to improve:
Hi Qin,
I love your patch! Yet something to improve:
[auto build test ERROR on pza/reset/next]
[also build test ERROR on robh/for-next clk/clk-next tip/irq/core linus/master v5.15 next-20211104] [If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746 base: https://git.pengutronix.de/git/pza/linux reset/next config: arc-allyesconfig (attached as .config) compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/604141a9aad536dff720a6337561171d72d63d74
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746 git checkout 604141a9aad536dff720a6337561171d72d63d74
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
drivers/clk/clk-sp7021.c: In function 'plltv_fractional_div':
>> drivers/clk/clk-sp7021.c:292:13: error: variable 'diff_min_sign' set but not used [-Werror=unused-but-set-variable]
292 | u32 diff_min_sign = 0;
| ^~~~~~~~~~~~~ drivers/clk/clk-sp7021.c: At top level:
drivers/clk/clk-sp7021.c:625:13: error: no previous prototype for 'clk_register_sp_pll' [-Werror=missing-prototypes]
625 | struct clk *clk_register_sp_pll(const char *name, const char *parent,
| ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/diff_min_sign +292 drivers/clk/clk-sp7021.c
286
287 static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq)
288 {
289 u32 m, r;
290 u32 nint, nfra;
291 u32 diff_min_quotient = 210000000, diff_min_remainder = 0;
> 292 u32 diff_min_sign = 0;
293 unsigned long fvco, nf, f, fout = 0;
294 int sdm, ph;
295
296 /* check freq */
297 if (freq < F_MIN) {
298 pr_warn("%s: %s freq:%lu < F_MIN:%lu, round up\n",
299 __func__, clk_hw_get_name(&clk->hw), freq, F_MIN);
300 freq = F_MIN;
301 } else if (freq > F_MAX) {
302 pr_warn("%s: %s freq:%lu > F_MAX:%lu, round down\n",
303 __func__, clk_hw_get_name(&clk->hw), freq, F_MAX);
304 freq = F_MAX;
305 }
306
307 /* DIVR 0~3 */
308 for (r = 0; r <= 3; r++) {
309 fvco = freq << r;
310 if (fvco <= FVCO_MAX)
311 break;
312 }
313 f = F_27M >> r;
314
315 /* PH_SEL 1/0 */
316 for (ph = 1; ph >= 0; ph--) {
317 const u32 *pp = pt[ph];
318 u32 ms = 1;
319
320 /* SDM_MOD 0/1 */
321 for (sdm = 0; sdm <= 1; sdm++) {
322 u32 mod = mods[sdm];
323
324 /* DIVM 1~32 */
325 for (m = ms; m <= 32; m++) {
326 u32 diff_freq;
327 u32 diff_freq_quotient = 0, diff_freq_remainder = 0;
328 u32 diff_freq_sign = 0; /* 0:Positive number, 1:Negative number */
329
330 nf = fvco * m;
331 nint = nf / pp[3];
332
333 if (nint < pp[1])
334 continue;
335 if (nint > pp[1])
336 break;
337
338 nfra = (((nf % pp[3]) * mod * pp[4]) + (F_27M / 2)) / F_27M;
339 if (nfra)
340 diff_freq = (f * (nint + pp[2]) / pp[0]) -
341 (f * (mod - nfra) / mod / pp[4]);
342 else
343 diff_freq = (f * (nint) / pp[0]);
344
345 diff_freq_quotient = diff_freq / m;
346 diff_freq_remainder = ((diff_freq % m) * 1000) / m;
347
348 if (freq > diff_freq_quotient) {
349 diff_freq_quotient = freq - diff_freq_quotient - 1;
350 diff_freq_remainder = 1000 - diff_freq_remainder;
351 diff_freq_sign = 1;
352 } else {
353 diff_freq_quotient = diff_freq_quotient - freq;
354 diff_freq_sign = 0;
355 }
356
357 if ((diff_min_quotient > diff_freq_quotient) ||
358 ((diff_min_quotient == diff_freq_quotient) &&
359 (diff_min_remainder > diff_freq_remainder))) {
360
361 /* found a closer freq, save parameters */
362 clk->p[SEL_FRA] = 1;
363 clk->p[SDM_MOD] = sdm;
364 clk->p[PH_SEL] = ph;
365 clk->p[NFRA] = nfra;
366 clk->p[DIVR] = r;
367 clk->p[DIVM] = m; 368
369 fout = diff_freq / m;
370 diff_min_quotient = diff_freq_quotient;
371 diff_min_remainder = diff_freq_remainder;
372 diff_min_sign = diff_freq_sign;
373 }
374 }
375 }
376 }
377
378 if (!fout) {
379 pr_err("%s: %s freq:%lu not found a valid setting\n",
380 __func__, clk_hw_get_name(&clk->hw), freq);
381 return -EINVAL;
382 }
383
384 return fout;
385 }
386
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
Qin Jian
maintainerPATCH v4 7/10 dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller
In reply to Qin JianAdd documentation to describe Sunplus SP7021 interrupt controller bindings.
--- .../sunplus,sp7021-intc.yaml | 62 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml new file +62 -0
@@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Interrupt Controller Device Tree Bindings + +maintainers: + - Qin Jian <[email protected]> + +properties: + compatible: + items: + - const: sunplus,sp7021-intc + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + description: + The first cell is the IRQ number, the second cell is the trigger + type as defined in interrupt.txt in this directory. + + reg: + maxItems: 2 + description: + Specifies base physical address(s) and size of the controller regs. + The 1st region include type/polarity/priority/mask regs. + The 2nd region include clear/masked_ext0/masked_ext1/group regs. + + interrupts: + maxItems: 2 + description: + EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt + controller. + +required: + - compatible + - interrupt-controller + - "#interrupt-cells" + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + intc: interrupt-controller@9c000780 { + compatible = "sunplus,sp7021-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9c000780 0x80>, <0x9c000a80 0x80>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */ + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */ + }; + +...
MAINTAINERS +1 -0
@@ -2662,6 +2662,7 @@ S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml +F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/clk/clk-sp7021.c F: drivers/reset/reset-sunplus.c
Signature · 1 line
2.33.1
Rob Herring
maintainerRe: [PATCH v4 07/10] dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller
Quoted 9 lines · Qin Jian
Add documentation to describe Sunplus SP7021 interrupt controller bindings.
Signed-off-by Qin Jian <[email protected]>--- .../sunplus,sp7021-intc.yaml | 62 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
Qin Jian
maintainerPATCH v4 8/10 irqchip: Add Sunplus SP7021 interrupt controller driver
In reply to Qin JianAdd interrupt controller driver for Sunplus SP7021 SoC.
This is the interrupt controller in P-chip which collects all interrupt sources in P-chip and routes them to parent interrupt controller in C-chip.
--- MAINTAINERS | 1 + drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sp7021-intc.c | 279 ++++++++++++++++++++++++++++++ 4 files changed, 290 insertions(+) create mode 100644 drivers/irqchip/irq-sp7021-intc.c
MAINTAINERS +1 -0
@@ -2665,6 +2665,7 @@ F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/clk/clk-sp7021.c +F: drivers/irqchip/irq-sp7021-intc.c F: drivers/reset/reset-sunplus.c F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h
drivers/irqchip/Kconfig +9 -0
@@ -602,4 +602,13 @@ config APPLE_AIC Support for the Apple Interrupt Controller found on Apple Silicon SoCs, such as the M1. +config SUNPLUS_SP7021_INTC + bool "Sunplus SP7021 interrupt controller" + help + Support for the Sunplus SP7021 Interrupt Controller IP core. + SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a + chained controller, routed all interrupt source in P-Chip to + the primary controller on C-Chip. + This is selected automatically by platform config. + endmenu
drivers/irqchip/Makefile +1 -0
@@ -116,3 +116,4 @@ obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o obj-$(CONFIG_WPCM450_AIC) += irq-wpcm450-aic.o obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o +obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
drivers/irqchip/irq-sp7021-intc.c new file +279 -0
279 lines not on this page · raw message
Signature · 1 line
2.33.1
Re: [PATCH v4 08/10] irqchip: Add Sunplus SP7021 interrupt controller driver
Quoted 5 lines · Qin Jian
drivers/irqchip/Kconfig +0
-0
drivers/irqchip/Kconfig config APPLE_AIC · line 610
Quoted 9 lines
drivers/irqchip/Kconfig +6
-0@@ -602,4 +602,13 @@ config APPLE_AIC Support for the Apple Interrupt Controller found on Apple Silicon SoCs, such as the M1. +config SUNPLUS_SP7021_INTC + bool "Sunplus SP7021 interrupt controller" + help + Support for the Sunplus SP7021 Interrupt Controller IP core. + SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a + chained controller, routed all interrupt source in P-Chip to
routing all interrupt sources
Quoted 2 lines
drivers/irqchip/Kconfig +2
-0+ the primary controller on C-Chip. + This is selected automatically by platform config.
Signature · 1 line
~Randy
Qin Jian
maintainerPATCH v4 9/10 ARM: sunplus: Add initial support for Sunplus SP7021 SoC
In reply to Qin JianThis patch aims to add an initial support for Sunplus SP7021 SoC.
--- MAINTAINERS | 1 + arch/arm/Kconfig | 20 ++++++++++++++++++++ arch/arm/Makefile | 2 ++ arch/arm/mach-sunplus/Kconfig | 20 ++++++++++++++++++++ arch/arm/mach-sunplus/Makefile | 9 +++++++++ arch/arm/mach-sunplus/Makefile.boot | 3 +++ arch/arm/mach-sunplus/sp7021.c | 16 ++++++++++++++++ 7 files changed, 71 insertions(+) create mode 100644 arch/arm/mach-sunplus/Kconfig create mode 100644 arch/arm/mach-sunplus/Makefile create mode 100644 arch/arm/mach-sunplus/Makefile.boot create mode 100644 arch/arm/mach-sunplus/sp7021.c
MAINTAINERS +1 -0
@@ -2664,6 +2664,7 @@ F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: arch/arm/mach-sunplus/ F: drivers/clk/clk-sp7021.c F: drivers/irqchip/irq-sp7021-intc.c F: drivers/reset/reset-sunplus.c
arch/arm/Kconfig +20 -0
@@ -487,6 +487,24 @@ config ARCH_S3C24XX (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the Samsung SMDK2410 development board (and derivatives). +config ARCH_SUNPLUS + bool "Sunplus SoCs" + select CLKSRC_OF + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_MULTI_HANDLER + select SERIAL_SUNPLUS + select SERIAL_SUNPLUS_CONSOLE + select USE_OF + select RTC_CLASS + select RESET_SUNPLUS + help + Support for Sunplus SoC family: SP7021 and succeed SoCs based systems, + such as the Banana Pi BPI-F2S development board ( and derivatives). + (<http://www.sinovoip.com.cn/ecp_view.asp?id=586>) + (<https://tibbo.com/store/plus1.html>) + config ARCH_OMAP1 bool "TI OMAP1" depends on MMU
@@ -689,6 +707,8 @@ source "arch/arm/mach-sti/Kconfig" source "arch/arm/mach-stm32/Kconfig" +source "arch/arm/mach-sunplus/Kconfig" + source "arch/arm/mach-sunxi/Kconfig" source "arch/arm/mach-tegra/Kconfig"
arch/arm/Makefile +2 -0
@@ -152,6 +152,7 @@ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 textofs-$(CONFIG_ARCH_MESON) := 0x00208000 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 +textofs-$(CONFIG_ARCH_SUNPLUS) := 0x00308000 # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name.
@@ -212,6 +213,7 @@ machine-$(CONFIG_ARCH_RENESAS) += shmobile machine-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_STI) += sti machine-$(CONFIG_ARCH_STM32) += stm32 +machine-$(CONFIG_ARCH_SUNPLUS) += sunplus machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_U8500) += ux500
arch/arm/mach-sunplus/Kconfig new file +20 -0
@@ -0,0 +1,20 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +config SOC_SP7021 + bool "Sunplus SP7021 SoC support" + default y + select CPU_V7 + select ARM_GIC + select SUNPLUS_SP7021_INTC + select HAVE_SMP + select ARM_PSCI + select COMMON_CLK_SP7021 + select PINCTRL + select PINCTRL_SPPCTL + select OF_OVERLAY + select GPIOLIB + help + Support for Sunplus SP7021 SoC. It is based on ARM 4-core + Cotex-A7 with various peripherals (ex: I2C, SPI, SDIO, + Ethernet and etc.), FPGA interface, chip-to-chip bus. + It is designed for industrial control.
arch/arm/mach-sunplus/Makefile new file +9 -0
@@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-$(CONFIG_SOC_SP7021) += sp7021.o +
arch/arm/mach-sunplus/Makefile.boot new file +3 -0
@@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +zreladdr-$(CONFIG_ARCH_SUNPLUS) := 0x00308000
arch/arm/mach-sunplus/sp7021.c new file +16 -0
@@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* +* Copyright (C) Sunplus Technology Co., Ltd. +* All rights reserved. +*/ +#include <linux/kernel.h> +#include <asm/mach/arch.h> + +static const char *sp7021_compat[]__initconst = { +"sunplus,sp7021" , +NULL +}; + +DT_MACHINE_START (SP7021_DT ,"SP7021" ) + .dt_compat = sp7021_compat, +MACHINE_END
Signature · 1 line
2.33.1
Re: [PATCH v4 09/10] ARM: sunplus: Add initial support for Sunplus SP7021 SoC
Quoted 12 lines · Qin Jian
arch/arm/Kconfig +4
-0@@ -487,6 +487,24 @@ config ARCH_S3C24XX (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the Samsung SMDK2410 development board (and derivatives). +config ARCH_SUNPLUS + bool "Sunplus SoCs" + select CLKSRC_OF + select COMMON_CLK
arch/arm/Kconfig config ARCH_S3C24XX · line 503
Quoted 10 lines
arch/arm/Kconfig +10
-0+ select GENERIC_CLOCKEVENTS + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_MULTI_HANDLER + select SERIAL_SUNPLUS + select SERIAL_SUNPLUS_CONSOLE + select USE_OF + select RTC_CLASS + select RESET_SUNPLUS + help + Support for Sunplus SoC family: SP7021 and succeed SoCs based systems,
succeeding or successsor or following
SoC-based systems,
arch/arm/Kconfig config ARCH_S3C24XX · line 504
Quoted 1 line
arch/arm/Kconfig +1
-0+ such as the Banana Pi BPI-F2S development board ( and derivatives).
(and derivatives).
Quoted 2 lines
arch/arm/Kconfig +2
-0+ (<http://www.sinovoip.com.cn/ecp_view.asp?id=586>) + (<https://tibbo.com/store/plus1.html>)
Signature · 1 line
~Randy
Re: [PATCH v4 09/10] ARM: sunplus: Add initial support for Sunplus SP7021 SoC
In reply to Qin JianQuoted 14 lines · Qin Jian
arch/arm/mach-sunplus/Kconfig new file +8
-0@@ -0,0 +1,20 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +config SOC_SP7021 + bool "Sunplus SP7021 SoC support" + default y + select CPU_V7 + select ARM_GIC + select SUNPLUS_SP7021_INTC
arch/arm/mach-sunplus/Kconfig line 18
Quoted 10 lines
arch/arm/mach-sunplus/Kconfig new file +10
-0+ select HAVE_SMP + select ARM_PSCI + select COMMON_CLK_SP7021 + select PINCTRL + select PINCTRL_SPPCTL + select OF_OVERLAY + select GPIOLIB + help + Support for Sunplus SP7021 SoC. It is based on ARM 4-core + Cotex-A7 with various peripherals (ex: I2C, SPI, SDIO,
Is that Cortex-A7
?
Quoted 2 lines
arch/arm/mach-sunplus/Kconfig new file +2
-0+ Ethernet and etc.), FPGA interface, chip-to-chip bus. + It is designed for industrial control.
Signature · 1 line
~Randy
kernel test robot
build botRe: [PATCH v4 09/10] ARM: sunplus: Add initial support for Sunplus SP7021 SoC
In reply to Qin JianI love your patch! Yet something to improve:
Hi Qin,
I love your patch! Yet something to improve:
[auto build test ERROR on pza/reset/next]
[also build test ERROR on robh/for-next clk/clk-next v5.15] [cannot apply to tip/irq/core linus/master next-20211104] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746 base: https://git.pengutronix.de/git/pza/linux reset/next config: arm-randconfig-c002-20211104 (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/a0450f4dfa75b60af973bceea07b1be864ae81ba
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746
git checkout a0450f4dfa75b60af973bceea07b1be864ae81ba
# save the attached .config to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm SHELL=/bin/bash arch/arm/kernel/ arch/arm/mm/
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
arch/arm/kernel/setup.c: In function 'early_print':
arch/arm/kernel/setup.c:372:9: warning: function 'early_print' might be a candidate for 'gnu_printf' format attribute [-Wsuggest-attribute=format]
372 | vsnprintf(buf, sizeof(buf), str, ap);
| ^~~~~~~~~
In file included from arch/arm/kernel/setup.c:36:
arch/arm/kernel/setup.c: In function 'cpuid_init_hwcaps':
>> arch/arm/include/asm/cputype.h:22:25: error: expected ':' or ')' before numeric constant
22 | #define CPUID_EXT_ISAR0 0x60
| ^~~~
arch/arm/include/asm/cputype.h:135:51: note: in definition of macro 'read_cpuid_ext'
135 | asm("mrc p15, 0, %0, c0, " ext_reg \
| ^~~~~~~
arch/arm/kernel/setup.c:457:17: note: in expansion of macro 'cpuid_feature_extract'
457 | block = cpuid_feature_extract(CPUID_EXT_ISAR0, 24);
| ^~~~~~~~~~~~~~~~~~~~~
arch/arm/kernel/setup.c:457:39: note: in expansion of macro 'CPUID_EXT_ISAR0'
457 | block = cpuid_feature_extract(CPUID_EXT_ISAR0, 24);
| ^~~~~~~~~~~~~~~
arch/arm/include/asm/cputype.h:18:25: error: expected ':' or ')' before numeric constant
18 | #define CPUID_EXT_MMFR0 0x50
| ^~~~
arch/arm/include/asm/cputype.h:135:51: note: in definition of macro 'read_cpuid_ext'
135 | asm("mrc p15, 0, %0, c0, " ext_reg \
| ^~~~~~~
arch/arm/kernel/setup.c:464:17: note: in expansion of macro 'cpuid_feature_extract'
464 | block = cpuid_feature_extract(CPUID_EXT_MMFR0, 0);
| ^~~~~~~~~~~~~~~~~~~~~
arch/arm/kernel/setup.c:464:39: note: in expansion of macro 'CPUID_EXT_MMFR0'
464 | block = cpuid_feature_extract(CPUID_EXT_MMFR0, 0);
| ^~~~~~~~~~~~~~~
arch/arm/include/asm/cputype.h:27:25: error: expected ':' or ')' before numeric constant
27 | #define CPUID_EXT_ISAR5 0x74
| ^~~~
arch/arm/include/asm/cputype.h:135:51: note: in definition of macro 'read_cpuid_ext'
135 | asm("mrc p15, 0, %0, c0, " ext_reg \
| ^~~~~~~
arch/arm/kernel/setup.c:469:32: note: in expansion of macro 'CPUID_EXT_ISAR5'
469 | isar5 = read_cpuid_ext(CPUID_EXT_ISAR5);
| ^~~~~~~~~~~~~~~
arch/arm/kernel/setup.c: In function 'elf_hwcap_fixup':
arch/arm/include/asm/cputype.h:25:25: error: expected ':' or ')' before numeric constant
25 | #define CPUID_EXT_ISAR3 0x6c
| ^~~~
arch/arm/include/asm/cputype.h:135:51: note: in definition of macro 'read_cpuid_ext'
135 | asm("mrc p15, 0, %0, c0, " ext_reg \
| ^~~~~~~
arch/arm/kernel/setup.c:513:13: note: in expansion of macro 'cpuid_feature_extract'
513 | if (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) > 1 ||
| ^~~~~~~~~~~~~~~~~~~~~
arch/arm/kernel/setup.c:513:35: note: in expansion of macro 'CPUID_EXT_ISAR3'
513 | if (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) > 1 ||
| ^~~~~~~~~~~~~~~
arch/arm/include/asm/cputype.h:25:25: error: expected ':' or ')' before numeric constant
25 | #define CPUID_EXT_ISAR3 0x6c
| ^~~~
arch/arm/include/asm/cputype.h:135:51: note: in definition of macro 'read_cpuid_ext'
135 | asm("mrc p15, 0, %0, c0, " ext_reg \
| ^~~~~~~
arch/arm/kernel/setup.c:514:14: note: in expansion of macro 'cpuid_feature_extract'
514 | (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) == 1 &&
| ^~~~~~~~~~~~~~~~~~~~~
arch/arm/kernel/setup.c:514:36: note: in expansion of macro 'CPUID_EXT_ISAR3'
514 | (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) == 1 &&
| ^~~~~~~~~~~~~~~
arch/arm/include/asm/cputype.h:26:25: error: expected ':' or ')' before numeric constant
26 | #define CPUID_EXT_ISAR4 0x70
| ^~~~
arch/arm/include/asm/cputype.h:135:51: note: in definition of macro 'read_cpuid_ext'
135 | asm("mrc p15, 0, %0, c0, " ext_reg \
| ^~~~~~~
arch/arm/kernel/setup.c:515:14: note: in expansion of macro 'cpuid_feature_extract'
515 | cpuid_feature_extract(CPUID_EXT_ISAR4, 20) >= 3))
| ^~~~~~~~~~~~~~~~~~~~~
arch/arm/kernel/setup.c:515:36: note: in expansion of macro 'CPUID_EXT_ISAR4'
515 | cpuid_feature_extract(CPUID_EXT_ISAR4, 20) >= 3))
| ^~~~~~~~~~~~~~~ In file included from arch/arm/include/asm/efi.h:12,
from arch/arm/kernel/setup.c:37:
At top level:
arch/arm/include/asm/fixmap.h:39:35: warning: '__end_of_fixed_addresses' defined but not used [-Wunused-const-variable=]
39 | static const enum fixed_addresses __end_of_fixed_addresses =
| ^~~~~~~~~~~~~~~~~~~~~~~~
--
arch/arm/mm/pmsa-v8.c: In function 'prlar_read':
>> arch/arm/mm/pmsa-v8.c:53:16: error: implicit declaration of function 'readl_relaxed' [-Werror=implicit-function-declaration]
53 | return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RLAR);
| ^~~~~~~~~~~~~
>> arch/arm/mm/pmsa-v8.c:53:30: error: 'BASEADDR_V7M_SCB' undeclared (first use in this function)
53 | return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RLAR);
| ^~~~~~~~~~~~~~~~
arch/arm/mm/pmsa-v8.c:53:30: note: each undeclared identifier is reported only once for each function it appears in
>> arch/arm/mm/pmsa-v8.c:53:49: error: 'PMSAv8_RLAR' undeclared (first use in this function); did you mean 'PMSAv8_MAIR'?
53 | return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RLAR);
| ^~~~~~~~~~~
| PMSAv8_MAIR
arch/arm/mm/pmsa-v8.c: In function 'prbar_read':
arch/arm/mm/pmsa-v8.c:58:30: error: 'BASEADDR_V7M_SCB' undeclared (first use in this function)
58 | return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RBAR);
| ^~~~~~~~~~~~~~~~
>> arch/arm/mm/pmsa-v8.c:58:49: error: 'PMSAv8_RBAR' undeclared (first use in this function); did you mean 'PMSAv8_MAIR'?
58 | return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RBAR);
| ^~~~~~~~~~~
| PMSAv8_MAIR
arch/arm/mm/pmsa-v8.c: In function 'prsel_write':
>> arch/arm/mm/pmsa-v8.c:63:9: error: implicit declaration of function 'writel_relaxed' [-Werror=implicit-function-declaration]
63 | writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RNR);
| ^~~~~~~~~~~~~~
arch/arm/mm/pmsa-v8.c:63:27: error: 'BASEADDR_V7M_SCB' undeclared (first use in this function)
63 | writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RNR);
| ^~~~~~~~~~~~~~~~
>> arch/arm/mm/pmsa-v8.c:63:46: error: 'PMSAv8_RNR' undeclared (first use in this function); did you mean 'PMSAv8_MAIR'?
63 | writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RNR);
| ^~~~~~~~~~
| PMSAv8_MAIR
arch/arm/mm/pmsa-v8.c: In function 'prbar_write':
arch/arm/mm/pmsa-v8.c:68:27: error: 'BASEADDR_V7M_SCB' undeclared (first use in this function)
68 | writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RBAR);
| ^~~~~~~~~~~~~~~~
arch/arm/mm/pmsa-v8.c:68:46: error: 'PMSAv8_RBAR' undeclared (first use in this function); did you mean 'PMSAv8_MAIR'?
68 | writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RBAR);
| ^~~~~~~~~~~
| PMSAv8_MAIR
arch/arm/mm/pmsa-v8.c: In function 'prlar_write':
arch/arm/mm/pmsa-v8.c:73:27: error: 'BASEADDR_V7M_SCB' undeclared (first use in this function)
73 | writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RLAR);
| ^~~~~~~~~~~~~~~~
arch/arm/mm/pmsa-v8.c:73:46: error: 'PMSAv8_RLAR' undeclared (first use in this function); did you mean 'PMSAv8_MAIR'?
73 | writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RLAR);
| ^~~~~~~~~~~
| PMSAv8_MAIR
arch/arm/mm/pmsa-v8.c: In function 'prbar_read':
arch/arm/mm/pmsa-v8.c:59:1: error: control reaches end of non-void function [-Werror=return-type]
59 | }
| ^
arch/arm/mm/pmsa-v8.c: In function 'prlar_read':
arch/arm/mm/pmsa-v8.c:54:1: error: control reaches end of non-void function [-Werror=return-type]
54 | }
| ^cc1: some warnings being treated as errors
vim +22 arch/arm/include/asm/cputype.h
0ba8b9b273c45d Russell King 2008-08-10 12
6fae9cdafc92ae Uwe Kleine-König 2013-05-06 13 #ifdef CONFIG_CPU_V7M 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 14 #define CPUID_EXT_PFR0 0x40 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 15 #define CPUID_EXT_PFR1 0x44 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 16 #define CPUID_EXT_DFR0 0x48 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 17 #define CPUID_EXT_AFR0 0x4c 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 18 #define CPUID_EXT_MMFR0 0x50 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 19 #define CPUID_EXT_MMFR1 0x54 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 20 #define CPUID_EXT_MMFR2 0x58 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 21 #define CPUID_EXT_MMFR3 0x5c 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 @22 #define CPUID_EXT_ISAR0 0x60 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 23 #define CPUID_EXT_ISAR1 0x64 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 24 #define CPUID_EXT_ISAR2 0x68 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 25 #define CPUID_EXT_ISAR3 0x6c 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 26 #define CPUID_EXT_ISAR4 0x70 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 27 #define CPUID_EXT_ISAR5 0x74 6fae9cdafc92ae Uwe Kleine-König 2013-05-06 28 #else faa7bc51c11d5b Catalin Marinas 2009-05-30 29 #define CPUID_EXT_PFR0 "c1, 0" faa7bc51c11d5b Catalin Marinas 2009-05-30 30 #define CPUID_EXT_PFR1 "c1, 1" faa7bc51c11d5b Catalin Marinas 2009-05-30 31 #define CPUID_EXT_DFR0 "c1, 2" faa7bc51c11d5b Catalin Marinas 2009-05-30 32 #define CPUID_EXT_AFR0 "c1, 3" faa7bc51c11d5b Catalin Marinas 2009-05-30 33 #define CPUID_EXT_MMFR0 "c1, 4" faa7bc51c11d5b Catalin Marinas 2009-05-30 34 #define CPUID_EXT_MMFR1 "c1, 5" faa7bc51c11d5b Catalin Marinas 2009-05-30 35 #define CPUID_EXT_MMFR2 "c1, 6" faa7bc51c11d5b Catalin Marinas 2009-05-30 36 #define CPUID_EXT_MMFR3 "c1, 7" faa7bc51c11d5b Catalin Marinas 2009-05-30 37 #define CPUID_EXT_ISAR0 "c2, 0" faa7bc51c11d5b Catalin Marinas 2009-05-30 38 #define CPUID_EXT_ISAR1 "c2, 1" faa7bc51c11d5b Catalin Marinas 2009-05-30 39 #define CPUID_EXT_ISAR2 "c2, 2" faa7bc51c11d5b Catalin Marinas 2009-05-30 40 #define CPUID_EXT_ISAR3 "c2, 3" faa7bc51c11d5b Catalin Marinas 2009-05-30 41 #define CPUID_EXT_ISAR4 "c2, 4" faa7bc51c11d5b Catalin Marinas 2009-05-30 42 #define CPUID_EXT_ISAR5 "c2, 5"
6fae9cdafc92ae Uwe Kleine-König 2013-05-06 43 #endif faa7bc51c11d5b Catalin Marinas 2009-05-30 44
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
Qin Jian
maintainerPATCH v4 10/10 ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig
In reply to Qin JianAdd generic Sunplus SP7021 based board defconfig
--- MAINTAINERS | 1 + arch/arm/configs/sp7021_defconfig | 176 ++++++++++++++++++++++++++++++ 2 files changed, 177 insertions(+) create mode 100644 arch/arm/configs/sp7021_defconfig
MAINTAINERS +1 -0
@@ -2664,6 +2664,7 @@ F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: arch/arm/configs/sp7021_*defconfig F: arch/arm/mach-sunplus/ F: drivers/clk/clk-sp7021.c F: drivers/irqchip/irq-sp7021-intc.c
arch/arm/configs/sp7021_defconfig new file +176 -0
176 lines not on this page · raw message
Signature · 1 line
2.33.1
Qin,
Quoted 7 lines · Qin Jian
This patch series add Sunplus SP7021 SoC support.
Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates many peripherals (ex: UART, I2C, SPI, SDIO, eMMC, USB, SD card and etc.) into a single chip. It is designed for industrial control.
Quoted 6 lines
SP7021 consists of two chips (dies) in a package. One is called C-chip (computing chip). It is a 4-core ARM Cortex A7 CPU. It adopts high-level process (22 nm) for high performance computing. The other is called P- chip (peripheral chip). It has many peripherals and an ARM A926 added especially for real-time control. P-chip is made for customers. It adopts low-level process (ex: 0.11 um) to reduce cost.
That's the 3rd version of this series since Friday, two of them during the merge window. All you are achieving is to actually *delay* the review process (at this rate, I'll probably wait until v11 before I take another look at it).
Documentation/process/submitting-patches.rst states it clearly:
<quote>
Wait for a minimum of one week before resubmitting </quote>
So please leave people the time to actually do a good review job, and take the opportunity to review your own patches before posting them again.
Thanks,
M.
Signature · 1 line
Without deviation from the norm, progress is not possible.
qinjian[覃健]
maintainerMarc,
Got it. Thank you for reminding me.
I'm sorry for the previous mistake.
Quoted 48 lines
-----邮件原件-----
发件人: Marc Zyngier <[email protected]>
发送时间: 2021年11月4日 16:23
收件人: qinjian[覃健] <[email protected]>
抄送: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Wells Lu 呂芳騰 <[email protected]>
主题: Re: [PATCH v4 00/10] Add Sunplus SP7021 SoC SupportQin,
Quoted 7 lines · Qin Jian
This patch series add Sunplus SP7021 SoC support.
Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates many peripherals (ex: UART, I2C, SPI, SDIO, eMMC, USB, SD card and etc.) into a single chip. It is designed for industrial control.
Quoted 6 lines
SP7021 consists of two chips (dies) in a package. One is called C-chip (computing chip). It is a 4-core ARM Cortex A7 CPU. It adopts high-level process (22 nm) for high performance computing. The other is called P- chip (peripheral chip). It has many peripherals and an ARM A926 added especially for real-time control. P-chip is made for customers. It adopts low-level process (ex: 0.11 um) to reduce cost.
That's the 3rd version of this series since Friday, two of them during the merge window. All you are achieving is to actually *delay* the review process (at this rate, I'll probably wait until v11 before I take another look at it).
Documentation/process/submitting-patches.rststates it clearly:<quote>
Wait for a minimum of one week before resubmitting </quote>So please leave people the time to actually do a good review job, and take the opportunity to review your own patches before posting them again.
Thanks,
M.--
Without deviation from the norm, progress is not possible.