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Add Sunplus SP7021 SoC Support

PATCH Superseded Qin Jian 3 participants 17 messages Dec 22, 2021 – Jan 10, 2022 1 message not in the archive

Subsystems (7)
Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +3 more subsystems

v7 of 20 Superseded Latest is v20 →

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Qin Jian

author maintainer
#0 lore raw

v7 cover Add Sunplus SP7021 SoC Support

This patch series add Sunplus SP7021 SoC support.

Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates many peripherals (ex: UART, I2C, SPI, SDIO, eMMC, USB, SD card and etc.) into a single chip. It is designed for industrial control.

SP7021 consists of two chips (dies) in a package. One is called C-chip (computing chip). It is a 4-core ARM Cortex A7 CPU. It adopts high-level process (22 nm) for high performance computing. The other is called P- chip (peripheral chip). It has many peripherals and an ARM A926 added especially for real-time control. P-chip is made for customers. It adopts low-level process (ex: 0.11 um) to reduce cost.

Refer to (for documentations):
https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview

Refer to (applications):
https://tibbo.com/store/plus1.html

Refer to (applications):
http://www.sinovoip.com.cn/ecp_view.asp?id=586

Changes in v7:
- sunplus,sp7021-clkc.yaml: Add clocks & clock-names
- clk-sp7021.c: fix the comments form Stephen Boyd
- irq-sp7021-intc.c: fix the comments from Marc

Changes in v6:
- reset-sunplus.c: fix the comments from Philipp
- irq-sp7021-intc.c: fix the comments from Marc
- mach-sunplus: fix the comments from Arnd

Changes in v5:
- reset-sunplus.c: fix strict checks
- clk/Kconfig: fix spell
- clk-sp7021.c: using bitfield ops, fix strict checks
- irqchip/Kconfig: fix spell
- irq-sp7021-intc.c: cleanup error path in probe, fix strict checks
- arm/Kconfig: fix spell & typo, remove CONFIG_SERIAL_SUNPLUS
- mach-sunplus/Kconfig: fix typo
- sp7021_defconfig: add CONFIG_SERIAL_SUNPLUS

Changes in v4:
- mach-sunplus: add initial support for SP7021
- sp7021_defconfig: add generic SP7021 defconfig
- reset-sunplus: remove Q645 support
- reset-sunplus.c: refine code based on Philipp's review
- clk-sp7021: clock defines add prefix, more clean up

Changes in v3:
- sp7021-intc: remove primary controller mode due to P-chip running Linux not supported any more.
- sp7021-intc.h: removed, not set ext through the DT but sp_intc_set_ext()
- sunplus,sp7021-intc.yaml: update descriptions for above changes
- irq-sp7021-intc.c: more cleanup based on Marc's review
- all driver's Kconfig removed default, it's selected by platform config

Changes in v2:
- sunplus,sp7021-intc.yaml: add descrption for "#interrupt-cells", interrupts
- sunplus,sp7021-intc.yaml: drop "ext0-mask"/"ext1-mask" from DT
- sunplus,sp7021-intc.yaml: fix example.dt too long error
- irq-sp7021-intc.c: major rewrite
- all files with dual license

Qin Jian (10):
dt-bindings: vendor-prefixes: Add Sunplus
dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards
dt-bindings: reset: Add bindings for SP7021 reset driver
reset: Add Sunplus SP7021 reset driver
dt-bindings: clock: Add bindings for SP7021 clock driver
clk: Add Sunplus SP7021 clock driver
dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt
controller
irqchip: Add Sunplus SP7021 interrupt controller driver
ARM: sunplus: Add initial support for Sunplus SP7021 SoC
ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig

 .../bindings/arm/sunplus,sp7021.yaml          |  27 +
 .../bindings/clock/sunplus,sp7021-clkc.yaml   |  52 ++
 .../sunplus,sp7021-intc.yaml                  |  62 ++
 .../bindings/reset/sunplus,reset.yaml         |  38 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS                                   |  17 +
 arch/arm/Kconfig                              |   2 +
 arch/arm/Makefile                             |   1 +
 arch/arm/configs/multi_v7_defconfig           |   1 +
 arch/arm/configs/sp7021_defconfig             |  61 ++
 arch/arm/mach-sunplus/Kconfig                 |  26 +
 arch/arm/mach-sunplus/Makefile                |   9 +
 arch/arm/mach-sunplus/sp7021.c                |  16 +
 drivers/clk/Kconfig                           |  10 +-
 drivers/clk/Makefile                          |   1 +
 drivers/clk/clk-sp7021.c                      | 705 ++++++++++++++++++
 drivers/irqchip/Kconfig                       |   9 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-sp7021-intc.c             | 288 +++++++
 drivers/reset/Kconfig                         |   9 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-sunplus.c                 | 130 ++++
 include/dt-bindings/clock/sp-sp7021.h         | 112 +++
 include/dt-bindings/reset/sp-sp7021.h         |  97 +++
 24 files changed, 1676 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 create mode 100644 arch/arm/configs/sp7021_defconfig
 create mode 100644 arch/arm/mach-sunplus/Kconfig
 create mode 100644 arch/arm/mach-sunplus/Makefile
 create mode 100644 arch/arm/mach-sunplus/sp7021.c
 create mode 100644 drivers/clk/clk-sp7021.c
 create mode 100644 drivers/irqchip/irq-sp7021-intc.c
 create mode 100644 drivers/reset/reset-sunplus.c
 create mode 100644 include/dt-bindings/clock/sp-sp7021.h
 create mode 100644 include/dt-bindings/reset/sp-sp7021.h
Signature · 1 line
2.33.1
author maintainer
#1 lore raw

PATCH v7 1/10 dt-bindings: vendor-prefixes: Add Sunplus

Add vendor prefix for Sunplus Technology Co., Ltd. (http://www.sunplus.com)

Acked-by Rob Herring <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/vendor-prefixes.yaml +2 -0
index a867f7102..50d4ee5ac 100644
@@ -1131,6 +1131,8 @@ patternProperties:
     description: Summit microelectronics
   "^sunchip,.*":
     description: Shenzhen Sunchip Technology Co., Ltd
+  "^sunplus,.*":
+    description: Sunplus Technology Co., Ltd.
   "^SUNW,.*":
     description: Sun Microsystems, Inc
   "^supermicro,.*":
Signature · 1 line
2.33.1
author maintainer
#3 lore raw

PATCH v7 2/10 dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards

In reply to Qin Jian

This introduces bindings for boards based Sunplus SP7021 SoC.

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 .../bindings/arm/sunplus,sp7021.yaml          | 27 +++++++++++++++++++
 MAINTAINERS                                   |  7 +++++
 2 files changed, 34 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml new file +27 -0
new file mode 100644
index 000000000..5b9985b73
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus SP7021 Boards Device Tree Bindings
+
+maintainers:
+  - qinjian <[email protected]>
+
+description: |
+  ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC.
+  Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - const: sunplus,sp7021-achip
+
+additionalProperties: true
+
+...
MAINTAINERS +7 -0
index e0bca0de0..6a5422f10 100644
@@ -2655,6 +2655,13 @@ F:	drivers/clocksource/armv7m_systick.c
 N:	stm32
 N:	stm
 
+ARM/SUNPLUS SP7021 SOC SUPPORT
+M:	Qin Jian <[email protected]>
+L:	[email protected] (moderated for mon-subscribers)
+S:	Maintained
+W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
+F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
+
 ARM/Synaptics SoC support
 M:	Jisheng Zhang <[email protected]>
 M:	Sebastian Hesselbarth <[email protected]>
Signature · 1 line
2.33.1
author maintainer
#4 lore raw

PATCH v7 3/10 dt-bindings: reset: Add bindings for SP7021 reset driver

In reply to Qin Jian

Add documentation to describe Sunplus SP7021 reset driver bindings.

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 .../bindings/reset/sunplus,reset.yaml         | 38 ++++++++
 MAINTAINERS                                   |  2 +
 include/dt-bindings/reset/sp-sp7021.h         | 97 +++++++++++++++++++
 3 files changed, 137 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 create mode 100644 include/dt-bindings/reset/sp-sp7021.h
Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file +38 -0
new file mode 100644
index 000000000..c083c821f
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Sunplus SoC Reset Controller
+
+maintainers:
+  - Qin Jian <[email protected]>
+
+properties:
+  compatible:
+    const: sunplus,sp7021-reset
+
+  "#reset-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#reset-cells"
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    rstc: reset@9c000054 {
+      compatible = "sunplus,sp7021-reset";
+      #reset-cells = <1>;
+      reg = <0x9c000054 0x28>;
+    };
+
+...
MAINTAINERS +2 -0
index 6a5422f10..652f42cab 100644
@@ -2661,6 +2661,8 @@ L:	[email protected] (moderated for mon-subscribers)
 S:	Maintained
 W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
 F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
+F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
+F:	include/dt-bindings/reset/sp-sp7021.h
 
 ARM/Synaptics SoC support
 M:	Jisheng Zhang <[email protected]>
include/dt-bindings/reset/sp-sp7021.h new file +97 -0

97 lines not on this page · raw message

Signature · 1 line
2.33.1
author maintainer
#5 lore raw

PATCH v7 4/10 reset: Add Sunplus SP7021 reset driver

In reply to Qin Jian

Add reset driver for Sunplus SP7021 SoC.

Reviewed-by Philipp Zabel <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 MAINTAINERS                   |   1 +
 drivers/reset/Kconfig         |   9 +++
 drivers/reset/Makefile        |   1 +
 drivers/reset/reset-sunplus.c | 130 ++++++++++++++++++++++++++++++++++
 4 files changed, 141 insertions(+)
 create mode 100644 drivers/reset/reset-sunplus.c
MAINTAINERS +1 -0
index 652f42cab..6caffd6d0 100644
@@ -2662,6 +2662,7 @@ S:	Maintained
 W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
 F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
+F:	drivers/reset/reset-sunplus.c
 F:	include/dt-bindings/reset/sp-sp7021.h
 
 ARM/Synaptics SoC support
drivers/reset/Kconfig +9 -0
index be799a5ab..fb14456a8 100644
@@ -224,6 +224,15 @@ config RESET_SOCFPGA
 	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
 	  driver gets initialized early during platform init calls.
 
+config RESET_SUNPLUS
+	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
+	default ARCH_SUNPLUS
+	help
+	  This enables the reset driver support for Sunplus SoCs.
+	  The reset lines that can be asserted and deasserted by toggling bits
+	  in a contiguous, exclusive register space. The register is HIWORD_MASKED,
+	  which means each register hold 16 reset lines.
+
 config RESET_SUNXI
 	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
 	default ARCH_SUNXI
drivers/reset/Makefile +1 -0
index 21d46d886..f03403e97 100644
@@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
+obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
drivers/reset/reset-sunplus.c new file +130 -0

130 lines not on this page · raw message

Signature · 1 line
2.33.1
author maintainer
#6 lore raw

PATCH v7 5/10 dt-bindings: clock: Add bindings for SP7021 clock driver

In reply to Qin Jian

Add documentation to describe Sunplus SP7021 clock driver bindings.

Signed-off-by Qin Jian <[email protected]>

---
Add clocks & clock-names.

---
 .../bindings/clock/sunplus,sp7021-clkc.yaml   |  52 ++++++++
 MAINTAINERS                                   |   2 +
 include/dt-bindings/clock/sp-sp7021.h         | 112 ++++++++++++++++++
 3 files changed, 166 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 create mode 100644 include/dt-bindings/clock/sp-sp7021.h
Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file +52 -0
new file mode 100644
index 000000000..e6d098cf4
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus SP7021 SoC Clock Controller Binding
+
+maintainers:
+  - Qin Jian <[email protected]>
+
+properties:
+  compatible:
+    const: sunplus,sp7021-clkc
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: External oscillator clock
+      - description: System clock
+
+  clock-names:
+    items:
+      - const: extclk
+      - const: pllsys
+
+required:
+  - compatible
+  - "#clock-cells"
+  - reg
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    clkc: clock-controller@9c000000 {
+      compatible = "sunplus,sp7021-clkc";
+      #clock-cells = <1>;
+      reg = <0x9c000000 0x280>;
+      clocks = <&extclk>, <&clkc PLL_SYS>;
+      clock-names = "extclk", "pllsys";
+    };
+
+...
MAINTAINERS +2 -0
index 6caffd6d0..90ebb823f 100644
@@ -2661,8 +2661,10 @@ L:	[email protected] (moderated for mon-subscribers)
 S:	Maintained
 W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
 F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
+F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 F:	drivers/reset/reset-sunplus.c
+F:	include/dt-bindings/clock/sp-sp7021.h
 F:	include/dt-bindings/reset/sp-sp7021.h
 
 ARM/Synaptics SoC support
include/dt-bindings/clock/sp-sp7021.h new file +112 -0

112 lines not on this page · raw message

Signature · 1 line
2.33.1
maintainer Reviewed-by on v7 5/10
#7 lore raw

Re: [PATCH v7 05/10] dt-bindings: clock: Add bindings for SP7021 clock driver

Quoted 5 lines · Qin Jian

Add documentation to describe Sunplus SP7021 clock driver bindings.

Signed-off-by Qin Jian <[email protected]>

---
Add clocks & clock-names.

Quoted 8 lines
---
 .../bindings/clock/sunplus,sp7021-clkc.yaml   |  52 ++++++++
 MAINTAINERS                                   |   2 +
 include/dt-bindings/clock/sp-sp7021.h         | 112 ++++++++++++++++++
 3 files changed, 166 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 create mode 100644 include/dt-bindings/clock/sp-sp7021.h
Reviewed-by Rob Herring <[email protected]>
author maintainer
#9 lore raw

PATCH v7 6/10 clk: Add Sunplus SP7021 clock driver

In reply to Qin Jian

Add clock driver for Sunplus SP7021 SoC.

Signed-off-by Qin Jian <[email protected]>

---
Fix the comments from Stephen Boyd.

---
 MAINTAINERS              |   1 +
 drivers/clk/Kconfig      |  10 +-
 drivers/clk/Makefile     |   1 +
 drivers/clk/clk-sp7021.c | 705 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 716 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/clk-sp7021.c
MAINTAINERS +1 -0
index 90ebb823f..5069f552f 100644
@@ -2663,6 +2663,7 @@ W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
 F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
+F:	drivers/clk/clk-sp7021.c
 F:	drivers/reset/reset-sunplus.c
 F:	include/dt-bindings/clock/sp-sp7021.h
 F:	include/dt-bindings/reset/sp-sp7021.h
drivers/clk/Kconfig +9 -1
index c5b3dc973..4a186ccf6 100644
@@ -334,6 +334,15 @@ config COMMON_CLK_VC5
 	  This driver supports the IDT VersaClock 5 and VersaClock 6
 	  programmable clock generators.
 
+config COMMON_CLK_SP7021
+	bool "Clock driver for Sunplus SP7021 SoC"
+	default SOC_SP7021
+	help
+	  This driver supports the Sunplus SP7021 SoC clocks.
+	  It implements SP7021 PLLs/gate.
+	  Not all features of the PLL are currently supported
+	  by the driver.
+
 config COMMON_CLK_STM32MP157
 	def_bool COMMON_CLK && MACH_STM32MP157
 	help

@@ -366,7 +375,6 @@ config COMMON_CLK_MMP2
 
 config COMMON_CLK_MMP2_AUDIO
         tristate "Clock driver for MMP2 Audio subsystem"
-        depends on COMMON_CLK_MMP2 || COMPILE_TEST
         help
           This driver supports clocks for Audio subsystem on MMP2 SoC.
drivers/clk/Makefile +1 -0
index e42312121..f15bb5070 100644
@@ -60,6 +60,7 @@ obj-$(CONFIG_COMMON_CLK_SI5351)		+= clk-si5351.o
 obj-$(CONFIG_COMMON_CLK_SI514)		+= clk-si514.o
 obj-$(CONFIG_COMMON_CLK_SI544)		+= clk-si544.o
 obj-$(CONFIG_COMMON_CLK_SI570)		+= clk-si570.o
+obj-$(CONFIG_COMMON_CLK_SP7021)		+= clk-sp7021.o
 obj-$(CONFIG_COMMON_CLK_STM32F)		+= clk-stm32f4.o
 obj-$(CONFIG_COMMON_CLK_STM32H7)	+= clk-stm32h7.o
 obj-$(CONFIG_COMMON_CLK_STM32MP157)	+= clk-stm32mp1.o
drivers/clk/clk-sp7021.c new file +705 -0

705 lines not on this page · raw message

Signature · 1 line
2.33.1
maintainer
#10 lore raw

Re: [PATCH v7 06/10] clk: Add Sunplus SP7021 clock driver

Quoting Qin Jian (2021-12-21 23:06:02)

Quoted 21 lines
drivers/clk/Kconfig +9 -0
index c5b3dc973..4a186ccf6 100644
@@ -334,6 +334,15 @@ config COMMON_CLK_VC5
          This driver supports the IDT VersaClock 5 and VersaClock 6
          programmable clock generators.
 
+config COMMON_CLK_SP7021
+       bool "Clock driver for Sunplus SP7021 SoC"
+       default SOC_SP7021
+       help
+         This driver supports the Sunplus SP7021 SoC clocks.
+         It implements SP7021 PLLs/gate.
+         Not all features of the PLL are currently supported
+         by the driver.
+
 config COMMON_CLK_STM32MP157
        def_bool COMMON_CLK && MACH_STM32MP157
        help

drivers/clk/Kconfig config COMMON_CLK_MMP2 · line 380

Quoted 7 lines
drivers/clk/Kconfig +0 -1
@@ -366,7 +375,6 @@ config COMMON_CLK_MMP2
 
 config COMMON_CLK_MMP2_AUDIO
         tristate "Clock driver for MMP2 Audio subsystem"
-        depends on COMMON_CLK_MMP2 || COMPILE_TEST
         help
           This driver supports clocks for Audio subsystem on MMP2 SoC.

What's the relevance of this hunk to this patch? Can you drop this part?

Quoted 24 lines
drivers/clk/clk-sp7021.c new file +18 -0
new file mode 100644
index 000000000..6df87f0a6
@@ -0,0 +1,705 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (C) Sunplus Technology Co., Ltd.
+ *       All rights reserved.
+ */
+//#define DEBUG
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/bitfield.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <dt-bindings/clock/sp-sp7021.h>
+
+#define REG(i)         (pll_regs + (i) * 4)
+

[....]

drivers/clk/clk-sp7021.c line 363

Quoted 7 lines
drivers/clk/clk-sp7021.c new file +7 -0
+
+static long plltv_div(struct sp_pll *clk, unsigned long freq)
+{
+       if (freq % 100)
+               return plltv_fractional_div(clk, freq);
+       else
+               return plltv_integer_div(clk, freq);

Drop else please

Quoted 13 lines
drivers/clk/clk-sp7021.c new file +13 -0
+}
+
+static void plltv_set_rate(struct sp_pll *clk)
+{
+       u32 reg;
+
+       reg  = HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]);
+       reg |= HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]);
+       reg |= HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]);
+       reg |= HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]);
+       writel(reg, clk->reg);
+
+       reg  = HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]);

[...]

Quoted 10 lines
drivers/clk/clk-sp7021.c new file +10 -0
+       .set_rate = sp_pll_set_rate
+};
+
+static const struct clk_ops sp_pll_sub_ops = {
+       .enable = sp_pll_enable,
+       .disable = sp_pll_disable,
+       .is_enabled = sp_pll_is_enabled,
+       .recalc_rate = sp_pll_recalc_rate,
+};
+

drivers/clk/clk-sp7021.c line 607

Quoted 10 lines
drivers/clk/clk-sp7021.c new file +10 -0
+struct clk_hw *sp_pll_register(const char *name, const char *parent,
+                              void __iomem *reg, int pd_bit, int bp_bit,
+                              unsigned long brate, int shift, int width,
+                              spinlock_t *lock)
+{
+       struct sp_pll *pll;
+       struct clk_hw *hw;
+       struct clk_init_data initd = {
+               .name = name,
+               .parent_names = &parent,

Any chance clk_parent_data can be used instead of string names?

drivers/clk/clk-sp7021.c line 617

Quoted 10 lines
drivers/clk/clk-sp7021.c new file +10 -0
+               .ops = (bp_bit >= 0) ? &sp_pll_ops : &sp_pll_sub_ops,
+               .num_parents = 1,
+       };
+       int ret;
+
+       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+       if (!pll)
+               return ERR_PTR(-ENOMEM);
+
+       if (reg == PLLSYS_CTL) /* system clock, should not be closed */

s/closed/disabled/

Quoted 8 lines
drivers/clk/clk-sp7021.c new file +8 -0
+               initd.flags |= CLK_IS_CRITICAL;
+
+       pll->hw.init = &initd;
+       pll->reg = reg;
+       pll->pd_bit = pd_bit;
+       pll->bp_bit = bp_bit;
+       pll->brate = brate;
+       pll->div_shift = shift;

drivers/clk/clk-sp7021.c line 635

Quoted 10 lines
drivers/clk/clk-sp7021.c new file +10 -0
+       pll->div_width = width;
+       pll->lock = lock;
+
+       hw = &pll->hw;
+       ret = clk_hw_register(NULL, hw);
+       if (ret) {
+               kfree(pll);
+               hw = ERR_PTR(ret);
+       } else {
+               pr_info("%-20s%lu\n", name, clk_hw_get_rate(hw));

Drop this print or make it pr_debug()

Quoted 51 lines
drivers/clk/clk-sp7021.c new file +51 -0
+               clk_hw_register_clkdev(hw, NULL, name);
+       }
+
+       return hw;
+}
+
+static void __init sp_clk_setup(struct device_node *np)
+{
+       int i, j;
+       struct clk_hw **hws;
+
+       sp_clk_base = of_iomap(np, 0);
+       if (WARN_ON(!sp_clk_base))
+               return; /* -ENXIO */
+
+       sp_clk_data = kzalloc(struct_size(sp_clk_data, hws, CLK_MAX), GFP_KERNEL);
+       if (!sp_clk_data)
+               return; /* -ENOMEM */
+
+       hws = sp_clk_data->hws;
+
+       /* PLL_A */
+       hws[PLL_A] = sp_pll_register("plla", EXTCLK, PLLA_CTL, 11, 12,
+                                    27000000, 0, DIV_A, &plla_lock);
+
+       /* PLL_E */
+       hws[PLL_E] = sp_pll_register("plle", EXTCLK, PLLE_CTL, 6, 2,
+                                    50000000, 0, 0, &plle_lock);
+       hws[PLL_E_2P5] = sp_pll_register("plle_2p5", "plle", PLLE_CTL, 13, -1,
+                                        2500000, 0, 0, &plle_lock);
+       hws[PLL_E_25] = sp_pll_register("plle_25", "plle", PLLE_CTL, 12, -1,
+                                       25000000, 0, 0, &plle_lock);
+       hws[PLL_E_112P5] = sp_pll_register("plle_112p5", "plle", PLLE_CTL, 11, -1,
+                                          112500000, 0, 0, &plle_lock);
+
+       /* PLL_F */
+       hws[PLL_F] = sp_pll_register("pllf", EXTCLK, PLLF_CTL, 0, 10,
+                                    13500000, 1, 4, &pllf_lock);
+
+       /* PLL_TV */
+       hws[PLL_TV] = sp_pll_register("plltv", EXTCLK, PLLTV_CTL, 0, 15,
+                                     27000000, 0, DIV_TV, &plltv_lock);
+       hws[PLL_TV_A] = clk_hw_register_divider(NULL, "plltv_a", "plltv", 0,
+                                               PLLTV_CTL + 4, 5, 1,
+                                               CLK_DIVIDER_POWER_OF_TWO,
+                                               &plltv_lock);
+       clk_hw_register_clkdev(hws[PLL_TV_A], NULL, "plltv_a");
+
+       /* PLL_SYS */
+       hws[PLL_SYS] = sp_pll_register("pllsys", EXTCLK, PLLSYS_CTL, 10, 9,
+                                      13500000, 0, 4, &pllsys_lock);

drivers/clk/clk-sp7021.c line 696

Quoted 10 lines
drivers/clk/clk-sp7021.c new file +10 -0
+
+       /* gates */
+       for (i = 0; i < ARRAY_SIZE(gates); i++) {
+               char s[10];
+
+               j = gates[i] & 0xffff;
+               sprintf(s, "clken%02x", j);
+               hws[j] = clk_hw_register_gate(NULL, s,
+                                             parents[gates[i] >> 16].fw_name,
+                                             CLK_IGNORE_UNUSED,

Why CLK_IGNORE_UNUSED? There should be a comment or it should be replaced with CLK_IS_CRITICAL.

drivers/clk/clk-sp7021.c line 705

Quoted 9 lines
drivers/clk/clk-sp7021.c new file +9 -0
+                                             clk_regs + (j >> 4) * 4, j & 0x0f,
+                                             CLK_GATE_HIWORD_MASK, NULL);
+       }
+
+       sp_clk_data->num = CLK_MAX;
+       of_clk_add_hw_provider(np, of_clk_hw_onecell_get, sp_clk_data);
+}
+
+CLK_OF_DECLARE_DRIVER(sp_clkc, "sunplus,sp7021-clkc", sp_clk_setup);

Why CLK_OF_DECLARE_DRIVER? There should be a comment but better would be to make a platform driver instead. If the platform driver can't be used, we need to know what other device driver is probing based on this clkc compatible string.

author maintainer
#11 lore raw

RE: [PATCH v7 06/10] clk: Add Sunplus SP7021 clock driver

Quoted 7 lines

drivers/clk/clk-sp7021.c line 705

Quoted 2 lines
drivers/clk/clk-sp7021.c new file +2 -0
+
+CLK_OF_DECLARE_DRIVER(sp_clkc, "sunplus,sp7021-clkc", sp_clk_setup);

Why CLK_OF_DECLARE_DRIVER? There should be a comment but better would be to make a platform driver instead. If the platform driver can't be used, we need to know what other device driver is probing based on this clkc compatible string.

Dear Stephen,

Sorry, I don't understand your comment.
Did you mean, like below:

static int sp7021_clk_probe(struct platform_device *pdev)

{
	......
	sp_clk_data->num = CLK_MAX;
	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, sp_clk_data);
}
static const struct of_device_id sp7021_clk_dt_ids[] = {
	{ .compatible = "sunplus,sp7021-clkc", },
	{ }
};

MODULE_DEVICE_TABLE(of, sp7021_clk_dt_ids);

static struct platform_driver sp7021_clk_driver = {
	.probe  = sp7021_clk_probe,
	.driver = {
		.name = "sp7021-clk",
		.of_match_table = sp7021_clk_dt_ids,
	},
};

builtin_platform_driver(sp7021_clk_driver);

But, It's doesn't work.
Most other clk drivers used CLK_OF_DECLARE_DRIVER or CLK_OF_DECLARE. I just take these as the reference and it's working.

A message that is not in the archive (sent off-list or not yet received): [email protected]

author maintainer
#13 lore raw

RE: [PATCH v7 06/10] clk: Add Sunplus SP7021 clock driver

Quoted 40 lines
Quoted 33 lines
Quoted 7 lines

drivers/clk/clk-sp7021.c line 705

Quoted 2 lines
drivers/clk/clk-sp7021.c new file +2 -0
+
+CLK_OF_DECLARE_DRIVER(sp_clkc, "sunplus,sp7021-clkc", sp_clk_setup);

Why CLK_OF_DECLARE_DRIVER? There should be a comment but better would be to make a platform driver instead. If the platform driver can't be used, we need to know what other device driver is probing based on this clkc compatible string.

Dear Stephen,

Sorry, I don't understand your comment.
Did you mean, like below:

static int sp7021_clk_probe(struct platform_device *pdev)

{
        ......
        sp_clk_data->num = CLK_MAX;
        return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, sp_clk_data);
}
static const struct of_device_id sp7021_clk_dt_ids[] = {
        { .compatible = "sunplus,sp7021-clkc", },
        { }
};

MODULE_DEVICE_TABLE(of, sp7021_clk_dt_ids);

static struct platform_driver sp7021_clk_driver = {
        .probe  = sp7021_clk_probe,
        .driver = {
                .name = "sp7021-clk",
                .of_match_table = sp7021_clk_dt_ids,
        },
};
Quoted 4 lines

builtin_platform_driver(sp7021_clk_driver);

But, It's doesn't work.

Why doesn't it work?

Quoted 7 lines
Quoted 2 lines

Most other clk drivers used CLK_OF_DECLARE_DRIVER or CLK_OF_DECLARE. I just take these as the reference and it's working.

CLK_OF_DECLARE is for clks that need to be registered so the main irqchip and/or clocksource/clockevent can operate properly. CLK_OF_DECLARE_DRIVER is for the case that there's another driver that will attach to the device node that has the compatible string.

After some trace, I found:
In our dts, 'clkc' node defined @ clocks:

	clocks {
		...
		clkc: clock-controller@9c000000 {
			#clock-cells = <1>;
			compatible = "sunplus,sp7021-clkc";
			reg = <0x9c000000 0x280>; // G0:CLKEN ~ G4:PLL
			clocks = <&extclk>, <&clkc PLL_SYS>;
			clock-names = "extclk", "pllsys";
		};
	};
	soc {
		...
	}

In this case, clk driver write as platform driver not work (sp7021_clk_probe not called) But, CLK_OF_DECLARE and CLK_OF_DECLARE_DRIVER both worked (called from clk_of_init)

Then, I move the 'clkc' mode from 'clocks' to 'soc':

	clocks {
		...
	};
	soc {
		...
		clkc: clock-controller@9c000000 {
			#clock-cells = <1>;
			compatible = "sunplus,sp7021-clkc";
			reg = <0x9c000000 0x280>; // G0:CLKEN ~ G4:PLL
			clocks = <&extclk>, <&clkc PLL_SYS>;
			clock-names = "extclk", "pllsys";
		};
	}

In this case, clk driver write as platform driver worked (called from platform_probe)
CLK_OF_DECLARE and CLK_OF_DECLARE_DRIVER also both worked. (still called from clk_of_init, more early than platform_probe)

It looks like CLK_OF_DECLARE/CLK_OF_DECLARE_DRIVER is better than platform driver. Why you prefer platform driver?

author maintainer
#14 lore raw

PATCH v7 7/10 dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller

In reply to Qin Jian

Add documentation to describe Sunplus SP7021 interrupt controller bindings.

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 .../sunplus,sp7021-intc.yaml                  | 62 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml new file +62 -0
new file mode 100644
index 000000000..5daeab63c
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus SP7021 SoC Interrupt Controller Device Tree Bindings
+
+maintainers:
+  - Qin Jian <[email protected]>
+
+properties:
+  compatible:
+    items:
+      - const: sunplus,sp7021-intc
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+    description:
+      The first cell is the IRQ number, the second cell is the trigger
+      type as defined in interrupt.txt in this directory.
+
+  reg:
+    maxItems: 2
+    description:
+      Specifies base physical address(s) and size of the controller regs.
+      The 1st region include type/polarity/priority/mask regs.
+      The 2nd region include clear/masked_ext0/masked_ext1/group regs.
+
+  interrupts:
+    maxItems: 2
+    description:
+      EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt
+      controller.
+
+required:
+  - compatible
+  - interrupt-controller
+  - "#interrupt-cells"
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    intc: interrupt-controller@9c000780 {
+        compatible = "sunplus,sp7021-intc";
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        reg = <0x9c000780 0x80>, <0x9c000a80 0x80>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */
+                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */
+    };
+
+...
MAINTAINERS +1 -0
index 5069f552f..6b3bbe021 100644
@@ -2662,6 +2662,7 @@ S:	Maintained
 W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
 F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
+F:	Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 F:	drivers/clk/clk-sp7021.c
 F:	drivers/reset/reset-sunplus.c
Signature · 1 line
2.33.1
author maintainer
#15 lore raw

PATCH v7 8/10 irqchip: Add Sunplus SP7021 interrupt controller driver

In reply to Qin Jian

Add interrupt controller driver for Sunplus SP7021 SoC.

This is the interrupt controller in P-chip which collects all interrupt sources in P-chip and routes them to parent interrupt controller in C-chip.

Signed-off-by Qin Jian <[email protected]>

---
Fix the comments from Marc.

---
 MAINTAINERS                       |   1 +
 drivers/irqchip/Kconfig           |   9 +
 drivers/irqchip/Makefile          |   1 +
 drivers/irqchip/irq-sp7021-intc.c | 288 ++++++++++++++++++++++++++++++
 4 files changed, 299 insertions(+)
 create mode 100644 drivers/irqchip/irq-sp7021-intc.c
MAINTAINERS +1 -0
index 6b3bbe021..febbd97bf 100644
@@ -2665,6 +2665,7 @@ F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:	Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 F:	drivers/clk/clk-sp7021.c
+F:	drivers/irqchip/irq-sp7021-intc.c
 F:	drivers/reset/reset-sunplus.c
 F:	include/dt-bindings/clock/sp-sp7021.h
 F:	include/dt-bindings/reset/sp-sp7021.h
drivers/irqchip/Kconfig +9 -0
index aca7b595c..32d7a8e0c 100644
@@ -602,4 +602,13 @@ config APPLE_AIC
 	  Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
 	  such as the M1.
 
+config SUNPLUS_SP7021_INTC
+	bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
+	default SOC_SP7021
+	help
+	  Support for the Sunplus SP7021 Interrupt Controller IP core.
+	  SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
+	  chained controller, routing all interrupt source in P-Chip to
+	  the primary controller on C-Chip.
+
 endmenu
drivers/irqchip/Makefile +1 -0
index f88cbf36a..75411f654 100644
@@ -116,3 +116,4 @@ obj-$(CONFIG_MACH_REALTEK_RTL)		+= irq-realtek-rtl.o
 obj-$(CONFIG_WPCM450_AIC)		+= irq-wpcm450-aic.o
 obj-$(CONFIG_IRQ_IDT3243X)		+= irq-idt3243x.o
 obj-$(CONFIG_APPLE_AIC)			+= irq-apple-aic.o
+obj-$(CONFIG_SUNPLUS_SP7021_INTC)	+= irq-sp7021-intc.o
drivers/irqchip/irq-sp7021-intc.c new file +288 -0

288 lines not on this page · raw message

Signature · 1 line
2.33.1
author maintainer
#16 lore raw

PATCH v7 9/10 ARM: sunplus: Add initial support for Sunplus SP7021 SoC

In reply to Qin Jian

This patch aims to add an initial support for Sunplus SP7021 SoC.

Reviewed-by Arnd Bergmann <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 MAINTAINERS                    |  1 +
 arch/arm/Kconfig               |  2 ++
 arch/arm/Makefile              |  1 +
 arch/arm/mach-sunplus/Kconfig  | 26 ++++++++++++++++++++++++++
 arch/arm/mach-sunplus/Makefile |  9 +++++++++
 arch/arm/mach-sunplus/sp7021.c | 16 ++++++++++++++++
 6 files changed, 55 insertions(+)
 create mode 100644 arch/arm/mach-sunplus/Kconfig
 create mode 100644 arch/arm/mach-sunplus/Makefile
 create mode 100644 arch/arm/mach-sunplus/sp7021.c
MAINTAINERS +1 -0
index febbd97bf..0ae537a41 100644
@@ -2664,6 +2664,7 @@ F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:	Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
+F:	arch/arm/mach-sunplus/
 F:	drivers/clk/clk-sp7021.c
 F:	drivers/irqchip/irq-sp7021-intc.c
 F:	drivers/reset/reset-sunplus.c
arch/arm/Kconfig +2 -0
index 59baf6c13..8c7883b5a 100644
@@ -689,6 +689,8 @@ source "arch/arm/mach-sti/Kconfig"
 
 source "arch/arm/mach-stm32/Kconfig"
 
+source "arch/arm/mach-sunplus/Kconfig"
+
 source "arch/arm/mach-sunxi/Kconfig"
 
 source "arch/arm/mach-tegra/Kconfig"
arch/arm/Makefile +1 -0
index 847c31e7c..973ffb830 100644
@@ -212,6 +212,7 @@ machine-$(CONFIG_ARCH_RENESAS)	 	+= shmobile
 machine-$(CONFIG_ARCH_INTEL_SOCFPGA)	+= socfpga
 machine-$(CONFIG_ARCH_STI)		+= sti
 machine-$(CONFIG_ARCH_STM32)		+= stm32
+machine-$(CONFIG_ARCH_SUNPLUS)		+= sunplus
 machine-$(CONFIG_ARCH_SUNXI)		+= sunxi
 machine-$(CONFIG_ARCH_TEGRA)		+= tegra
 machine-$(CONFIG_ARCH_U8500)		+= ux500
arch/arm/mach-sunplus/Kconfig new file +26 -0
new file mode 100644
index 000000000..e720606dd
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+menuconfig ARCH_SUNPLUS
+	bool "Sunplus SoCs"
+	depends on ARCH_MULTI_V7
+	help
+	  Support for Sunplus SoC family: SP7021 and succeeding SoC-based systems,
+	  such as the Banana Pi BPI-F2S development board (and derivatives).
+	  (<http://www.sinovoip.com.cn/ecp_view.asp?id=586>)
+	  (<https://tibbo.com/store/plus1.html>)
+
+config SOC_SP7021
+	bool "Sunplus SP7021 SoC support"
+	depends on ARCH_SUNPLUS
+	default ARCH_SUNPLUS
+	select ARM_GIC
+	select ARM_PSCI
+	select PINCTRL
+	select PINCTRL_SPPCTL
+	select SERIAL_SUNPLUS
+	select SERIAL_SUNPLUS_CONSOLE
+	help
+	  Support for Sunplus SP7021 SoC. It is based on ARM 4-core
+	  Cortex-A7 with various peripherals (ex: I2C, SPI, SDIO,
+	  Ethernet and etc.), FPGA interface,  chip-to-chip bus.
+	  It is designed for industrial control.
arch/arm/mach-sunplus/Makefile new file +9 -0
new file mode 100644
index 000000000..c902580a7
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-$(CONFIG_SOC_SP7021)	+= sp7021.o
+
arch/arm/mach-sunplus/sp7021.c new file +16 -0
new file mode 100644
index 000000000..774d0a5bd
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (C) Sunplus Technology Co., Ltd.
+ *       All rights reserved.
+ */
+#include <linux/kernel.h>
+#include <asm/mach/arch.h>
+
+static const char *sp7021_compat[] __initconst = {
+	"sunplus,sp7021",
+	NULL
+};
+
+DT_MACHINE_START(SP7021_DT, "SP7021")
+	.dt_compat	= sp7021_compat,
+MACHINE_END
Signature · 1 line
2.33.1
author maintainer
#17 lore raw

PATCH v7 10/10 ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig

In reply to Qin Jian

Add generic Sunplus SP7021 based board defconfig

Reviewed-by Arnd Bergmann <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 MAINTAINERS                         |  1 +
 arch/arm/configs/multi_v7_defconfig |  1 +
 arch/arm/configs/sp7021_defconfig   | 61 +++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+)
 create mode 100644 arch/arm/configs/sp7021_defconfig
MAINTAINERS +1 -0
index 0ae537a41..9340f8760 100644
@@ -2664,6 +2664,7 @@ F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:	Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
+F:	arch/arm/configs/sp7021_*defconfig
 F:	arch/arm/mach-sunplus/
 F:	drivers/clk/clk-sp7021.c
 F:	drivers/irqchip/irq-sp7021-intc.c
arch/arm/configs/multi_v7_defconfig +1 -0
index b4f74454f..585e3b5d3 100644
@@ -87,6 +87,7 @@ CONFIG_MACH_SPEAR1310=y
 CONFIG_MACH_SPEAR1340=y
 CONFIG_ARCH_STI=y
 CONFIG_ARCH_STM32=y
+CONFIG_ARCH_SUNPLUS=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_ARCH_UNIPHIER=y
arch/arm/configs/sp7021_defconfig new file +61 -0

61 lines not on this page · raw message

Signature · 1 line
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