Update the Icicle Kit device tree

From: Conor Dooley <[email protected]>

The services actually provided by the system controller are not documented so add some words about what the system controller can actually do. Add a link to the oneline documentation with the specific details of each individual service.
Also, drop the unneeded label from the example.

Signed-off-by Conor Dooley <[email protected]>

---
  .../soc/microchip/microchip,mpfs-sys-controller.yaml  | 11 ++++++++---
  1 file changed, 8 insertions(+), 3 deletions(-)

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +8 -3

index f699772fedf3..b0dae51e1d42 100644
@@ -10,9 +10,14 @@ maintainers:
    - Conor Dooley <[email protected]>
 
  description: |
-  The PolarFire SoC system controller is communicated with via a mailbox.
-  This document describes the bindings for the client portion of that mailbox.
+  PolarFire SoC devices include a microcontroller acting as the system controller,
+  which provides "services" to the main processor and to the FPGA fabric. These
+  services include hardware rng, reprogramming of the FPGA and verfification of the
+  eNVM contents etc. More information on these services can be found online, at
+  https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
 
+  Communication with the system controller is done via a mailbox, of which the client
+  portion is documented here.
 
  properties:
    mboxes:

@@ -29,7 +34,7 @@ additionalProperties: false
 
  examples:
    - |
-    syscontroller: syscontroller {
+    syscontroller {
        compatible = "microchip,mpfs-sys-controller";
        mboxes = <&mbox 0>;
      };

From: Conor Dooley <[email protected]>

The services actually provided by the system controller are not documented so add some words about what the system controller can actually do. Add a link to the oneline documentation with the specific details of each individual service.
Also, drop the unneeded label from the example.

Signed-off-by Conor Dooley <[email protected]>

---
 .../soc/microchip/microchip,mpfs-sys-controller.yaml  | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

From: Conor Dooley <[email protected]>

Add device tree bindings for the real time clock on the Microchip PolarFire SoC.

Signed-off-by Daire McNamara <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
  .../bindings/rtc/microchip,mfps-rtc.yaml      | 58 +++++++++++++++++++
  1 file changed, 58 insertions(+)

create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file +58 -0

new file mode 100644
index 000000000000..a2e984ea3553
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
+
+allOf:
+  - $ref: rtc.yaml#
+
+maintainers:
+  - Daire McNamara <[email protected]>
+  - Lewis Hanly <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - microchip,mpfs-rtc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: |
+          RTC_WAKEUP interrupt
+      - description: |
+          RTC_MATCH, asserted when the content of the Alarm register is equal
+          to that of the RTC's count register.
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: rtc
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    rtc@20124000 {
+        compatible = "microchip,mpfs-rtc";
+        reg = <0x20124000 0x1000>;
+        clocks = <&clkcfg 21>;
+        clock-names = "rtc";
+        interrupts = <80>, <81>;
+    };
+...

Hi Alessandro, Alexandre,
If one of you could take a look at this, that'd be great.

Thanks,
Conor.

Quoted 78 lines · On 14/02/2022 13:58, [email protected] wrote:

From: Conor Dooley <[email protected]>

Add device tree bindings for the real time clock on the Microchip PolarFire SoC.

Signed-off-by Daire McNamara <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
  .../bindings/rtc/microchip,mfps-rtc.yaml      | 58 +++++++++++++++++++
  1 file changed, 58 insertions(+)

create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file +58 -0

new file mode 100644
index 000000000000..a2e984ea3553
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
+
+allOf:
+  - $ref: rtc.yaml#
+
+maintainers:
+  - Daire McNamara <[email protected]>
+  - Lewis Hanly <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - microchip,mpfs-rtc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: |
+          RTC_WAKEUP interrupt
+      - description: |
+          RTC_MATCH, asserted when the content of the Alarm register is equal
+          to that of the RTC's count register.
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: rtc
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    rtc@20124000 {
+        compatible = "microchip,mpfs-rtc";
+        reg = <0x20124000 0x1000>;
+        clocks = <&clkcfg 21>;
+        clock-names = "rtc";
+        interrupts = <80>, <81>;
+    };
+...

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Quoted 2 lines · On 23/02/2022 07:41:27+0000, [email protected] wrote:

Hi Alessandro, Alexandre,
If one of you could take a look at this, that'd be great.

I actually expected someone else to apply this, what is your plan?

Quoted 75 lines

Thanks,
Conor.

Quoted 70 lines · On 14/02/2022 13:58, [email protected] wrote:

From: Conor Dooley <[email protected]>

Add device tree bindings for the real time clock on the Microchip PolarFire SoC.

Signed-off-by Daire McNamara <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
   .../bindings/rtc/microchip,mfps-rtc.yaml      | 58 +++++++++++++++++++
   1 file changed, 58 insertions(+)

create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file +50 -0

new file mode 100644
index 000000000000..a2e984ea3553
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
+
+allOf:
+  - $ref: rtc.yaml#
+
+maintainers:
+  - Daire McNamara <[email protected]>
+  - Lewis Hanly <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - microchip,mpfs-rtc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: |
+          RTC_WAKEUP interrupt
+      - description: |
+          RTC_MATCH, asserted when the content of the Alarm register is equal
+          to that of the RTC's count register.
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: rtc
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |

Quoted 9 lines

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml line 58

Quoted 8 lines

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file +8 -0

+    rtc@20124000 {
+        compatible = "microchip,mpfs-rtc";
+        reg = <0x20124000 0x1000>;
+        clocks = <&clkcfg 21>;
+        clock-names = "rtc";
+        interrupts = <80>, <81>;
+    };
+...

--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Quoted 3 lines · Alexandre Belloni

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

On 23/02/2022 07:41:27+0000, [email protected] wrote:

Quoted 4 lines

Quoted 2 lines

Hi Alessandro, Alexandre,
If one of you could take a look at this, that'd be great.

I actually expected someone else to apply this, what is your plan?

I was going to ask Palmer to take the series via riscv. Since I have Rob's R-b, I was just looking for a subsystem maintainer ack/R-b before actually asking him.

Thanks,
Conor.

Quoted 89 lines

Quoted 75 lines

Thanks,
Conor.

Quoted 70 lines · On 14/02/2022 13:58, [email protected] wrote:

From: Conor Dooley <[email protected]>

Add device tree bindings for the real time clock on the Microchip PolarFire SoC.

Signed-off-by Daire McNamara <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
   .../bindings/rtc/microchip,mfps-rtc.yaml      | 58 +++++++++++++++++++
   1 file changed, 58 insertions(+)

create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file +50 -0

new file mode 100644
index 000000000000..a2e984ea3553
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
+
+allOf:
+  - $ref: rtc.yaml#
+
+maintainers:
+  - Daire McNamara <[email protected]>
+  - Lewis Hanly <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - microchip,mpfs-rtc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: |
+          RTC_WAKEUP interrupt
+      - description: |
+          RTC_MATCH, asserted when the content of the Alarm register is equal
+          to that of the RTC's count register.
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: rtc
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |

Quoted 9 lines

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml line 58

Quoted 8 lines

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file +8 -0

+    rtc@20124000 {
+        compatible = "microchip,mpfs-rtc";
+        reg = <0x20124000 0x1000>;
+        clocks = <&clkcfg 21>;
+        clock-names = "rtc";
+        interrupts = <80>, <81>;
+    };
+...

--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Quoted 4 lines · On 23/02/2022 15:25:00+0000, [email protected] wrote:

Quoted 3 lines · Alexandre Belloni

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

On 23/02/2022 07:41:27+0000, [email protected] wrote:

Quoted 9 lines

Quoted 4 lines

Quoted 2 lines

Hi Alessandro, Alexandre,
If one of you could take a look at this, that'd be great.

I actually expected someone else to apply this, what is your plan?

I was going to ask Palmer to take the series via riscv. Since I have Rob's R-b, I was just looking for a subsystem maintainer ack/R-b before actually asking him.

Rob's review is enough for a DT binding, no need to wait for me. but FWIW:

Acked-by Alexandre Belloni <[email protected]>

Quoted 95 lines

Thanks,
Conor.

Quoted 89 lines

Quoted 75 lines

Thanks,
Conor.

Quoted 70 lines · On 14/02/2022 13:58, [email protected] wrote:

From: Conor Dooley <[email protected]>

Add device tree bindings for the real time clock on the Microchip PolarFire SoC.

Signed-off-by Daire McNamara <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
    .../bindings/rtc/microchip,mfps-rtc.yaml      | 58 +++++++++++++++++++
    1 file changed, 58 insertions(+)

create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file +50 -0

new file mode 100644
index 000000000000..a2e984ea3553
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
+
+allOf:
+  - $ref: rtc.yaml#
+
+maintainers:
+  - Daire McNamara <[email protected]>
+  - Lewis Hanly <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - microchip,mpfs-rtc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: |
+          RTC_WAKEUP interrupt
+      - description: |
+          RTC_MATCH, asserted when the content of the Alarm register is equal
+          to that of the RTC's count register.
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: rtc
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |

Quoted 9 lines

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml line 58

Quoted 8 lines

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file +8 -0

+    rtc@20124000 {
+        compatible = "microchip,mpfs-rtc";
+        reg = <0x20124000 0x1000>;
+        clocks = <&clkcfg 21>;
+        clock-names = "rtc";
+        interrupts = <80>, <81>;
+    };
+...

--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

From: Conor Dooley <[email protected]>

Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

---
  .../bindings/pwm/microchip,corepwm.yaml       | 81 +++++++++++++++++++
  1 file changed, 81 insertions(+)

create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml

Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml new file +81 -0

new file mode 100644
index 000000000000..a7fae1772a81
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip IP corePWM controller bindings
+
+maintainers:
+  - Conor Dooley <[email protected]>
+
+description: |
+  corePWM is an 16 channel pulse width modulator FPGA IP
+
+  https://www.microsemi.com/existing-parts/parts/152118
+
+allOf:
+  - $ref: pwm.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: microchip,corepwm-rtl-v4
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  "#pwm-cells":
+    const: 2
+
+  microchip,sync-update-mask:
+    description: |
+      Depending on how the IP is instantiated, there are two modes of operation.
+      In synchronous mode, all channels are updated at the beginning of the PWM period,
+      and in asynchronous mode updates happen as the control registers are written.
+      A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
+      mode is possible for each channel, and is set by the bitstream programmed to the
+      FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
+      control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
+      At runtime a bit wide register exposed to APB can be used to toggle on/off
+      synchronised mode for all channels it has been synthesised for.
+      Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
+      whether synchronous mode is possible for the PWM channel.
+
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  microchip,dac-mode-mask:
+    description: |
+      Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
+      a minimum period pulse train whose High/Low average is that of the chosen duty
+      cycle. This "DAC" will have far better bandwidth and ripple performance than the
+      standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
+      core, set at instantiation and by the bitstream programmed to the FPGA, determines
+      whether a given channel operates in regular PWM or DAC mode.
+      Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
+      for that channel.
+
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    pwm@41000000 {
+      compatible = "microchip,corepwm-rtl-v4";
+      microchip,sync-update-mask = /bits/ 32 <0>;
+      clocks = <&clkcfg 30>;
+      reg = <0x41000000 0xF0>;
+      #pwm-cells = <2>;
+    };

From: Conor Dooley <[email protected]>

Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

Quoted 8 lines · On Mon, Feb 14, 2022 at 01:58:35PM +0000, [email protected] wrote:

From: Conor Dooley <[email protected]>

Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

I like it:

Acked-by Uwe Kleine-König <[email protected]>

nitpick: Put your S-o-b last in the commit log. (This doesn't justify a resend IMHO)

Quoted 12 lines · Uwe Kleine-König

Quoted 8 lines · On Mon, Feb 14, 2022 at 01:58:35PM +0000, [email protected] wrote:

From: Conor Dooley <[email protected]>

Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

I like it:

Quoted 4 lines

Acked-by Uwe Kleine-König <[email protected]>

nitpick: Put your S-o-b last in the commit log. (This doesn't justify a resend IMHO)

It should be the opposite - the first. First author signs the patch, then comes review and finally an ack. Putting SoB at then suggests that tags were accumulated before sending patch, out of mailing list.

Quoted 13 lines · Krzysztof Kozlowski

Quoted 12 lines · Uwe Kleine-König

Quoted 8 lines · On Mon, Feb 14, 2022 at 01:58:35PM +0000, [email protected] wrote:

From: Conor Dooley <[email protected]>

Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

I like it:

Quoted 8 lines

Quoted 4 lines

Acked-by Uwe Kleine-König <[email protected]>

nitpick: Put your S-o-b last in the commit log. (This doesn't justify a resend IMHO)

It should be the opposite - the first. First author signs the patch, then comes review and finally an ack. Putting SoB at then suggests that tags were accumulated before sending patch, out of mailing list.

well, or in an earlier revision of this patch as is the case here. One of the ideas of S-o-b is that the order shows the flow of the patch states and if this patch ends in git with:

Referred-by Rob Herring <[email protected]>

Singed-off-by Conor Dooley <[email protected]>

Backed-by Palmer Dabbelt <[email protected]>

Singed-off-by Peter Maintainer <[email protected]>

I'd expect that Backed-by was added by Peter, not Conor. (Modified the tags on purpose to not interfere with b4's tag pickup, I guess you humans still get the point.)

Quoted 13 lines · Krzysztof Kozlowski

Quoted 12 lines · Uwe Kleine-König

Quoted 8 lines · On Mon, Feb 14, 2022 at 01:58:35PM +0000, [email protected] wrote:

From: Conor Dooley <[email protected]>

Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

I like it:

Quoted 8 lines

Quoted 4 lines

Acked-by Uwe Kleine-König <[email protected]>

nitpick: Put your S-o-b last in the commit log. (This doesn't justify a resend IMHO)

It should be the opposite - the first. First author signs the patch, then comes review and finally an ack. Putting SoB at then suggests that tags were accumulated before sending patch, out of mailing list.

well, or in an earlier revision of this patch as is the case here. One of the ideas of S-o-b is that the order shows the flow of the patch states and if this patch ends in git with:

Referred-by Rob Herring <[email protected]>

Singed-off-by Conor Dooley <[email protected]>

Backed-by Palmer Dabbelt <[email protected]>

Singed-off-by Peter Maintainer <[email protected]>

I'd expect that Backed-by was added by Peter, not Conor. (Modified the tags on purpose to not interfere with b4's tag pickup, I guess you humans still get the point.)

From: Conor Dooley <[email protected]>

Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

Acked-by Palmer Dabbelt <[email protected]>

---
 .../bindings/pwm/microchip,corepwm.yaml       | 81 +++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml

From: Conor Dooley <[email protected]>

This series updates the Microchip Icicle Kit device tree by adding a host of peripherals, and some updates to the memory map. In addition, the device tree has been split into a third part, which contains "soft" peripherals that are in the fpga fabric.

Several of the entries are for peripherals that have not get had their drivers upstreamed, so in those cases the dt bindings are included where appropriate in order to avoid the many "DT compatible string <x> appears un-documented" errors.

Depends on mpfs clock driver binding (on clk/next) to provide dt-bindings/clock/microchip,mpfs-clock.h for the device tree and on the other changes to the icicle/mpfs device tree from geert that are already in linux/riscv/for-next.

Additionally, the interrupt-extended warnings on the plic/clint are cleared by [1] & [2].

[1] https://lore.kernel.org/linux-riscv/[email protected]/
[2] https://lore.kernel.org/linux-riscv/[email protected]/

Changes from v6:
- Dropped i2c patch, as its in i2c-next
- Added ack on gpio, reviewed-by on rtc
- Dropped child nodes from sysctrl binding entirely, added a link to the online documenation for the services the system controller can provide
- Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's series

Changes from v5:
- reworded the descriptions in the pwm binding to (hopefully) add clarity
- added -mask to the custom properties and made them 32 bit
- renamed the i2c binding to corei2c, since it is not mpfs specific
- removed the child nodes of the system controller in example/dts & will create them in the driver.
@Rob, I assume keeping them documented is the correct thing to do?
- removed the dependancy on the clock binding from the examples
- reformatted rtc interrupts as per Rob's suggestion

Changes from v4:
- dont include icicle_kit_defconfig, accidentally added in v3
- drop prescaler from mpfs-rtc & calculate the value instead
- use corei2c as a fallback device for mpfs-i2c
- drop spi dt-binding (on spi-next)
commit 2da187304e556ac59cf2dacb323cc78ded988169
- drop usb dt-binding (on usb-next)

Changes from v3:
- drop "mailbox: change mailbox-mpfs compatible string", already upstream:
commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
- fix copy paste error in microchip,mpfs-mailbox dt-binding
- remove whitespace in syscontroller dt entry

Changes from v2:
- dropped plic int header & corresponding defines in dts{,i}
- use $ref to drmode in mpfs-musb binding
- split changes to dts{,i} again: functional changes to existing elements now are in a new patch
- drop num-cs property in mpfs-spi binding
- dont make the system controller a simple-mfd
- move the separate bindings for rng/generic system services into the system controller binding
- added an instance corei2c as i2c2 in the fabric dtsi
- add version numbering to corepwm and corei2c compat string (-rtl-vN)

Conor Dooley (11):
dt-bindings: soc/microchip: update syscontroller compatibles
dt-bindings: soc/microchip: add info about services to mpfs sysctrl
dt-bindings: rtc: add bindings for microchip mpfs rtc
dt-bindings: gpio: add bindings for microchip mpfs gpio
dt-bindings: pwm: add microchip corepwm binding
riscv: dts: microchip: use clk defines for icicle kit
riscv: dts: microchip: add fpga fabric section to icicle kit
riscv: dts: microchip: refactor icicle kit device tree
riscv: dts: microchip: update peripherals in icicle kit device tree
riscv: dts: microchip: add new peripherals to icicle kit device tree
MAINTAINERS: update riscv/microchip entry

  .../bindings/gpio/microchip,mpfs-gpio.yaml    |  79 ++++++
  ...ilbox.yaml => microchip,mpfs-mailbox.yaml} |   6 +-
  .../bindings/pwm/microchip,corepwm.yaml       |  81 ++++++
  .../bindings/rtc/microchip,mfps-rtc.yaml      |  58 ++++
  .../microchip,mpfs-sys-controller.yaml        |  40 +++
  ...icrochip,polarfire-soc-sys-controller.yaml |  35 ---
  MAINTAINERS                                   |   2 +
  .../dts/microchip/microchip-mpfs-fabric.dtsi  |  25 ++
  .../microchip/microchip-mpfs-icicle-kit.dts   | 115 ++++++--
  .../boot/dts/microchip/microchip-mpfs.dtsi    | 254 ++++++++++++++----
  10 files changed, 591 insertions(+), 104 deletions(-)

create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi

Quoted 12 lines · On 14/02/2022 13:58, [email protected] wrote:

From: Conor Dooley <[email protected]>

This series updates the Microchip Icicle Kit device tree by adding a host of peripherals, and some updates to the memory map. In addition, the device tree has been split into a third part, which contains "soft" peripherals that are in the fpga fabric.

Several of the entries are for peripherals that have not get had their drivers upstreamed, so in those cases the dt bindings are included where appropriate in order to avoid the many "DT compatible string <x> appears un-documented" errors.

Quoted 4 lines

Depends on mpfs clock driver binding (on clk/next) to provide dt-bindings/clock/microchip,mpfs-clock.h for the device tree and on the other changes to the icicle/mpfs device tree from geert that are already in linux/riscv/for-next.

Quoted 6 lines

Additionally, the interrupt-extended warnings on the plic/clint are cleared by [1] & [2].

[1] https://lore.kernel.org/linux-riscv/[email protected]/
[2] https://lore.kernel.org/linux-riscv/[email protected]/

Hey Palmer,

dt-bindings should be set now, so if you're still happy to take the series via riscv, that'd be great. i2c, spi & usb patches ended going via the sub-system trees (and have been dropped from the series), in case those generate warnings for you.

Thanks,
Conor.

Quoted 79 lines

Changes from v6:
- Dropped i2c patch, as its in i2c-next
- Added ack on gpio, reviewed-by on rtc
- Dropped child nodes from sysctrl binding entirely, added a link to the online documenation for the services the system controller can provide
- Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's series

Changes from v5:
- reworded the descriptions in the pwm binding to (hopefully) add clarity
- added -mask to the custom properties and made them 32 bit
- renamed the i2c binding to corei2c, since it is not mpfs specific
- removed the child nodes of the system controller in example/dts & will create them in the driver.
@Rob, I assume keeping them documented is the correct thing to do?
- removed the dependancy on the clock binding from the examples
- reformatted rtc interrupts as per Rob's suggestion

Changes from v4:
- dont include icicle_kit_defconfig, accidentally added in v3
- drop prescaler from mpfs-rtc & calculate the value instead
- use corei2c as a fallback device for mpfs-i2c
- drop spi dt-binding (on spi-next)
commit 2da187304e556ac59cf2dacb323cc78ded988169
- drop usb dt-binding (on usb-next)

Changes from v3:
- drop "mailbox: change mailbox-mpfs compatible string", already upstream:
commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
- fix copy paste error in microchip,mpfs-mailbox dt-binding
- remove whitespace in syscontroller dt entry

Changes from v2:
- dropped plic int header & corresponding defines in dts{,i}
- use $ref to drmode in mpfs-musb binding
- split changes to dts{,i} again: functional changes to existing elements now are in a new patch
- drop num-cs property in mpfs-spi binding
- dont make the system controller a simple-mfd
- move the separate bindings for rng/generic system services into the system controller binding
- added an instance corei2c as i2c2 in the fabric dtsi
- add version numbering to corepwm and corei2c compat string (-rtl-vN)

Conor Dooley (11):
dt-bindings: soc/microchip: update syscontroller compatibles
dt-bindings: soc/microchip: add info about services to mpfs sysctrl
dt-bindings: rtc: add bindings for microchip mpfs rtc
dt-bindings: gpio: add bindings for microchip mpfs gpio
dt-bindings: pwm: add microchip corepwm binding
riscv: dts: microchip: use clk defines for icicle kit
riscv: dts: microchip: add fpga fabric section to icicle kit
riscv: dts: microchip: refactor icicle kit device tree
riscv: dts: microchip: update peripherals in icicle kit device tree
riscv: dts: microchip: add new peripherals to icicle kit device tree
MAINTAINERS: update riscv/microchip entry

  .../bindings/gpio/microchip,mpfs-gpio.yaml    |  79 ++++++
  ...ilbox.yaml => microchip,mpfs-mailbox.yaml} |   6 +-
  .../bindings/pwm/microchip,corepwm.yaml       |  81 ++++++
  .../bindings/rtc/microchip,mfps-rtc.yaml      |  58 ++++
  .../microchip,mpfs-sys-controller.yaml        |  40 +++
  ...icrochip,polarfire-soc-sys-controller.yaml |  35 ---
  MAINTAINERS                                   |   2 +
  .../dts/microchip/microchip-mpfs-fabric.dtsi  |  25 ++
  .../microchip/microchip-mpfs-icicle-kit.dts   | 115 ++++++--
  .../boot/dts/microchip/microchip-mpfs.dtsi    | 254 ++++++++++++++----
  10 files changed, 591 insertions(+), 104 deletions(-)

create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Quoted 13 lines · On Wed, 23 Feb 2022 12:48:16 PST (-0800), [email protected] wrote:

Quoted 12 lines · On 14/02/2022 13:58, [email protected] wrote:

From: Conor Dooley <[email protected]>

This series updates the Microchip Icicle Kit device tree by adding a host of peripherals, and some updates to the memory map. In addition, the device tree has been split into a third part, which contains "soft" peripherals that are in the fpga fabric.

Several of the entries are for peripherals that have not get had their drivers upstreamed, so in those cases the dt bindings are included where appropriate in order to avoid the many "DT compatible string <x> appears un-documented" errors.

Quoted 4 lines

Quoted 4 lines

Depends on mpfs clock driver binding (on clk/next) to provide dt-bindings/clock/microchip,mpfs-clock.h for the device tree and on the other changes to the icicle/mpfs device tree from geert that are already in linux/riscv/for-next.

So that's causing this to not build, as I can't build without the header.  I went ahead and put these on top of that patch, resulting in

   * 48e8641c2bf0 - (HEAD -> riscv-microchip, palmer/riscv-microchip) MAINTAINERS: update riscv/microchip entry (2 minutes ago) <Conor Dooley>
   * 528a5b1f2556 - riscv: dts: microchip: add new peripherals to icicle kit device tree (2 minutes ago) <Conor Dooley>
   * 5b28df37d311 - riscv: dts: microchip: update peripherals in icicle kit device tree (2 minutes ago) <Conor Dooley>
   * c5094f371008 - riscv: dts: microchip: refactor icicle kit device tree (2 minutes ago) <Conor Dooley>
   * 72560c6559b8 - riscv: dts: microchip: add fpga fabric section to icicle kit (2 minutes ago) <Conor Dooley>
   * 6546f920868e - riscv: dts: microchip: use clk defines for icicle kit (2 minutes ago) <Conor Dooley>
   * df77f7735786 - dt-bindings: pwm: add microchip corepwm binding (2 minutes ago) <Conor Dooley>
   * 735806d8a68e - dt-bindings: gpio: add bindings for microchip mpfs gpio (2 minutes ago) <Conor Dooley>
   * 4cbcc0d7b397 - dt-bindings: rtc: add bindings for microchip mpfs rtc (2 minutes ago) <Conor Dooley>
   * b435a1728c9f - dt-bindings: soc/microchip: add info about services to mpfs sysctrl (2 minutes ago) <Conor Dooley>
   * 213556235526 - dt-bindings: soc/microchip: update syscontroller compatibles (2 minutes ago) <Conor Dooley>
   * 2145bb687e3f - (clk/clk-microchip) dt-bindings: clk: microchip: Add Microchip PolarFire host binding (6 weeks ago) <Daire McNamara>
   * e783362eb54c - (tag: v5.17-rc1) Linux 5.17-rc1 (7 weeks ago) <Linus Torvalds>

sboyd: IIRC it's OK to consider clk-microchip as a stable branch?  If not I can just wait until you send your PR to Linus and send this later in the merge window, no big deal on my end.

I've put this on for-next.  If that's a problem let me know and I'll delay it.

Thanks!

Quoted 7 lines

Quoted 6 lines

Additionally, the interrupt-extended warnings on the plic/clint are cleared by [1] & [2].

[1] https://lore.kernel.org/linux-riscv/[email protected]/
[2] https://lore.kernel.org/linux-riscv/[email protected]/

Quoted 6 lines

Hey Palmer,

dt-bindings should be set now, so if you're still happy to take the series via riscv, that'd be great. i2c, spi & usb patches ended going via the sub-system trees (and have been dropped from the series), in case those generate warnings for you.

Something went off the rails in email land and #0 and #2 didn't end up in my patch queue but the rest did.  Luckily enough made it through that it didn't get lost, and lore's pretty great so this sort of thing isn't that big of a deal these days.  That said, email is a bit of a black box so figured I'd give you a heads up.

Quoted 83 lines

Thanks,
Conor.

Quoted 79 lines

Changes from v6:
- Dropped i2c patch, as its in i2c-next
- Added ack on gpio, reviewed-by on rtc
- Dropped child nodes from sysctrl binding entirely, added a link to the online documenation for the services the system controller can provide
- Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's series

Changes from v5:
- reworded the descriptions in the pwm binding to (hopefully) add clarity
- added -mask to the custom properties and made them 32 bit
- renamed the i2c binding to corei2c, since it is not mpfs specific
- removed the child nodes of the system controller in example/dts & will create them in the driver.
   @Rob, I assume keeping them documented is the correct thing to do?
- removed the dependancy on the clock binding from the examples
- reformatted rtc interrupts as per Rob's suggestion

Changes from v4:
- dont include icicle_kit_defconfig, accidentally added in v3
- drop prescaler from mpfs-rtc & calculate the value instead
- use corei2c as a fallback device for mpfs-i2c
- drop spi dt-binding (on spi-next)
   commit 2da187304e556ac59cf2dacb323cc78ded988169
- drop usb dt-binding (on usb-next)

Changes from v3:
- drop "mailbox: change mailbox-mpfs compatible string", already upstream:
   commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
- fix copy paste error in microchip,mpfs-mailbox dt-binding
- remove whitespace in syscontroller dt entry

Changes from v2:
- dropped plic int header & corresponding defines in dts{,i}
- use $ref to drmode in mpfs-musb binding
- split changes to dts{,i} again: functional changes to existing elements now are in a new patch
- drop num-cs property in mpfs-spi binding
- dont make the system controller a simple-mfd
- move the separate bindings for rng/generic system services into the system controller binding
- added an instance corei2c as i2c2 in the fabric dtsi
- add version numbering to corepwm and corei2c compat string (-rtl-vN)

Conor Dooley (11):
   dt-bindings: soc/microchip: update syscontroller compatibles
   dt-bindings: soc/microchip: add info about services to mpfs sysctrl
   dt-bindings: rtc: add bindings for microchip mpfs rtc
   dt-bindings: gpio: add bindings for microchip mpfs gpio
   dt-bindings: pwm: add microchip corepwm binding
   riscv: dts: microchip: use clk defines for icicle kit
   riscv: dts: microchip: add fpga fabric section to icicle kit
   riscv: dts: microchip: refactor icicle kit device tree
   riscv: dts: microchip: update peripherals in icicle kit device tree
   riscv: dts: microchip: add new peripherals to icicle kit device tree
   MAINTAINERS: update riscv/microchip entry

  .../bindings/gpio/microchip,mpfs-gpio.yaml    |  79 ++++++ ...ilbox.yaml => microchip,mpfs-mailbox.yaml} |   6 +- .../bindings/pwm/microchip,corepwm.yaml       |  81 ++++++ .../bindings/rtc/microchip,mfps-rtc.yaml      |  58 ++++ .../microchip,mpfs-sys-controller.yaml        |  40 +++ ...icrochip,polarfire-soc-sys-controller.yaml |  35 --- MAINTAINERS                                   |   2 + .../dts/microchip/microchip-mpfs-fabric.dtsi  |  25 ++ .../microchip/microchip-mpfs-icicle-kit.dts   | 115 ++++++-- .../boot/dts/microchip/microchip-mpfs.dtsi    | 254 ++++++++++++++----

  10 files changed, 591 insertions(+), 104 deletions(-)

  create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
  rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
  create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
  create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi

Quoted 38 lines · Palmer Dabbelt

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Quoted 13 lines · On Wed, 23 Feb 2022 12:48:16 PST (-0800), [email protected] wrote:

Quoted 12 lines · On 14/02/2022 13:58, [email protected] wrote:

From: Conor Dooley <[email protected]>

This series updates the Microchip Icicle Kit device tree by adding a host of peripherals, and some updates to the memory map. In addition, the device tree has been split into a third part, which contains "soft" peripherals that are in the fpga fabric.

Several of the entries are for peripherals that have not get had their drivers upstreamed, so in those cases the dt bindings are included where appropriate in order to avoid the many "DT compatible string <x> appears un-documented" errors.

Quoted 4 lines

Quoted 4 lines

Depends on mpfs clock driver binding (on clk/next) to provide dt-bindings/clock/microchip,mpfs-clock.h for the device tree and on the other changes to the icicle/mpfs device tree from geert that are already in linux/riscv/for-next.

So that's causing this to not build, as I can't build without the header. I went ahead and put these on top of that patch, resulting in

* 48e8641c2bf0 - (HEAD -> riscv-microchip, palmer/riscv-microchip) MAINTAINERS: update riscv/microchip entry (2 minutes ago) <Conor Dooley>
* 528a5b1f2556 - riscv: dts: microchip: add new peripherals to icicle kit device tree (2 minutes ago) <Conor Dooley>
* 5b28df37d311 - riscv: dts: microchip: update peripherals in icicle kit device tree (2 minutes ago) <Conor Dooley>
* c5094f371008 - riscv: dts: microchip: refactor icicle kit device tree (2 minutes ago) <Conor Dooley>
* 72560c6559b8 - riscv: dts: microchip: add fpga fabric section to icicle kit (2 minutes ago) <Conor Dooley>
* 6546f920868e - riscv: dts: microchip: use clk defines for icicle kit (2 minutes ago) <Conor Dooley>
* df77f7735786 - dt-bindings: pwm: add microchip corepwm binding (2 minutes ago) <Conor Dooley>
* 735806d8a68e - dt-bindings: gpio: add bindings for microchip mpfs gpio (2 minutes ago) <Conor Dooley>
* 4cbcc0d7b397 - dt-bindings: rtc: add bindings for microchip mpfs rtc (2 minutes ago) <Conor Dooley>
* b435a1728c9f - dt-bindings: soc/microchip: add info about services to mpfs sysctrl (2 minutes ago) <Conor Dooley>
* 213556235526 - dt-bindings: soc/microchip: update syscontroller compatibles (2 minutes ago) <Conor Dooley>
* 2145bb687e3f - (clk/clk-microchip) dt-bindings: clk: microchip: Add Microchip PolarFire host binding (6 weeks ago) <Daire McNamara>
* e783362eb54c - (tag: v5.17-rc1) Linux 5.17-rc1 (7 weeks ago) <Linus Torvalds>

Quoted 6 lines

sboyd: IIRC it's OK to consider clk-microchip as a stable branch? If not I can just wait until you send your PR to Linus and send this later in the merge window, no big deal on my end.

I've put this on for-next. If that's a problem let me know and I'll delay it.

Great, thanks! Probably worth mentioning that I've deleted the dma node that Zong Li is modifying in his pdma patchset.

Quoted 17 lines

Thanks!

Quoted 7 lines

Quoted 6 lines

Additionally, the interrupt-extended warnings on the plic/clint are cleared by [1] & [2].

[1] https://lore.kernel.org/linux-riscv/[email protected]/
[2] https://lore.kernel.org/linux-riscv/[email protected]/

Quoted 6 lines

Hey Palmer,

dt-bindings should be set now, so if you're still happy to take the series via riscv, that'd be great. i2c, spi & usb patches ended going via the sub-system trees (and have been dropped from the series), in case those generate warnings for you.

Quoted 5 lines

Something went off the rails in email land and #0 and #2 didn't end up in my patch queue but the rest did. Luckily enough made it through that it didn't get lost, and lore's pretty great so this sort of thing isn't that big of a deal these days. That said, email is a bit of a black box so figured I'd give you a heads up.

Huh, interesting. I do check after sending that I can see the mails in my other email's inbox & they're there. Guess good thing that I sent the follow up. Thanks,
Conor.

Quoted 83 lines

Quoted 83 lines

Thanks,
Conor.

Quoted 79 lines

Changes from v6:
- Dropped i2c patch, as its in i2c-next
- Added ack on gpio, reviewed-by on rtc
- Dropped child nodes from sysctrl binding entirely, added a link to the online documenation for the services the system controller can provide
- Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's series

Changes from v5:
- reworded the descriptions in the pwm binding to (hopefully) add clarity
- added -mask to the custom properties and made them 32 bit
- renamed the i2c binding to corei2c, since it is not mpfs specific
- removed the child nodes of the system controller in example/dts & will create them in the driver.
@Rob, I assume keeping them documented is the correct thing to do?
- removed the dependancy on the clock binding from the examples
- reformatted rtc interrupts as per Rob's suggestion

Changes from v4:
- dont include icicle_kit_defconfig, accidentally added in v3
- drop prescaler from mpfs-rtc & calculate the value instead
- use corei2c as a fallback device for mpfs-i2c
- drop spi dt-binding (on spi-next)
commit 2da187304e556ac59cf2dacb323cc78ded988169
- drop usb dt-binding (on usb-next)

Changes from v3:
- drop "mailbox: change mailbox-mpfs compatible string", already upstream:
commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
- fix copy paste error in microchip,mpfs-mailbox dt-binding
- remove whitespace in syscontroller dt entry

Changes from v2:
- dropped plic int header & corresponding defines in dts{,i}
- use $ref to drmode in mpfs-musb binding
- split changes to dts{,i} again: functional changes to existing elements now are in a new patch
- drop num-cs property in mpfs-spi binding
- dont make the system controller a simple-mfd
- move the separate bindings for rng/generic system services into the system controller binding
- added an instance corei2c as i2c2 in the fabric dtsi
- add version numbering to corepwm and corei2c compat string (-rtl-vN)

Conor Dooley (11):
dt-bindings: soc/microchip: update syscontroller compatibles
dt-bindings: soc/microchip: add info about services to mpfs sysctrl
dt-bindings: rtc: add bindings for microchip mpfs rtc
dt-bindings: gpio: add bindings for microchip mpfs gpio
dt-bindings: pwm: add microchip corepwm binding
riscv: dts: microchip: use clk defines for icicle kit
riscv: dts: microchip: add fpga fabric section to icicle kit
riscv: dts: microchip: refactor icicle kit device tree
riscv: dts: microchip: update peripherals in icicle kit device tree
riscv: dts: microchip: add new peripherals to icicle kit device tree
MAINTAINERS: update riscv/microchip entry

  .../bindings/gpio/microchip,mpfs-gpio.yaml    |  79 ++++++
  ...ilbox.yaml => microchip,mpfs-mailbox.yaml} |   6 +-
  .../bindings/pwm/microchip,corepwm.yaml       |  81 ++++++
  .../bindings/rtc/microchip,mfps-rtc.yaml      |  58 ++++
  .../microchip,mpfs-sys-controller.yaml        |  40 +++
  ...icrochip,polarfire-soc-sys-controller.yaml |  35 ---
  MAINTAINERS                                   |   2 +
  .../dts/microchip/microchip-mpfs-fabric.dtsi  |  25 ++
  .../microchip/microchip-mpfs-icicle-kit.dts   | 115 ++++++--
  .../boot/dts/microchip/microchip-mpfs.dtsi    | 254 ++++++++++++++----
  10 files changed, 591 insertions(+), 104 deletions(-)

create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi

Quoted 44 lines · On Thu, Mar 10, 2022 at 3:35 PM <[email protected]> wrote:

Quoted 42 lines · Palmer Dabbelt

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Quoted 13 lines · On Wed, 23 Feb 2022 12:48:16 PST (-0800), [email protected] wrote:

Quoted 12 lines · On 14/02/2022 13:58, [email protected] wrote:

From: Conor Dooley <[email protected]>

This series updates the Microchip Icicle Kit device tree by adding a host of peripherals, and some updates to the memory map. In addition, the device tree has been split into a third part, which contains "soft" peripherals that are in the fpga fabric.

Several of the entries are for peripherals that have not get had their drivers upstreamed, so in those cases the dt bindings are included where appropriate in order to avoid the many "DT compatible string <x> appears un-documented" errors.

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Depends on mpfs clock driver binding (on clk/next) to provide dt-bindings/clock/microchip,mpfs-clock.h for the device tree and on the other changes to the icicle/mpfs device tree from geert that are already in linux/riscv/for-next.

So that's causing this to not build, as I can't build without the header. I went ahead and put these on top of that patch, resulting in

* 48e8641c2bf0 - (HEAD -> riscv-microchip, palmer/riscv-microchip) MAINTAINERS: update riscv/microchip entry (2 minutes ago) <Conor Dooley>
* 528a5b1f2556 - riscv: dts: microchip: add new peripherals to icicle kit device tree (2 minutes ago) <Conor Dooley>
* 5b28df37d311 - riscv: dts: microchip: update peripherals in icicle kit device tree (2 minutes ago) <Conor Dooley>
* c5094f371008 - riscv: dts: microchip: refactor icicle kit device tree (2 minutes ago) <Conor Dooley>
* 72560c6559b8 - riscv: dts: microchip: add fpga fabric section to icicle kit (2 minutes ago) <Conor Dooley>
* 6546f920868e - riscv: dts: microchip: use clk defines for icicle kit (2 minutes ago) <Conor Dooley>
* df77f7735786 - dt-bindings: pwm: add microchip corepwm binding (2 minutes ago) <Conor Dooley>
* 735806d8a68e - dt-bindings: gpio: add bindings for microchip mpfs gpio (2 minutes ago) <Conor Dooley>
* 4cbcc0d7b397 - dt-bindings: rtc: add bindings for microchip mpfs rtc (2 minutes ago) <Conor Dooley>
* b435a1728c9f - dt-bindings: soc/microchip: add info about services to mpfs sysctrl (2 minutes ago) <Conor Dooley>
* 213556235526 - dt-bindings: soc/microchip: update syscontroller compatibles (2 minutes ago) <Conor Dooley>
* 2145bb687e3f - (clk/clk-microchip) dt-bindings: clk: microchip: Add Microchip PolarFire host binding (6 weeks ago) <Daire McNamara>
* e783362eb54c - (tag: v5.17-rc1) Linux 5.17-rc1 (7 weeks ago) <Linus Torvalds>

sboyd: IIRC it's OK to consider clk-microchip as a stable branch? If not I can just wait until you send your PR to Linus and send this later in the merge window, no big deal on my end.

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I've put this on for-next. If that's a problem let me know and I'll delay it.

Great, thanks! Probably worth mentioning that I've deleted the dma node that Zong Li is modifying in his pdma patchset.

I guess I could re-sent the next version based on top of for-next, or delay my patch set until the next tag. What is your perspective?

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Thanks!

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Additionally, the interrupt-extended warnings on the plic/clint are cleared by [1] & [2].

[1] https://lore.kernel.org/linux-riscv/[email protected]/
[2] https://lore.kernel.org/linux-riscv/[email protected]/

Quoted 6 lines

Hey Palmer,

dt-bindings should be set now, so if you're still happy to take the series via riscv, that'd be great. i2c, spi & usb patches ended going via the sub-system trees (and have been dropped from the series), in case those generate warnings for you.

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Something went off the rails in email land and #0 and #2 didn't end up in my patch queue but the rest did. Luckily enough made it through that it didn't get lost, and lore's pretty great so this sort of thing isn't that big of a deal these days. That said, email is a bit of a black box so figured I'd give you a heads up.

Quoted 89 lines

Huh, interesting. I do check after sending that I can see the mails in my other email's inbox & they're there. Guess good thing that I sent the follow up. Thanks,
Conor.

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Thanks,
Conor.

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Changes from v6:
- Dropped i2c patch, as its in i2c-next
- Added ack on gpio, reviewed-by on rtc
- Dropped child nodes from sysctrl binding entirely, added a link to the online documenation for the services the system controller can provide
- Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's series

Changes from v5:
- reworded the descriptions in the pwm binding to (hopefully) add clarity
- added -mask to the custom properties and made them 32 bit
- renamed the i2c binding to corei2c, since it is not mpfs specific
- removed the child nodes of the system controller in example/dts & will create them in the driver.
@Rob, I assume keeping them documented is the correct thing to do?
- removed the dependancy on the clock binding from the examples
- reformatted rtc interrupts as per Rob's suggestion

Changes from v4:
- dont include icicle_kit_defconfig, accidentally added in v3
- drop prescaler from mpfs-rtc & calculate the value instead
- use corei2c as a fallback device for mpfs-i2c
- drop spi dt-binding (on spi-next)

    commit 2da187304e556ac59cf2dacb323cc78ded988169

- drop usb dt-binding (on usb-next)

Changes from v3:
- drop "mailbox: change mailbox-mpfs compatible string", already upstream:
commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
- fix copy paste error in microchip,mpfs-mailbox dt-binding
- remove whitespace in syscontroller dt entry

Changes from v2:
- dropped plic int header & corresponding defines in dts{,i}
- use $ref to drmode in mpfs-musb binding
- split changes to dts{,i} again: functional changes to existing elements now are in a new patch
- drop num-cs property in mpfs-spi binding
- dont make the system controller a simple-mfd
- move the separate bindings for rng/generic system services into the system controller binding
- added an instance corei2c as i2c2 in the fabric dtsi
- add version numbering to corepwm and corei2c compat string (-rtl-vN)

Conor Dooley (11):
dt-bindings: soc/microchip: update syscontroller compatibles
dt-bindings: soc/microchip: add info about services to mpfs sysctrl
dt-bindings: rtc: add bindings for microchip mpfs rtc
dt-bindings: gpio: add bindings for microchip mpfs gpio
dt-bindings: pwm: add microchip corepwm binding
riscv: dts: microchip: use clk defines for icicle kit
riscv: dts: microchip: add fpga fabric section to icicle kit
riscv: dts: microchip: refactor icicle kit device tree
riscv: dts: microchip: update peripherals in icicle kit device tree
riscv: dts: microchip: add new peripherals to icicle kit device tree
MAINTAINERS: update riscv/microchip entry

   .../bindings/gpio/microchip,mpfs-gpio.yaml    |  79 ++++++
   ...ilbox.yaml => microchip,mpfs-mailbox.yaml} |   6 +-
   .../bindings/pwm/microchip,corepwm.yaml       |  81 ++++++
   .../bindings/rtc/microchip,mfps-rtc.yaml      |  58 ++++
   .../microchip,mpfs-sys-controller.yaml        |  40 +++
   ...icrochip,polarfire-soc-sys-controller.yaml |  35 ---
   MAINTAINERS                                   |   2 +
   .../dts/microchip/microchip-mpfs-fabric.dtsi  |  25 ++
   .../microchip/microchip-mpfs-icicle-kit.dts   | 115 ++++++--
   .../boot/dts/microchip/microchip-mpfs.dtsi    | 254 ++++++++++++++----
   10 files changed, 591 insertions(+), 104 deletions(-)

create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi

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Quoted 4 lines · On Wed, 23 Feb 2022 12:48:16 PST (-0800), [email protected] wrote:

dt-bindings should be set now, so if you're still happy to take the series via riscv, that'd be great. i2c, spi & usb patches ended going via the sub-system trees (and have been dropped from the series), in case those generate warnings for you.

Something went off the rails in email land and #0 and #2 didn't end up in my patch queue but the rest did. Luckily enough made it through that it didn't get lost, and lore's pretty great so this sort of thing isn't that big of a deal these days. That said, email is a bit of a black box so figured I'd give you a heads up.