clk: qcom: clk-alpha-pll: add support for APSS PLL
Subsystems (6)
PATCH v3 1/6 clk: qcom: clk-alpha-pll: add support for APSS PLL
APSS PLL type will be used by the IPQ8074 APSS driver for providing the CPU core clocks and enabling CPU Frequency scaling.
This is ported from the downstream 5.4 kernel.
--- drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 13 insertions(+)
drivers/clk/qcom/clk-alpha-pll.c +12 -0
@@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_APSS] = { + [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL_U] = 0xff, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0xff, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + [PLL_OFF_STATUS] = 0x28, + }, };EXPORT_SYMBOL_GPL (clk_alpha_pll_regs);
drivers/clk/qcom/clk-alpha-pll.h +1 -0
@@ -18,6 +18,7 @@ enum {CLK_ALPHA_PLL_TYPE_AGERA ,CLK_ALPHA_PLL_TYPE_ZONDA ,CLK_ALPHA_PLL_TYPE_LUCID_EVO , +CLK_ALPHA_PLL_TYPE_APSS , CLK_ALPHA_PLL_TYPE_MAX, };
Signature · 1 line
2.35.1
PATCH v3 2/6 dt-bindings: clock: Add support for IPQ8074 APSS clock controller
Add dt-binding for the IPQ8074 APSS clock controller which provides clocks to the CPU cores.
---
Changes in v2:
* Correct subject
--- include/dt-bindings/clock/qcom,apss-ipq8074.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq8074.h
include/dt-bindings/clock/qcom,apss-ipq8074.h new file +14 -0
@@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2021, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H + +#define APSS_PLL_EARLY 0 +#define APSS_PLL 1 +#define APCS_ALIAS0_CLK_SRC 2 +#define APCS_ALIAS0_CORE_CLK 3 + +#endif
Signature · 1 line
2.35.1
Re: [PATCH v3 2/6] dt-bindings: clock: Add support for IPQ8074 APSS clock controller
Quoted 7 lines · Robert Marko
Add dt-binding for the IPQ8074 APSS clock controller which provides clocks to the CPU cores.
Signed-off-by Robert Marko <[email protected]>---
Changes in v2:
* Correct subject
After explanations about license:
Best regards,
Krzysztof
PATCH v3 3/6 clk: qcom: Add IPQ8074 APSS clock controller
In reply to Robert MarkoIPQ8074 APSS clock controller provides the clock for the IPQ8074 CPU cores, thus also providing support for CPU frequency scaling.
It looks like they are clocked by the XO and a custom APSS type PLL.
---
Changes in v2:
* Convert to using parent-data instead of parent-names
--- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq8074.c | 170 ++++++++++++++++++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq8074.c
drivers/clk/qcom/Kconfig +11 -0
@@ -134,6 +134,17 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. +config IPQ_APSS_8074 + tristate "IPQ8074 APSS Clock Controller" + select IPQ_GCC_8074 + depends on QCOM_APCS_IPC || COMPILE_TEST + help + Support for APSS clock controller on IPQ8074 platforms. The + APSS clock controller manages the Mux and enable block that feeds the + CPUs. + Say Y if you want to support CPU frequency scaling on + IPQ8074 based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help
drivers/clk/qcom/Makefile +1 -0
@@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o +obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
drivers/clk/qcom/apss-ipq8074.c new file +170 -0
170 lines not on this page · raw message
Signature · 1 line
2.35.1
PATCH v3 4/6 mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock controller support
In reply to Robert MarkoIPQ8074 has the APSS clock controller utilizing the same register space as the APCS, so provide access to the APSS utilizing a child device like IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS clock driver.
Also, APCS register space in IPQ8074 is 0x6000 so max_register needs to be updated to 0x5FFC.
--- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
drivers/mailbox/qcom-apcs-ipc-mailbox.c +6 -2
@@ -33,6 +33,10 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = { .offset = 8, .clk_name = "qcom,apss-ipq6018-clk" }; +static const struct qcom_apcs_ipc_data ipq8074_apcs_data = { + .offset =8 , .clk_name ="qcom,apss-ipq8074-clk" +}; +static const struct qcom_apcs_ipc_data msm8916_apcs_data = { .offset =8 , .clk_name ="qcom-apcs-msm8916-clk" };
@@ -57,7 +61,7 @@ static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, - .max_register = 0x1008, + .max_register = 0x5FFC, .fast_io = true, };
@@ -142,7 +146,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)/* .data is the offset of the ipc register within the global block */ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible ="qcom,ipq6018-apcs-apps-global" , .data = &ipq6018_apcs_data }, - { .compatible ="qcom,ipq8074-apcs-apps-global" , .data = &msm8994_apcs_data }, + { .compatible ="qcom,ipq8074-apcs-apps-global" , .data = &ipq8074_apcs_data }, { .compatible ="qcom,msm8916-apcs-kpss-global" , .data = &msm8916_apcs_data }, { .compatible ="qcom,msm8939-apcs-kpss-global" , .data = &msm8916_apcs_data }, { .compatible ="qcom,msm8953-apcs-kpss-global" , .data = &msm8994_apcs_data },
Signature · 1 line
2.35.1
PATCH v3 5/6 dt-bindings: mailbox: qcom: set correct #clock-cells
In reply to Robert MarkoIPQ6018 and IPQ8074 require #clock-cells to be set to 1 as their APSS clock driver provides multiple clock outputs.
So allow setting 1 as #clock-cells and check that its set to 1 for IPQ6018 and IPQ8074, check others for 0 as its currently.
---
Changes in v3:
* Drop not needed blank line
Changes in v2:
* Correct subject name
--- .../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +16 -1
@@ -50,7 +50,7 @@ properties: const: 1 '#clock-cells': - const: 0 + enum: [0, 1] clock-names: minItems: 2
@@ -96,6 +96,21 @@ allOf: properties: clocks: maxItems: 3 + - if: + properties: + compatible: + enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global + then: + properties: + '#clock-cells': + const: 1 + else: + properties: + '#clock-cells': + const: 0 + examples: # Example apcs with msm8996
Signature · 1 line
2.35.1
PATCH v3 6/6 arm64: dts: ipq8074: add APCS node
In reply to Robert MarkoAPCS now has support for providing the APSS clocks as the child device for IPQ8074.
So, add the required DT node for it as it will later be used as the CPU clocksource.
---
Changes in v3:
* Node does not currently exist in the upstream kernel, so add it instead of modifying.
--- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/arm64/boot/dts/qcom/ipq8074.dtsi +8 -0
@@ -886,5 +886,13 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "axi_m_sticky"; status = "disabled"; }; + + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq8074-apcs-apps-global"; + reg = <0x0b111000 0x6000>; + + #clock-cells = <1>; + #mbox-cells = <1>; + }; }; };
Signature · 1 line
2.35.1