clk: qcom: clk-alpha-pll: add support for APSS PLL
PATCH v5 1/3 clk: qcom: clk-alpha-pll: add support for APSS PLL
APSS PLL type will be used by the IPQ8074 APSS driver for providing the CPU core clocks and enabling CPU Frequency scaling.
This is ported from the downstream 5.4 kernel.
--- drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 13 insertions(+)
drivers/clk/qcom/clk-alpha-pll.c +12 -0
@@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_APSS] = { + [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL_U] = 0xff, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0xff, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + [PLL_OFF_STATUS] = 0x28, + }, };EXPORT_SYMBOL_GPL (clk_alpha_pll_regs);
drivers/clk/qcom/clk-alpha-pll.h +1 -0
@@ -18,6 +18,7 @@ enum {CLK_ALPHA_PLL_TYPE_AGERA ,CLK_ALPHA_PLL_TYPE_ZONDA ,CLK_ALPHA_PLL_TYPE_LUCID_EVO , +CLK_ALPHA_PLL_TYPE_APSS , CLK_ALPHA_PLL_TYPE_MAX, };
Signature · 1 line
2.36.1
PATCH v5 2/3 dt-bindings: clock: Add support for IPQ8074 APSS clock controller
Add dt-binding for the IPQ8074 APSS clock controller which provides clocks to the CPU cores.
---
Changes in v4:
* Dual license the bindings
* Update the copyright year
Changes in v2:
* Correct subject
--- include/dt-bindings/clock/qcom,apss-ipq8074.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq8074.h
include/dt-bindings/clock/qcom,apss-ipq8074.h new file +14 -0
@@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* +* Copyright (c) 2022, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H + +#define APSS_PLL_EARLY 0 +#define APSS_PLL 1 +#define APCS_ALIAS0_CLK_SRC 2 +#define APCS_ALIAS0_CORE_CLK 3 + +#endif
Signature · 1 line
2.36.1
PATCH v5 3/3 clk: qcom: Add IPQ8074 APSS clock controller
In reply to Robert MarkoIPQ8074 APSS clock controller provides the clock for the IPQ8074 CPU cores, thus also providing support for CPU frequency scaling.
It looks like they are clocked by the XO and a custom APSS type PLL.
---
Changes in v5:
* Drop F define as its already defined in clk-rgc.h
* Correct the driver name to not include commas
* Correct Christian-s SoB
* Add MODULE_ALIAS so it gets loaded if built as a module
Changes in v2:
* Convert to using parent-data instead of parent-names
--- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq8074.c | 169 ++++++++++++++++++++++++++++++++ 3 files changed, 181 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq8074.c
drivers/clk/qcom/Kconfig +11 -0
@@ -134,6 +134,17 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. +config IPQ_APSS_8074 + tristate "IPQ8074 APSS Clock Controller" + select IPQ_GCC_8074 + depends on QCOM_APCS_IPC || COMPILE_TEST + help + Support for APSS clock controller on IPQ8074 platforms. The + APSS clock controller manages the Mux and enable block that feeds the + CPUs. + Say Y if you want to support CPU frequency scaling on + IPQ8074 based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help
drivers/clk/qcom/Makefile +1 -0
@@ -23,6 +23,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o +obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
drivers/clk/qcom/apss-ipq8074.c new file +169 -0
169 lines not on this page · raw message
Signature · 1 line
2.36.1
Re: [PATCH v5 3/3] clk: qcom: Add IPQ8074 APSS clock controller
Quoted 96 lines · Robert Marko
IPQ8074 APSS clock controller provides the clock for the IPQ8074 CPU cores, thus also providing support for CPU frequency scaling.
It looks like they are clocked by the XO and a custom APSS type PLL.
Co-developed-by Christian Marangi <[email protected]>Signed-off-by Christian Marangi <[email protected]>Signed-off-by Robert Marko <[email protected]>---
Changes in v5:
* Drop F define as its already defined inclk-rgc.h
* Correct the driver name to not include commas
* Correct Christian-s SoB
* AddMODULE_ALIASso it gets loaded if built as a moduleChanges in v2:
* Convert to using parent-data instead of parent-names--- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq8074.c | 169 ++++++++++++++++++++++++++++++++ 3 files changed, 181 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq8074.cdrivers/clk/qcom/Kconfig +11
-0@@ -134,6 +134,17 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. +config IPQ_APSS_8074 + tristate "IPQ8074 APSS Clock Controller" + select IPQ_GCC_8074 + depends on QCOM_APCS_IPC || COMPILE_TEST + help + Support for APSS clock controller on IPQ8074 platforms. The + APSS clock controller manages the Mux and enable block that feeds the + CPUs. + Say Y if you want to support CPU frequency scaling on + IPQ8074 based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" helpdrivers/clk/qcom/Makefile +1
-0@@ -23,6 +23,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o +obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.odrivers/clk/qcom/apss-ipq8074.c new file +32
-0@@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (c) 2022, The Linux Foundation. All rights reserved. +*/ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,apss-ipq8074.h> + +#include "common.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "clk-alpha-pll.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" + +enum { +P_XO , +P_GPLL0 , +P_GPLL2 , +P_GPLL4 , +P_APSS_PLL_EARLY , +P_APSS_PLL +}; +
drivers/clk/qcom/apss-ipq8074.c line 42
Quoted 10 lines
drivers/clk/qcom/apss-ipq8074.c new file +10
-0+static struct clk_alpha_pll apss_pll_early = { + .offset =0x5000 , + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS ], + .clkr = { + .enable_reg =0x5000 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="apss_pll_early" , + .parent_data = &(const struct clk_parent_data ) { + .fw_name ="xo" , .name ="xo"
Since you're only adding this driver now, no DT uses it an you should drop the .name lookup.
Quoted 26 lines
drivers/clk/qcom/apss-ipq8074.c new file +26
-0+ }, + .num_parents = 1, + .ops = &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv apss_pll = { + .offset =0x5000 , + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS ], + .width =2 , + .clkr.hw.init = &(struct clk_init_data ){ + .name ="apss_pll" , + .parent_hws = (const struct clk_hw *[]){ + &apss_pll_early.clkr.hw }, + .num_parents =1 , + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { + { .fw_name ="xo" , .name ="xo" }, + { .fw_name ="gpll0" , .name ="gpll0" }, + { .fw_name ="gpll2" , .name ="gpll2" }, + { .fw_name ="gpll4" , .name ="gpll4" }, + { .hw = &apss_pll.clkr.hw },
drivers/clk/qcom/apss-ipq8074.c line 78
Quoted 10 lines
drivers/clk/qcom/apss-ipq8074.c new file +10
-0+ { .hw = &apss_pll_early.clkr.hw }, +}; + +static const struct parent_map parents_apcs_alias0_clk_src_map[] = { + {P_XO ,0 }, + {P_GPLL0 ,4 }, + {P_GPLL2 ,2 }, + {P_GPLL4 ,1 }, + {P_APSS_PLL ,3 }, + {P_APSS_PLL_EARLY ,5 },
Looks like it only supports frequencies with APSS_PLL_EARLY and XO as parents? Are all of these other PLLs necessary here?
drivers/clk/qcom/apss-ipq8074.c line 90
Quoted 12 lines
drivers/clk/qcom/apss-ipq8074.c new file +12
-0+}; + +struct freq_tbl ftbl_apcs_alias0_clk_src[] = { +F (19200000 ,P_XO ,1 ,0 ,0 ), +F (403200000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (806400000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (1017600000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (1382400000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (1651200000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (1843200000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (1920000000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (2208000000UL ,P_APSS_PLL_EARLY ,1 ,0 ,0 ),
Every frequency is a div1 and comes from a single clock.. is this correct? This sounds like a simple mux that only switches between XO and APSS_PLL_EARLY..
Quoted 20 lines
drivers/clk/qcom/apss-ipq8074.c new file +20
-0+ { } +}; + +struct clk_rcg2 apcs_alias0_clk_src = { + .cmd_rcgr =0x0050 , + .freq_tbl = ftbl_apcs_alias0_clk_src, + .hid_width =5 , + .parent_map = parents_apcs_alias0_clk_src_map, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="apcs_alias0_clk_src" , + .parent_data = parents_apcs_alias0_clk_src, + .num_parents =ARRAY_SIZE (parents_apcs_alias0_clk_src), + .ops = &clk_rcg2_ops, + .flags =CLK_SET_RATE_PARENT , + }, +}; + +static struct clk_branch apcs_alias0_core_clk = { + .halt_reg =0x0058 , + .halt_bit =31 ,
drivers/clk/qcom/apss-ipq8074.c line 120
Quoted 10 lines
drivers/clk/qcom/apss-ipq8074.c new file +10
-0+ .clkr = { + .enable_reg = 0x0058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_core_clk", + .parent_hws = (const struct clk_hw *[]){ + &apcs_alias0_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL,
This can fit in a single line.
Quoted 25 lines
drivers/clk/qcom/apss-ipq8074.c new file +25
-0+ .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *apss_ipq8074_clks[] = { + [APSS_PLL_EARLY ] = &apss_pll_early.clkr, + [APSS_PLL ] = &apss_pll.clkr, + [APCS_ALIAS0_CLK_SRC ] = &apcs_alias0_clk_src.clkr, + [APCS_ALIAS0_CORE_CLK ] = &apcs_alias0_core_clk.clkr, +}; + +static const struct regmap_config apss_ipq8074_regmap_config = { + .reg_bits =32 , + .reg_stride =4 , + .val_bits =32 , + .max_register =0x5ffc , + .fast_io = true, +}; + +static const struct qcom_cc_desc apss_ipq8074_desc = { + .config = &apss_ipq8074_regmap_config, + .clks = apss_ipq8074_clks, + .num_clks =ARRAY_SIZE (apss_ipq8074_clks), +};
drivers/clk/qcom/apss-ipq8074.c line 155
Quoted 10 lines
drivers/clk/qcom/apss-ipq8074.c new file +10
-0+ +static int apss_ipq8074_probe (struct platform_device *pdev) +{ +struct regmap *regmap; + + regmap =dev_get_regmap (pdev->dev.parent,NULL ); +if (!regmap) +return -ENODEV ; + +return qcom_cc_really_probe (pdev, &apss_ipq8074_desc, regmap);
qcom_cc_probe?
Quoted 4 lines
drivers/clk/qcom/apss-ipq8074.c new file +4
-0+} + +static struct platform_driver apss_ipq8074_driver = { + .probe = apss_ipq8074_probe,
drivers/clk/qcom/apss-ipq8074.c line 169
Quoted 10 lines
drivers/clk/qcom/apss-ipq8074.c new file +10
-0+ .driver = { + .name = "qcom-apss-ipq8074-clk", + }, +}; + +module_platform_driver (apss_ipq8074_driver); + +MODULE_ALIAS ("platform:qcom-apss-ipq8074-clk" ); +MODULE_DESCRIPTION ("Qualcomm IPQ8074 APSS clock driver" ); +MODULE_LICENSE ("GPL" );
"GPL v2"?
Konrad
Re: [PATCH v5 3/3] clk: qcom: Add IPQ8074 APSS clock controller
Quoted 104 lines · Konrad Dybcio
Quoted 100 lines · Robert Marko
IPQ8074 APSS clock controller provides the clock for the IPQ8074 CPU cores, thus also providing support for CPU frequency scaling.
It looks like they are clocked by the XO and a custom APSS type PLL.
Co-developed-by Christian Marangi <[email protected]>Signed-off-by Christian Marangi <[email protected]>Signed-off-by Robert Marko <[email protected]>---
Changes in v5:
* Drop F define as its already defined inclk-rgc.h
* Correct the driver name to not include commas
* Correct Christian-s SoB
* AddMODULE_ALIASso it gets loaded if built as a moduleChanges in v2:
* Convert to using parent-data instead of parent-names--- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq8074.c | 169 ++++++++++++++++++++++++++++++++ 3 files changed, 181 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq8074.cdrivers/clk/qcom/Kconfig +11
-0@@ -134,6 +134,17 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. +config IPQ_APSS_8074 + tristate "IPQ8074 APSS Clock Controller" + select IPQ_GCC_8074 + depends on QCOM_APCS_IPC || COMPILE_TEST + help + Support for APSS clock controller on IPQ8074 platforms. The + APSS clock controller manages the Mux and enable block that feeds the + CPUs. + Say Y if you want to support CPU frequency scaling on + IPQ8074 based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" helpdrivers/clk/qcom/Makefile +1
-0@@ -23,6 +23,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o +obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.odrivers/clk/qcom/apss-ipq8074.c new file +36
-0@@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (c) 2022, The Linux Foundation. All rights reserved. +*/ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,apss-ipq8074.h> + +#include "common.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "clk-alpha-pll.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" + +enum { +P_XO , +P_GPLL0 , +P_GPLL2 , +P_GPLL4 , +P_APSS_PLL_EARLY , +P_APSS_PLL +}; + +static struct clk_alpha_pll apss_pll_early = { + .offset =0x5000 , + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS ], + .clkr = {
Quoted 8 lines
drivers/clk/qcom/apss-ipq8074.c line 42
Quoted 6 lines
drivers/clk/qcom/apss-ipq8074.c new file +6
-0+ .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data ){ + .name ="apss_pll_early" , + .parent_data = &(const struct clk_parent_data ) { + .fw_name ="xo" , .name ="xo" Since you're only adding this driver now, no DT uses it an you should drop the .name lookup.
Hi Konrad,
I will fix it up, also need to update the dtschema and DT node patch for APCS node as "xo" is not a valid clock currently for it.
Quoted 32 lines
Quoted 32 lines
drivers/clk/qcom/apss-ipq8074.c new file +30
-0+ }, + .num_parents = 1, + .ops = &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv apss_pll = { + .offset =0x5000 , + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS ], + .width =2 , + .clkr.hw.init = &(struct clk_init_data ){ + .name ="apss_pll" , + .parent_hws = (const struct clk_hw *[]){ + &apss_pll_early.clkr.hw }, + .num_parents =1 , + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { + { .fw_name ="xo" , .name ="xo" }, + { .fw_name ="gpll0" , .name ="gpll0" }, + { .fw_name ="gpll2" , .name ="gpll2" }, + { .fw_name ="gpll4" , .name ="gpll4" }, + { .hw = &apss_pll.clkr.hw }, + { .hw = &apss_pll_early.clkr.hw }, +}; + +static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
Quoted 8 lines
drivers/clk/qcom/apss-ipq8074.c line 78
Quoted 6 lines
drivers/clk/qcom/apss-ipq8074.c new file +6
-0+ { P_XO, 0 }, + { P_GPLL0, 4 }, + { P_GPLL2, 2 }, + { P_GPLL4, 1 }, + { P_APSS_PLL, 3 }, + { P_APSS_PLL_EARLY, 5 },Looks like it only supports frequencies with
APSS_PLL_EARLYand XO as parents? Are all of these other PLLs necessary here?
Unfortunately, I dont have any docs on this, this is based on the downstream 5.4 driver.
I got rid of GPLL-s as parents and it seems to still be able to set the correct frequency
, however, initially the frequency that is read during boot then matches the XO frequency
of 19.2 MHz which is obviously incorrect:
[ 1.632308] cpufreq: cpufreq_online: CPU0: Running at unlisted
initial frequency: 19200 KHz, changing to: 1017600 KHz
I can then use the userspace governor and go through all OPP points without an issue and
using the mhz [1] tool I can confirm that frequency matches the requested one.
[1] https://github.com/wtarreau/mhz
Quoted 16 lines
drivers/clk/qcom/apss-ipq8074.c line 90
Quoted 13 lines
drivers/clk/qcom/apss-ipq8074.c new file +12
-0+}; + +struct freq_tbl ftbl_apcs_alias0_clk_src[] = { +F (19200000 ,P_XO ,1 ,0 ,0 ), +F (403200000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (806400000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (1017600000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (1382400000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (1651200000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (1843200000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (1920000000 ,P_APSS_PLL_EARLY ,1 ,0 ,0 ), +F (2208000000UL ,P_APSS_PLL_EARLY ,1 ,0 ,0 ),Every frequency is a div1 and comes from a single clock.. is this correct? This sounds like a simple mux that only switches between XO and
APSS_PLL_EARLY..
I tested this using the IPQ6018 clk_regmap_mux apcs_alias0_clk_src and it appears to work, I am able to switch through all of the OPP-s:
# cat scaling_available_frequencies 1017600 1382400 1651200 1843200 1920000 2208000 # echo 1017600 > scaling_setspeed # mhz count=413212 us50=20314 us250=101571 diff=81257 cpu_MHz=1017.050 # echo 1382400 > scaling_setspeed # mhz count=645643 us50=23381 us250=116811 diff=93430 cpu_MHz=1382.089 # echo 1651200 > scaling_setspeed # mhz count=807053 us50=24452 us250=122238 diff=97786 cpu_MHz=1650.651 # echo 1843200 > scaling_setspeed # mhz count=807053 us50=21901 us250=109503 diff=87602 cpu_MHz=1842.545 # echo 1920000 > scaling_setspeed # mhz count=807053 us50=21023 us250=105125 diff=84102 cpu_MHz=1919.224 # echo 2208000 > scaling_setspeed # mhz count=1008816 us50=22857 us250=114255 diff=91398 cpu_MHz=2207.523
Seems like IPQ6018 and IPQ8074 use the same mux, though PLL is different.
Quoted 24 lines
Quoted 24 lines
drivers/clk/qcom/apss-ipq8074.c new file +23
-0+ { } +}; + +struct clk_rcg2 apcs_alias0_clk_src = { + .cmd_rcgr =0x0050 , + .freq_tbl = ftbl_apcs_alias0_clk_src, + .hid_width =5 , + .parent_map = parents_apcs_alias0_clk_src_map, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="apcs_alias0_clk_src" , + .parent_data = parents_apcs_alias0_clk_src, + .num_parents =ARRAY_SIZE (parents_apcs_alias0_clk_src), + .ops = &clk_rcg2_ops, + .flags =CLK_SET_RATE_PARENT , + }, +}; + +static struct clk_branch apcs_alias0_core_clk = { + .halt_reg =0x0058 , + .halt_bit =31 , + .clkr = { + .enable_reg =0x0058 , + .enable_mask =BIT (0 ),
Quoted 8 lines
drivers/clk/qcom/apss-ipq8074.c line 120
Quoted 7 lines
drivers/clk/qcom/apss-ipq8074.c new file +7
-0+ .hw.init = &(struct clk_init_data){ + .name ="apcs_alias0_core_clk" , + .parent_hws = (const struct clk_hw *[]){ + &apcs_alias0_clk_src.clkr.hw }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT | +CLK_IS_CRITICAL ,This can fit in a single line.
I will fix it in v6.
Quoted 29 lines
Quoted 29 lines
drivers/clk/qcom/apss-ipq8074.c new file +28
-0+ .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *apss_ipq8074_clks[] = { + [APSS_PLL_EARLY ] = &apss_pll_early.clkr, + [APSS_PLL ] = &apss_pll.clkr, + [APCS_ALIAS0_CLK_SRC ] = &apcs_alias0_clk_src.clkr, + [APCS_ALIAS0_CORE_CLK ] = &apcs_alias0_core_clk.clkr, +}; + +static const struct regmap_config apss_ipq8074_regmap_config = { + .reg_bits =32 , + .reg_stride =4 , + .val_bits =32 , + .max_register =0x5ffc , + .fast_io = true, +}; + +static const struct qcom_cc_desc apss_ipq8074_desc = { + .config = &apss_ipq8074_regmap_config, + .clks = apss_ipq8074_clks, + .num_clks =ARRAY_SIZE (apss_ipq8074_clks), +}; + +static int apss_ipq8074_probe (struct platform_device *pdev) +{
Quoted 8 lines
drivers/clk/qcom/apss-ipq8074.c line 155
Quoted 7 lines
drivers/clk/qcom/apss-ipq8074.c new file +7
-0+struct regmap *regmap; + + regmap =dev_get_regmap (pdev->dev.parent,NULL ); +if (!regmap) +return -ENODEV ; + +return qcom_cc_really_probe (pdev, &apss_ipq8074_desc, regmap);
qcom_cc_probe?
qcom_cc_probe would not work as it calls qcom_cc_map which works only on the device MMIO resource, and we have to get the regmap from the parent which is APCS as they share the same register space.
Quoted 16 lines
Quoted 5 lines
drivers/clk/qcom/apss-ipq8074.c new file +4
-0+} + +static struct platform_driver apss_ipq8074_driver = { + .probe = apss_ipq8074_probe,drivers/clk/qcom/apss-ipq8074.c line 169
Quoted 10 lines
drivers/clk/qcom/apss-ipq8074.c new file +10
-0+ .driver = { + .name = "qcom-apss-ipq8074-clk", + }, +}; + +module_platform_driver (apss_ipq8074_driver); + +MODULE_ALIAS ("platform:qcom-apss-ipq8074-clk" ); +MODULE_DESCRIPTION ("Qualcomm IPQ8074 APSS clock driver" ); +MODULE_LICENSE ("GPL" );"GPL v2"?
Checkpatch now warns on GPL v2 and other variants that GPL is preferred since 5.18:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/scripts/checkpatch.pl?h=v5.18.10&id=6e8f42dc9c8548c6b37566f3b8bda1873700c4a6
Originally had "GPL v2" and then checkpatch pointed this out.
Regards,
Robert
Quoted 2 lines
Konrad
Quoted 16 lines · Robert Marko
APSS PLL type will be used by the IPQ8074 APSS driver for providing the CPU core clocks and enabling CPU Frequency scaling.
This is ported from the downstream 5.4 kernel.
Signed-off-by Robert Marko <[email protected]>--- drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 13 insertions(+)drivers/clk/qcom/clk-alpha-pll.c +0
-0
drivers/clk/qcom/clk-alpha-pll.c const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { · line 157
Quoted 4 lines
drivers/clk/qcom/clk-alpha-pll.c +1
-0@@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1 ] =0x34 , }, + [CLK_ALPHA_PLL_TYPE_APSS] = {
The name is surely not correct, can somebody from qcom chime in and suggest what it should be?
Konrad
Quoted 26 lines
drivers/clk/qcom/clk-alpha-pll.c +11
-0+ [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL_U] = 0xff, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0xff, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + [PLL_OFF_STATUS] = 0x28, + }, };EXPORT_SYMBOL_GPL (clk_alpha_pll_regs);drivers/clk/qcom/clk-alpha-pll.h +1
-0@@ -18,6 +18,7 @@ enum {CLK_ALPHA_PLL_TYPE_AGERA ,CLK_ALPHA_PLL_TYPE_ZONDA ,CLK_ALPHA_PLL_TYPE_LUCID_EVO , +CLK_ALPHA_PLL_TYPE_APSS , CLK_ALPHA_PLL_TYPE_MAX, };
Quoted 15 lines · Konrad Dybcio
Quoted 11 lines · Robert Marko
APSS PLL type will be used by the IPQ8074 APSS driver for providing the CPU core clocks and enabling CPU Frequency scaling.
This is ported from the downstream 5.4 kernel.
Signed-off-by Robert Marko <[email protected]>--- drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 13 insertions(+)
Quoted 11 lines
drivers/clk/qcom/clk-alpha-pll.c const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { · line 157
Quoted 9 lines
drivers/clk/qcom/clk-alpha-pll.c +1
-0@@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1 ] =0x34 , }, + [CLK_ALPHA_PLL_TYPE_APSS] = {The name is surely not correct, can somebody from qcom chime in and suggest what it should be?
Hi Konrad,
That is how Qualcomm refers to the type in the downstream 4.4 and 5.4 kernels. I dont have any other reference to the name unless somebody from Qualcomm can chime in.
Regards,
Robert
Quoted 28 lines
Konrad
Quoted 26 lines
drivers/clk/qcom/clk-alpha-pll.c +11
-0+ [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL_U] = 0xff, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0xff, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + [PLL_OFF_STATUS] = 0x28, + }, };EXPORT_SYMBOL_GPL (clk_alpha_pll_regs);drivers/clk/qcom/clk-alpha-pll.h +1
-0@@ -18,6 +18,7 @@ enum {CLK_ALPHA_PLL_TYPE_AGERA ,CLK_ALPHA_PLL_TYPE_ZONDA ,CLK_ALPHA_PLL_TYPE_LUCID_EVO , +CLK_ALPHA_PLL_TYPE_APSS , CLK_ALPHA_PLL_TYPE_MAX, };