dt-bindings: Arm CoreSight binding schema conversions

PATCH Superseded Rob Herring 4 participants 9 messages May 20, 2022 – May 23, 2022

Subsystems (3)

Device tree bindings Arm STM32 Arm/CoreSight framework and drivers

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Rob Herring

author maintainer

2022-05-20 21:44 UTC #1 lore raw

PATCH 1/2 dt-bindings: arm: Convert CoreSight bindings to DT schema

Each CoreSight component has slightly different requirements and nothing applies to every component, so each CoreSight component has its own schema document.

Signed-off-by Rob Herring <[email protected]>

---
 .../bindings/arm/arm,coresight-catu.yaml      | 101 +++++
 .../arm/arm,coresight-dynamic-funnel.yaml     | 126 ++++++
 .../bindings/arm/arm,coresight-etb10.yaml     |  92 ++++
 .../bindings/arm/arm,coresight-etm.yaml       | 156 +++++++
 .../arm/arm,coresight-static-replicator.yaml  |  90 ++++
 .../bindings/arm/arm,coresight-stm.yaml       | 101 +++++
 .../bindings/arm/arm,coresight-tmc.yaml       | 132 ++++++
 .../bindings/arm/arm,coresight-tpiu.yaml      |  91 ++++
 .../devicetree/bindings/arm/coresight.txt     | 402 ------------------
 9 files changed, 889 insertions(+), 402 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml
 delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt

Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml new file +101 -0

new file mode 100644
index 000000000000..d783d9276124
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm Coresight Address Translation Unit (CATU)
+
+maintainers:
+  - Mathieu Poirier <[email protected]>
+  - Mike Leach <[email protected]>
+  - Leo Yan <[email protected]>
+  - Suzuki K Poulose <[email protected]>
+
+description: |
+  CoreSight components are compliant with the ARM CoreSight architecture
+  specification and can be connected in various topologies to suit a particular
+  SoCs tracing needs. These trace components can generally be classified as
+  sinks, links and sources. Trace data produced by one or more sources flows
+  through the intermediate links connecting the source to the currently selected
+  sink.
+
+  The CoreSight Address Translation Unit (CATU) translates addresses between an
+  AXI master and system memory. The CATU is normally used along with the TMC to
+  implement scattering of virtual trace buffers in physical memory. The CATU
+  translates contiguous Virtual Addresses (VAs) from an AXI master into
+  non-contiguous Physical Addresses (PAs) that are intended for system memory.
+
+# Need a custom select here or 'arm,primecell' will match on lots of nodes
+select:
+  properties:
+    compatible:
+      contains:
+        const: arm,coresight-catu
+  required:
+    - compatible
+
+allOf:
+  - $ref: /schemas/arm/primecell.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: arm,coresight-catu
+      - const: arm,primecell
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: apb_pclk
+      - const: atclk
+
+  interrupts:
+    maxItems: 1
+    description: Address translation error interrupt
+
+  in-ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    additionalProperties: false
+
+    properties:
+      port:
+        description: AXI Slave connected to another Coresight component
+        $ref: /schemas/graph.yaml#/properties/port
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - in-ports
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    catu@207e0000 {
+        compatible = "arm,coresight-catu", "arm,primecell";
+        reg = <0x207e0000 0x1000>;
+
+        clocks = <&oscclk6a>;
+        clock-names = "apb_pclk";
+
+        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+        in-ports {
+            port {
+                catu_in_port: endpoint {
+                    remote-endpoint = <&etr_out_port>;
+                };
+            };
+        };
+    };
+...

Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml new file +126 -0

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Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml new file +92 -0

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Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +156 -0

156 lines not on this page · raw message

Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml new file +90 -0

90 lines not on this page · raw message

Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml new file +101 -0

101 lines not on this page · raw message

Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml new file +132 -0

132 lines not on this page · raw message

Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml new file +91 -0

91 lines not on this page · raw message

Documentation/devicetree/bindings/arm/coresight.txt deleted +0 ~~-402~~

402 lines not on this page · raw message

Signature · 1 line

2.34.1

Krzysztof Kozlowski

2022-05-21 14:54 UTC #2 lore raw

Re: [PATCH 1/2] dt-bindings: arm: Convert CoreSight bindings to DT schema

Quoted 4 lines · Rob Herring

Each CoreSight component has slightly different requirements and nothing applies to every component, so each CoreSight component has its own schema document.

(...)

Quoted 18 lines

Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml new file +18 -0

+        const: arm,coresight-dynamic-funnel
+  required:
+    - compatible
+
+allOf:
+  - $ref: /schemas/arm/primecell.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: arm,coresight-dynamic-funnel
+      - const: arm,primecell
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1

Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml line 58

Quoted 10 lines

Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml new file +10 -0

+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: apb_pclk
+      - const: atclk
+
+  in-ports:
+    $ref: /schemas/graph.yaml#/properties/ports

Shouldn't this be with unevaluatedProperties:false?

Quoted 15 lines

Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml new file +15 -0

+
+    patternProperties:
+      '^port(@[0-7])?$':
+        description: Input connections from CoreSight Trace bus
+        $ref: /schemas/graph.yaml#/properties/port
+
+  out-ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    additionalProperties: false
+
+    properties:
+      port:
+        description: Output connection to CoreSight Trace bus
+        $ref: /schemas/graph.yaml#/properties/port
+

(...)

Quoted 30 lines

Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml new file +30 -0

+title: Arm CoreSight Static Trace Bus Replicator
+
+maintainers:
+  - Mathieu Poirier <[email protected]>
+  - Mike Leach <[email protected]>
+  - Leo Yan <[email protected]>
+  - Suzuki K Poulose <[email protected]>
+
+description: |
+  CoreSight components are compliant with the ARM CoreSight architecture
+  specification and can be connected in various topologies to suit a particular
+  SoCs tracing needs. These trace components can generally be classified as
+  sinks, links and sources. Trace data produced by one or more sources flows
+  through the intermediate links connecting the source to the currently selected
+  sink.
+
+  The Coresight replicator splits a single trace stream into two trace streams
+  for systems that have more than one trace sink component.
+
+properties:
+  compatible:
+    const: arm,coresight-static-replicator
+
+  in-ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    additionalProperties: false
+
+    properties:
+      port:
+        description: Input connection from CoreSight Trace bus

Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml line 46

Quoted 10 lines

Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml new file +10 -0

+        $ref: /schemas/graph.yaml#/properties/port
+
+  out-ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    patternProperties:
+      '^port@[01]$':
+        description: Output connections to CoreSight Trace bus
+        $ref: /schemas/graph.yaml#/properties/port
+

Same question.

(...)

Quoted 63 lines

Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml new file +63 -0

+title: Arm CoreSight Trace Memory Controller
+
+maintainers:
+  - Mathieu Poirier <[email protected]>
+  - Mike Leach <[email protected]>
+  - Leo Yan <[email protected]>
+  - Suzuki K Poulose <[email protected]>
+
+description: |
+  CoreSight components are compliant with the ARM CoreSight architecture
+  specification and can be connected in various topologies to suit a particular
+  SoCs tracing needs. These trace components can generally be classified as
+  sinks, links and sources. Trace data produced by one or more sources flows
+  through the intermediate links connecting the source to the currently selected
+  sink.
+
+  Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
+  FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
+  mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
+
+# Need a custom select here or 'arm,primecell' will match on lots of nodes
+select:
+  properties:
+    compatible:
+      contains:
+        const: arm,coresight-tmc
+  required:
+    - compatible
+
+allOf:
+  - $ref: /schemas/arm/primecell.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: arm,coresight-tmc
+      - const: arm,primecell
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: apb_pclk
+      - const: atclk
+
+  arm,buffer-size:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    deprecated: true
+    description:
+      Size of contiguous buffer space for TMC ETR (embedded trace router). The
+      buffer size can be configured dynamically via buffer_size property in
+      sysfs instead.
+
+  arm,scatter-gather:
+    type: boolean
+    description:
+      Indicates that the TMC-ETR can safely use the SG mode on this system.

Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml line 79

Quoted 10 lines

Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml new file +10 -0

+
+  arm,max-burst-size:
+    description:
+      The maximum burst size initiated by TMC on the AXI master interface. The
+      burst size can be in the range [0..15], the setting supports one data
+      transfer per burst up to a maximum of 16 data transfers per burst.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    maximum: 15
+
+

Just one blank line

Best regards,
Krzysztof

Rob Herring

author maintainer

2022-05-23 12:54 UTC #3 lore raw

Re: [PATCH 1/2] dt-bindings: arm: Convert CoreSight bindings to DT schema

Quoted 30 lines · Krzysztof Kozlowski

Quoted 4 lines · Rob Herring
Each CoreSight component has slightly different requirements and nothing applies to every component, so each CoreSight component has its own schema document.
(...)
Quoted 22 lines
Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml new file +22 -0
+        const: arm,coresight-dynamic-funnel
+  required:
+    - compatible
+
+allOf:
+  - $ref: /schemas/arm/primecell.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: arm,coresight-dynamic-funnel
+      - const: arm,primecell
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1

Quoted 8 lines

Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml line 65
Quoted 6 lines
Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml new file +6 -0
+    items:
+      - const: apb_pclk
+      - const: atclk
+
+  in-ports:
+    $ref: /schemas/graph.yaml#/properties/ports
Shouldn't this be with unevaluatedProperties:false?

No, because the ports definition has 'additionalProperties: false'. That does mean port nodes aren't actually restricted to 0-7 in any way. Not really any way to fix that other than listing #address-cells/#size-cells here or a pattern matching disallowed ports. But I think the limit to 8 is just current implementations and perhaps practical limit of how many streams of trace data can be combined.

Quoted 5 lines

Quoted 5 lines
Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml new file +5 -0
+
+    patternProperties:
+      '^port(@[0-7])?$':
+        description: Input connections from CoreSight Trace bus
+        $ref: /schemas/graph.yaml#/properties/port

Suzuki K Poulose

maintainer

2022-05-23 11:03 UTC #4 lore raw

Re: [PATCH 1/2] dt-bindings: arm: Convert CoreSight bindings to DT schema

In reply to Rob Herring

Hi Rob,

Thanks a lot for converting these to yaml. Some minor comments below.

In general, the "clocks" and "clock-names" are optional (e.g, for etm4 with system register access).

Quoted 25 lines · Rob Herring

Each CoreSight component has slightly different requirements and nothing applies to every component, so each CoreSight component has its own schema document.
Signed-off-by Rob Herring <[email protected]>
---
  .../bindings/arm/arm,coresight-catu.yaml      | 101 +++++
  .../arm/arm,coresight-dynamic-funnel.yaml     | 126 ++++++
  .../bindings/arm/arm,coresight-etb10.yaml     |  92 ++++
  .../bindings/arm/arm,coresight-etm.yaml       | 156 +++++++
  .../arm/arm,coresight-static-replicator.yaml  |  90 ++++
  .../bindings/arm/arm,coresight-stm.yaml       | 101 +++++
  .../bindings/arm/arm,coresight-tmc.yaml       | 132 ++++++
  .../bindings/arm/arm,coresight-tpiu.yaml      |  91 ++++
  .../devicetree/bindings/arm/coresight.txt     | 402 ------------------
  9 files changed, 889 insertions(+), 402 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt

...

Quoted 14 lines

Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml new file +8 -0

new file mode 100644
index 000000000000..ee1ce47225be
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm CoreSight Trace Memory Controller
+

...

Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml line 96

Quoted 8 lines

Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml new file +8 -0

+  out-ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    additionalProperties: false
+
+    properties:
+      port:
+        description: AXI Master output connection. Used for ETR and ETF
+          configurations.

nit: This is only for ETRs. Never for ETFs.

Suzuki

Rob Herring

author maintainer

2022-05-23 13:57 UTC #5 lore raw

Re: [PATCH 1/2] dt-bindings: arm: Convert CoreSight bindings to DT schema

Quoted 6 lines · Suzuki K Poulose

Hi Rob,
Thanks a lot for converting these to yaml. Some minor comments below.
In general, the "clocks" and "clock-names" are optional (e.g, for etm4 with system register access).

Reality, based on running dtbs_checks, seems to be that all instances have them, and the original doc said required.

Quoted 56 lines · Rob Herring

Quoted 25 lines
Each CoreSight component has slightly different requirements and nothing applies to every component, so each CoreSight component has its own schema document.
Signed-off-by Rob Herring <[email protected]>
---
  .../bindings/arm/arm,coresight-catu.yaml      | 101 +++++
  .../arm/arm,coresight-dynamic-funnel.yaml     | 126 ++++++
  .../bindings/arm/arm,coresight-etb10.yaml     |  92 ++++
  .../bindings/arm/arm,coresight-etm.yaml       | 156 +++++++
  .../arm/arm,coresight-static-replicator.yaml  |  90 ++++
  .../bindings/arm/arm,coresight-stm.yaml       | 101 +++++
  .../bindings/arm/arm,coresight-tmc.yaml       | 132 ++++++
  .../bindings/arm/arm,coresight-tpiu.yaml      |  91 ++++
  .../devicetree/bindings/arm/coresight.txt     | 402 ------------------
  9 files changed, 889 insertions(+), 402 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt
...
Quoted 14 lines
Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml new file +8 -0
new file mode 100644
index 000000000000..ee1ce47225be
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm CoreSight Trace Memory Controller
+
...
Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml line 96
Quoted 8 lines
Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml new file +8 -0
+  out-ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    additionalProperties: false
+
+    properties:
+      port:
+        description: AXI Master output connection. Used for ETR and ETF
+          configurations.

Quoted 1 line

nit: This is only for ETRs. Never for ETFs.

What about this example[1]? It's not AXI, but ATB actually.

Rob

[1] https://developer.arm.com/documentation/ddi0461/b/Introduction/Example-systems-with-different-configurations/ETF--ETR--and-TPIU

Rob Herring

author maintainer

2022-05-20 21:44 UTC #6 lore raw

PATCH 2/2 dt-bindings: arm: Convert CoreSight CPU debug to DT schema

In reply to Rob Herring

Convert the CoreSight CPU debug binding to DT schema format.

Signed-off-by Rob Herring <[email protected]>

---
 .../bindings/arm/arm,coresight-cpu-debug.yaml | 81 +++++++++++++++++++
 .../bindings/arm/coresight-cpu-debug.txt      | 49 -----------
 2 files changed, 81 insertions(+), 49 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml
 delete mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt

Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml new file +81 -0

new file mode 100644
index 000000000000..0a6bc03ebe00
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CoreSight CPU Debug Component
+
+maintainers:
+  - Mathieu Poirier <[email protected]>
+  - Mike Leach <[email protected]>
+  - Leo Yan <[email protected]>
+  - Suzuki K Poulose <[email protected]>
+
+description: |
+  CoreSight CPU debug component are compliant with the ARMv8 architecture
+  reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
+  external debug module is mainly used for two modes: self-hosted debug and
+  external debug, and it can be accessed from mmio region from Coresight and
+  eventually the debug module connects with CPU for debugging. And the debug
+  module provides sample-based profiling extension, which can be used to sample
+  CPU program counter, secure state and exception level, etc; usually every CPU
+  has one dedicated debug module to be connected.
+
+select:
+  properties:
+    compatible:
+      contains:
+        const: arm,coresight-cpu-debug
+  required:
+    - compatible
+
+allOf:
+  - $ref: /schemas/arm/primecell.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: arm,coresight-cpu-debug
+      - const: arm,primecell
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    maxItems: 1
+
+  cpu:
+    description:
+      A phandle to the cpu this debug component is bound to.
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+  power-domains:
+    maxItems: 1
+    description:
+      A phandle to the debug power domain if the debug logic has its own
+      dedicated power domain. CPU idle states may also need to be separately
+      constrained to keep CPU cores powered.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - cpu
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    debug@f6590000 {
+        compatible = "arm,coresight-cpu-debug", "arm,primecell";
+        reg = <0xf6590000 0x1000>;
+        clocks = <&sys_ctrl 1>;
+        clock-names = "apb_pclk";
+        cpu = <&cpu0>;
+    };
+...

Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt deleted +0 ~~-49~~

49 lines not on this page · raw message

Signature · 1 line

2.34.1

Leo Yan

Reviewed-by on v1 2/2

2022-05-21 13:28 UTC #7 lore raw

Re: [PATCH 2/2] dt-bindings: arm: Convert CoreSight CPU debug to DT schema

Quoted 3 lines · Rob Herring

Convert the CoreSight CPU debug binding to DT schema format.
Signed-off-by Rob Herring <[email protected]>

Compared line by line between old DT binding and new yaml file, I found only one difference is in the new yaml file it doesn't contain below info for constraints CPU power states:

"using "cpuidle.off=1" or "nohlt" in the kernel command line or
sysfs node ..."

IIUC, yaml file will be used not only for Linux kernel, thus it makes sense to remove the Linux specific info. Looks good to me:

Reviewed-by Leo Yan <[email protected]>

Krzysztof Kozlowski

Reviewed-by on v1 2/2

2022-05-21 14:47 UTC #8 lore raw

Re: [PATCH 2/2] dt-bindings: arm: Convert CoreSight CPU debug to DT schema

In reply to Rob Herring

Quoted 3 lines · Rob Herring

Convert the CoreSight CPU debug binding to DT schema format.
Signed-off-by Rob Herring <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof