From: Nicolas Chautru <[email protected]>
v8: Rebased to latest and fix related compilation error. Added acc200.ini and updated rel_notes.
Formatting improvement in comments, docs and commit message.
v7: Additional update in commits 9,10,11 based on review from Maxime.
v5/v6:Updates based on Maxime reviews of v4/v5. Thanks.
v4: Rebase suggested by Maxime to split first commit and update the order within the series. No functional change.
v3: Putting together ACC100 and ACC200 PMDs in common acc directory based on previous discussion on v2.
v2: Includes now code refactory to have common structures and code reused with the parallel ACC1XX serie PMD which can be shared moving forward.
v1: This is targeting 22.11 and includes the PMD for the new serie integrated accelerator on Intel Xeon SPR-EEC.
Nic Chautru (13):
baseband/acc100: remove unused registers baseband/acc100: refactor to segregate common code baseband/acc: rename directory from acc100 to acc baseband/acc: add HW register definitions for ACC200 baseband/acc: add info get function for ACC200 baseband/acc: add queue configuration for ACC200 baseband/acc: add LDPC processing functions baseband/acc: add LTE processing functions baseband/acc: add support for FFT operations baseband/acc: support interrupt baseband/acc: add device status and vf2pf comms baseband/acc: add PF configure companion function baseband/acc: simplify meson dependency
Nicolas Chautru (1):
baseband/acc: introduce PMD for ACC200
MAINTAINERS | 5 +-
app/test-bbdev/meson.build | 4 +-
app/test-bbdev/test_bbdev_perf.c | 81 +-
doc/guides/bbdevs/acc200.rst | 257 ++
doc/guides/bbdevs/features/acc200.ini | 14 +
doc/guides/bbdevs/features/default.ini | 1 +
doc/guides/bbdevs/index.rst | 1 +
doc/guides/rel_notes/release_22_11.rst | 6 +
drivers/baseband/acc/acc100_pf_enum.h | 147 +
drivers/baseband/acc/acc100_pmd.h | 177 +
.../baseband/{acc100 => acc}/acc100_vf_enum.h | 0
drivers/baseband/{acc100 => acc}/acc101_pmd.h | 10 -
drivers/baseband/acc/acc200_pf_enum.h | 108 +
drivers/baseband/acc/acc200_pmd.h | 196 +
drivers/baseband/acc/acc200_vf_enum.h | 83 +
drivers/baseband/acc/acc_common.h | 1389 ++++++
drivers/baseband/acc/meson.build | 8 +
drivers/baseband/acc/rte_acc100_cfg.h | 49 +
.../baseband/{acc100 => acc}/rte_acc100_pmd.c | 1773 +++-----
drivers/baseband/acc/rte_acc200_cfg.h | 48 +
drivers/baseband/acc/rte_acc200_pmd.c | 3941 +++++++++++++++++
.../rte_acc_common_cfg.h} | 62 +-
drivers/baseband/{acc100 => acc}/version.map | 1 +
drivers/baseband/acc100/acc100_pf_enum.h | 1086 -----
drivers/baseband/acc100/acc100_pmd.h | 624 ---
drivers/baseband/acc100/meson.build | 8 -
drivers/baseband/meson.build | 2 +-
27 files changed, 7104 insertions(+), 2977 deletions(-)
create mode 100644 doc/guides/bbdevs/acc200.rst
create mode 100644 doc/guides/bbdevs/features/acc200.ini
create mode 100644 drivers/baseband/acc/acc100_pf_enum.h
create mode 100644 drivers/baseband/acc/acc100_pmd.h
rename drivers/baseband/{acc100 => acc}/acc100_vf_enum.h (100%)
rename drivers/baseband/{acc100 => acc}/acc101_pmd.h (76%)
create mode 100644 drivers/baseband/acc/acc200_pf_enum.h
create mode 100644 drivers/baseband/acc/acc200_pmd.h
create mode 100644 drivers/baseband/acc/acc200_vf_enum.h
create mode 100644 drivers/baseband/acc/acc_common.h
create mode 100644 drivers/baseband/acc/meson.build
create mode 100644 drivers/baseband/acc/rte_acc100_cfg.h
rename drivers/baseband/{acc100 => acc}/rte_acc100_pmd.c (71%)
create mode 100644 drivers/baseband/acc/rte_acc200_cfg.h
create mode 100644 drivers/baseband/acc/rte_acc200_pmd.c
rename drivers/baseband/{acc100/rte_acc100_cfg.h => acc/rte_acc_common_cfg.h} (58%)
rename drivers/baseband/{acc100 => acc}/version.map (76%)
delete mode 100644 drivers/baseband/acc100/acc100_pf_enum.h
delete mode 100644 drivers/baseband/acc100/acc100_pmd.h
delete mode 100644 drivers/baseband/acc100/meson.buildSignature · 1 line
2.37.1
PATCH v8 1/14 baseband/acc100: remove unused registers
From: Nic Chautru <[email protected]>
Cleanep up the enum files to remove un-used registers definitions. No functionality change.
Signed-off-by Nic Chautru <[email protected]>
Reviewed-by Maxime Coquelin <[email protected]>
--- drivers/baseband/acc100/acc100_pf_enum.h | 939 ----------------------- 1 file changed, 939 deletions(-)
drivers/baseband/acc100/acc100_pf_enum.h +0 -939
@@ -14,32 +14,6 @@enum { HWPfQmgrEgressQueuesTemplate =0x0007FE00 , HWPfQmgrIngressAq =0x00080000 , - HWPfQmgrArbQAvail =0x00A00010 , - HWPfQmgrArbQBlock =0x00A00014 , - HWPfQmgrAqueueDropNotifEn =0x00A00024 , - HWPfQmgrAqueueDisableNotifEn =0x00A00028 , - HWPfQmgrSoftReset =0x00A00038 , - HWPfQmgrInitStatus =0x00A0003C , - HWPfQmgrAramWatchdogCount =0x00A00040 , - HWPfQmgrAramWatchdogCounterEn =0x00A00044 , - HWPfQmgrAxiWatchdogCount =0x00A00048 , - HWPfQmgrAxiWatchdogCounterEn =0x00A0004C , - HWPfQmgrProcessWatchdogCount =0x00A00050 , - HWPfQmgrProcessWatchdogCounterEn =0x00A00054 , - HWPfQmgrProcessUl4GWatchdogCounter =0x00A00058 , - HWPfQmgrProcessDl4GWatchdogCounter =0x00A0005C , - HWPfQmgrProcessUl5GWatchdogCounter =0x00A00060 , - HWPfQmgrProcessDl5GWatchdogCounter =0x00A00064 , - HWPfQmgrProcessMldWatchdogCounter =0x00A00068 , - HWPfQmgrMsiOverflowUpperVf =0x00A00070 , - HWPfQmgrMsiOverflowLowerVf =0x00A00074 , - HWPfQmgrMsiWatchdogOverflow =0x00A00078 , - HWPfQmgrMsiOverflowEnable =0x00A0007C , - HWPfQmgrDebugAqPointerMemGrp =0x00A00100 , - HWPfQmgrDebugOutputArbQFifoGrp =0x00A00140 , - HWPfQmgrDebugMsiFifoGrp =0x00A00180 , - HWPfQmgrDebugAxiWdTimeoutMsiFifo =0x00A001C0 , - HWPfQmgrDebugProcessWdTimeoutMsiFifo =0x00A001C4 , HWPfQmgrDepthLog2Grp =0x00A00200 , HWPfQmgrTholdGrp =0x00A00300 , HWPfQmgrGrpTmplateReg0Indx =0x00A00600 ,
@@ -48,85 +22,23 @@ enum { HWPfQmgrGrpTmplateReg3Indx =0x00A00780 , HWPfQmgrGrpTmplateReg4Indx =0x00A00800 , HWPfQmgrVfBaseAddr =0x00A01000 , - HWPfQmgrUl4GWeightRrVf =0x00A02000 , - HWPfQmgrDl4GWeightRrVf =0x00A02100 , - HWPfQmgrUl5GWeightRrVf =0x00A02200 , - HWPfQmgrDl5GWeightRrVf =0x00A02300 , - HWPfQmgrMldWeightRrVf =0x00A02400 , HWPfQmgrArbQDepthGrp =0x00A02F00 , HWPfQmgrGrpFunction0 =0x00A02F40 , - HWPfQmgrGrpFunction1 =0x00A02F44 , HWPfQmgrGrpPriority =0x00A02F48 , - HWPfQmgrWeightSync =0x00A03000 , HWPfQmgrAqEnableVf =0x00A10000 , - HWPfQmgrAqResetVf =0x00A20000 , HWPfQmgrRingSizeVf =0x00A20004 , HWPfQmgrGrpDepthLog20Vf =0x00A20008 , HWPfQmgrGrpDepthLog21Vf =0x00A2000C , - HWPfQmgrGrpFunction0Vf =0x00A20010 , - HWPfQmgrGrpFunction1Vf =0x00A20014 , HWPfDmaConfig0Reg =0x00B80000 , HWPfDmaConfig1Reg =0x00B80004 , HWPfDmaQmgrAddrReg =0x00B80008 , - HWPfDmaSoftResetReg =0x00B8000C , HWPfDmaAxcacheReg =0x00B80010 , - HWPfDmaVersionReg =0x00B80014 , - HWPfDmaFrameThreshold =0x00B80018 , - HWPfDmaTimestampLo =0x00B8001C , - HWPfDmaTimestampHi =0x00B80020 , - HWPfDmaAxiStatus =0x00B80028 , HWPfDmaAxiControl =0x00B8002C , - HWPfDmaNoQmgr =0x00B80030 , - HWPfDmaQosScale =0x00B80034 , HWPfDmaQmanen =0x00B80040 , - HWPfDmaQmgrQosBase =0x00B80060 , - HWPfDmaFecClkGatingEnable =0x00B80080 , - HWPfDmaPmEnable =0x00B80084 , - HWPfDmaQosEnable =0x00B80088 , - HWPfDmaHarqWeightedRrFrameThreshold =0x00B800B0 , - HWPfDmaDataSmallWeightedRrFrameThresh =0x00B800B4 , - HWPfDmaDataLargeWeightedRrFrameThresh =0x00B800B8 , - HWPfDmaInboundCbMaxSize =0x00B800BC , HWPfDmaInboundDrainDataSize =0x00B800C0 , HWPfDmaVfDdrBaseRw =0x00B80400 , - HWPfDmaCmplTmOutCnt =0x00B80800 , - HWPfDmaProcTmOutCnt =0x00B80804 , - HWPfDmaStatusRrespBresp =0x00B80810 , - HWPfDmaCfgRrespBresp =0x00B80814 , - HWPfDmaStatusMemParErr =0x00B80818 , - HWPfDmaCfgMemParErrEn =0x00B8081C , - HWPfDmaStatusDmaHwErr =0x00B80820 , - HWPfDmaCfgDmaHwErrEn =0x00B80824 , - HWPfDmaStatusFecCoreErr =0x00B80828 , - HWPfDmaCfgFecCoreErrEn =0x00B8082C , - HWPfDmaStatusFcwDescrErr =0x00B80830 , - HWPfDmaCfgFcwDescrErrEn =0x00B80834 , - HWPfDmaStatusBlockTransmit =0x00B80838 , - HWPfDmaBlockOnErrEn =0x00B8083C , - HWPfDmaStatusFlushDma =0x00B80840 , - HWPfDmaFlushDmaOnErrEn =0x00B80844 , - HWPfDmaStatusSdoneFifoFull =0x00B80848 , - HWPfDmaStatusDescriptorErrLoVf =0x00B8084C , - HWPfDmaStatusDescriptorErrHiVf =0x00B80850 , - HWPfDmaStatusFcwErrLoVf =0x00B80854 , - HWPfDmaStatusFcwErrHiVf =0x00B80858 , - HWPfDmaStatusDataErrLoVf =0x00B8085C , - HWPfDmaStatusDataErrHiVf =0x00B80860 , - HWPfDmaCfgMsiEnSoftwareErr =0x00B80864 , HWPfDmaDescriptorSignatuture =0x00B80868 , - HWPfDmaFcwSignature =0x00B8086C , HWPfDmaErrorDetectionEn =0x00B80870 , - HWPfDmaErrCntrlFifoDebug =0x00B8087C , - HWPfDmaStatusToutData =0x00B80880 , - HWPfDmaStatusToutDesc =0x00B80884 , - HWPfDmaStatusToutUnexpData =0x00B80888 , - HWPfDmaStatusToutUnexpDesc =0x00B8088C , - HWPfDmaStatusToutProcess =0x00B80890 , - HWPfDmaConfigCtoutOutDataEn =0x00B808A0 , - HWPfDmaConfigCtoutOutDescrEn =0x00B808A4 , - HWPfDmaConfigUnexpComplDataEn =0x00B808A8 , - HWPfDmaConfigUnexpComplDescrEn =0x00B808AC , - HWPfDmaConfigPtoutOutEn =0x00B808B0 , HWPfDmaFec5GulDescBaseLoRegVf =0x00B88020 , HWPfDmaFec5GulDescBaseHiRegVf =0x00B88024 , HWPfDmaFec5GulRespPtrLoRegVf = 0x00B88028,
@@ -143,414 +55,34 @@ enum { HWPfDmaFec4GdlDescBaseHiRegVf =0x00B88084 , HWPfDmaFec4GdlRespPtrLoRegVf =0x00B88088 , HWPfDmaFec4GdlRespPtrHiRegVf =0x00B8808C , - HWPfDmaVfDdrBaseRangeRo =0x00B880A0 , - HWPfQosmonACntrlReg =0x00B90000 , HWPfQosmonAEvalOverflow0 =0x00B90008 , - HWPfQosmonAEvalOverflow1 =0x00B9000C , - HWPfQosmonADivTerm =0x00B90010 , - HWPfQosmonATickTerm =0x00B90014 , - HWPfQosmonAEvalTerm =0x00B90018 , - HWPfQosmonAAveTerm =0x00B9001C , - HWPfQosmonAForceEccErr =0x00B90020 , - HWPfQosmonAEccErrDetect =0x00B90024 , - HWPfQosmonAIterationConfig0Low =0x00B90060 , - HWPfQosmonAIterationConfig0High =0x00B90064 , - HWPfQosmonAIterationConfig1Low =0x00B90068 , - HWPfQosmonAIterationConfig1High =0x00B9006C , - HWPfQosmonAIterationConfig2Low =0x00B90070 , - HWPfQosmonAIterationConfig2High =0x00B90074 , - HWPfQosmonAIterationConfig3Low =0x00B90078 , - HWPfQosmonAIterationConfig3High =0x00B9007C , - HWPfQosmonAEvalMemAddr =0x00B90080 , - HWPfQosmonAEvalMemData =0x00B90084 , - HWPfQosmonAXaction =0x00B900C0 , - HWPfQosmonARemThres1Vf =0x00B90400 , - HWPfQosmonAThres2Vf =0x00B90404 , - HWPfQosmonAWeiFracVf =0x00B90408 , - HWPfQosmonARrWeiVf =0x00B9040C , HWPfPermonACntrlRegVf =0x00B98000 , - HWPfPermonACountVf =0x00B98008 , - HWPfPermonAKCntLoVf =0x00B98010 , - HWPfPermonAKCntHiVf =0x00B98014 , - HWPfPermonADeltaCntLoVf =0x00B98020 , - HWPfPermonADeltaCntHiVf =0x00B98024 , - HWPfPermonAVersionReg =0x00B9C000 , - HWPfPermonACbControlFec =0x00B9C0F0 , - HWPfPermonADltTimerLoFec =0x00B9C0F4 , - HWPfPermonADltTimerHiFec =0x00B9C0F8 , - HWPfPermonACbCountFec =0x00B9C100 , - HWPfPermonAAccExecTimerLoFec =0x00B9C104 , - HWPfPermonAAccExecTimerHiFec =0x00B9C108 , - HWPfPermonAExecTimerMinFec =0x00B9C200 , - HWPfPermonAExecTimerMaxFec =0x00B9C204 , - HWPfPermonAControlBusMon =0x00B9C400 , - HWPfPermonAConfigBusMon =0x00B9C404 , - HWPfPermonASkipCountBusMon =0x00B9C408 , - HWPfPermonAMinLatBusMon =0x00B9C40C , - HWPfPermonAMaxLatBusMon =0x00B9C500 , - HWPfPermonATotalLatLowBusMon =0x00B9C504 , - HWPfPermonATotalLatUpperBusMon =0x00B9C508 , - HWPfPermonATotalReqCntBusMon =0x00B9C50C , - HWPfQosmonBCntrlReg =0x00BA0000 , HWPfQosmonBEvalOverflow0 =0x00BA0008 , - HWPfQosmonBEvalOverflow1 =0x00BA000C , - HWPfQosmonBDivTerm =0x00BA0010 , - HWPfQosmonBTickTerm =0x00BA0014 , - HWPfQosmonBEvalTerm =0x00BA0018 , - HWPfQosmonBAveTerm =0x00BA001C , - HWPfQosmonBForceEccErr =0x00BA0020 , - HWPfQosmonBEccErrDetect =0x00BA0024 , - HWPfQosmonBIterationConfig0Low =0x00BA0060 , - HWPfQosmonBIterationConfig0High =0x00BA0064 , - HWPfQosmonBIterationConfig1Low =0x00BA0068 , - HWPfQosmonBIterationConfig1High =0x00BA006C , - HWPfQosmonBIterationConfig2Low =0x00BA0070 , - HWPfQosmonBIterationConfig2High =0x00BA0074 , - HWPfQosmonBIterationConfig3Low =0x00BA0078 , - HWPfQosmonBIterationConfig3High =0x00BA007C , - HWPfQosmonBEvalMemAddr =0x00BA0080 , - HWPfQosmonBEvalMemData =0x00BA0084 , - HWPfQosmonBXaction =0x00BA00C0 , - HWPfQosmonBRemThres1Vf =0x00BA0400 , - HWPfQosmonBThres2Vf =0x00BA0404 , - HWPfQosmonBWeiFracVf =0x00BA0408 , - HWPfQosmonBRrWeiVf =0x00BA040C , HWPfPermonBCntrlRegVf =0x00BA8000 , - HWPfPermonBCountVf =0x00BA8008 , - HWPfPermonBKCntLoVf =0x00BA8010 , - HWPfPermonBKCntHiVf =0x00BA8014 , - HWPfPermonBDeltaCntLoVf =0x00BA8020 , - HWPfPermonBDeltaCntHiVf =0x00BA8024 , - HWPfPermonBVersionReg =0x00BAC000 , - HWPfPermonBCbControlFec =0x00BAC0F0 , - HWPfPermonBDltTimerLoFec =0x00BAC0F4 , - HWPfPermonBDltTimerHiFec =0x00BAC0F8 , - HWPfPermonBCbCountFec =0x00BAC100 , - HWPfPermonBAccExecTimerLoFec =0x00BAC104 , - HWPfPermonBAccExecTimerHiFec =0x00BAC108 , - HWPfPermonBExecTimerMinFec =0x00BAC200 , - HWPfPermonBExecTimerMaxFec =0x00BAC204 , - HWPfPermonBControlBusMon =0x00BAC400 , - HWPfPermonBConfigBusMon =0x00BAC404 , - HWPfPermonBSkipCountBusMon =0x00BAC408 , - HWPfPermonBMinLatBusMon =0x00BAC40C , - HWPfPermonBMaxLatBusMon =0x00BAC500 , - HWPfPermonBTotalLatLowBusMon =0x00BAC504 , - HWPfPermonBTotalLatUpperBusMon =0x00BAC508 , - HWPfPermonBTotalReqCntBusMon =0x00BAC50C , - HwPfFabI2MArbCntrlReg =0x00BB0000 , HWPfFabricMode =0x00BB1000 , - HwPfFabI2MGrp0DebugReg =0x00BBF000 , - HwPfFabI2MGrp1DebugReg =0x00BBF004 , - HwPfFabI2MGrp2DebugReg =0x00BBF008 , - HwPfFabI2MGrp3DebugReg =0x00BBF00C , - HwPfFabI2MBuf0DebugReg =0x00BBF010 , - HwPfFabI2MBuf1DebugReg =0x00BBF014 , - HwPfFabI2MBuf2DebugReg =0x00BBF018 , - HwPfFabI2MBuf3DebugReg =0x00BBF01C , - HwPfFabM2IBuf0Grp0DebugReg =0x00BBF020 , - HwPfFabM2IBuf1Grp0DebugReg =0x00BBF024 , - HwPfFabM2IBuf0Grp1DebugReg =0x00BBF028 , - HwPfFabM2IBuf1Grp1DebugReg =0x00BBF02C , - HwPfFabM2IBuf0Grp2DebugReg =0x00BBF030 , - HwPfFabM2IBuf1Grp2DebugReg =0x00BBF034 , - HwPfFabM2IBuf0Grp3DebugReg =0x00BBF038 , - HwPfFabM2IBuf1Grp3DebugReg =0x00BBF03C , HWPfFecUl5gCntrlReg =0x00BC0000 , - HWPfFecUl5gI2MThreshReg =0x00BC0004 , - HWPfFecUl5gVersionReg =0x00BC0100 , - HWPfFecUl5gFcwStatusReg =0x00BC0104 , - HWPfFecUl5gWarnReg =0x00BC0108 , HwPfFecUl5gIbDebugReg =0x00BC0200 , - HwPfFecUl5gObLlrDebugReg =0x00BC0204 , - HwPfFecUl5gObHarqDebugReg =0x00BC0208 , - HwPfFecUl5g1CntrlReg =0x00BC1000 , - HwPfFecUl5g1I2MThreshReg =0x00BC1004 , - HwPfFecUl5g1VersionReg =0x00BC1100 , - HwPfFecUl5g1FcwStatusReg =0x00BC1104 , - HwPfFecUl5g1WarnReg =0x00BC1108 , - HwPfFecUl5g1IbDebugReg =0x00BC1200 , - HwPfFecUl5g1ObLlrDebugReg =0x00BC1204 , - HwPfFecUl5g1ObHarqDebugReg =0x00BC1208 , - HwPfFecUl5g2CntrlReg =0x00BC2000 , - HwPfFecUl5g2I2MThreshReg =0x00BC2004 , - HwPfFecUl5g2VersionReg =0x00BC2100 , - HwPfFecUl5g2FcwStatusReg =0x00BC2104 , - HwPfFecUl5g2WarnReg =0x00BC2108 , - HwPfFecUl5g2IbDebugReg =0x00BC2200 , - HwPfFecUl5g2ObLlrDebugReg =0x00BC2204 , - HwPfFecUl5g2ObHarqDebugReg =0x00BC2208 , - HwPfFecUl5g3CntrlReg =0x00BC3000 , - HwPfFecUl5g3I2MThreshReg =0x00BC3004 , - HwPfFecUl5g3VersionReg =0x00BC3100 , - HwPfFecUl5g3FcwStatusReg =0x00BC3104 , - HwPfFecUl5g3WarnReg =0x00BC3108 , - HwPfFecUl5g3IbDebugReg =0x00BC3200 , - HwPfFecUl5g3ObLlrDebugReg =0x00BC3204 , - HwPfFecUl5g3ObHarqDebugReg =0x00BC3208 , - HwPfFecUl5g4CntrlReg =0x00BC4000 , - HwPfFecUl5g4I2MThreshReg =0x00BC4004 , - HwPfFecUl5g4VersionReg =0x00BC4100 , - HwPfFecUl5g4FcwStatusReg =0x00BC4104 , - HwPfFecUl5g4WarnReg =0x00BC4108 , - HwPfFecUl5g4IbDebugReg =0x00BC4200 , - HwPfFecUl5g4ObLlrDebugReg =0x00BC4204 , - HwPfFecUl5g4ObHarqDebugReg =0x00BC4208 , - HwPfFecUl5g5CntrlReg =0x00BC5000 , - HwPfFecUl5g5I2MThreshReg =0x00BC5004 , - HwPfFecUl5g5VersionReg =0x00BC5100 , - HwPfFecUl5g5FcwStatusReg =0x00BC5104 , - HwPfFecUl5g5WarnReg =0x00BC5108 , - HwPfFecUl5g5IbDebugReg =0x00BC5200 , - HwPfFecUl5g5ObLlrDebugReg =0x00BC5204 , - HwPfFecUl5g5ObHarqDebugReg =0x00BC5208 , - HwPfFecUl5g6CntrlReg =0x00BC6000 , - HwPfFecUl5g6I2MThreshReg =0x00BC6004 , - HwPfFecUl5g6VersionReg =0x00BC6100 , - HwPfFecUl5g6FcwStatusReg =0x00BC6104 , - HwPfFecUl5g6WarnReg =0x00BC6108 , - HwPfFecUl5g6IbDebugReg =0x00BC6200 , - HwPfFecUl5g6ObLlrDebugReg =0x00BC6204 , - HwPfFecUl5g6ObHarqDebugReg =0x00BC6208 , - HwPfFecUl5g7CntrlReg =0x00BC7000 , - HwPfFecUl5g7I2MThreshReg =0x00BC7004 , - HwPfFecUl5g7VersionReg =0x00BC7100 , - HwPfFecUl5g7FcwStatusReg =0x00BC7104 , - HwPfFecUl5g7WarnReg =0x00BC7108 , - HwPfFecUl5g7IbDebugReg =0x00BC7200 , - HwPfFecUl5g7ObLlrDebugReg =0x00BC7204 , - HwPfFecUl5g7ObHarqDebugReg =0x00BC7208 , - HwPfFecUl5g8CntrlReg =0x00BC8000 , - HwPfFecUl5g8I2MThreshReg =0x00BC8004 , - HwPfFecUl5g8VersionReg =0x00BC8100 , - HwPfFecUl5g8FcwStatusReg =0x00BC8104 , - HwPfFecUl5g8WarnReg =0x00BC8108 , - HwPfFecUl5g8IbDebugReg =0x00BC8200 , - HwPfFecUl5g8ObLlrDebugReg =0x00BC8204 , - HwPfFecUl5g8ObHarqDebugReg =0x00BC8208 , - HWPfFecDl5gCntrlReg =0x00BCF000 , - HWPfFecDl5gI2MThreshReg =0x00BCF004 , - HWPfFecDl5gVersionReg =0x00BCF100 , - HWPfFecDl5gFcwStatusReg =0x00BCF104 , - HWPfFecDl5gWarnReg =0x00BCF108 , - HWPfFecUlVersionReg =0x00BD0000 , - HWPfFecUlControlReg =0x00BD0004 , - HWPfFecUlStatusReg =0x00BD0008 , - HWPfFecDlVersionReg =0x00BDF000 , - HWPfFecDlClusterConfigReg =0x00BDF004 , - HWPfFecDlBurstThres =0x00BDF00C , - HWPfFecDlClusterStatusReg0 =0x00BDF040 , - HWPfFecDlClusterStatusReg1 =0x00BDF044 , - HWPfFecDlClusterStatusReg2 =0x00BDF048 , - HWPfFecDlClusterStatusReg3 =0x00BDF04C , - HWPfFecDlClusterStatusReg4 =0x00BDF050 , - HWPfFecDlClusterStatusReg5 =0x00BDF054 , - HWPfChaFabPllPllrst =0x00C40000 , - HWPfChaFabPllClk0 =0x00C40004 , - HWPfChaFabPllClk1 =0x00C40008 , - HWPfChaFabPllBwadj =0x00C4000C , - HWPfChaFabPllLbw =0x00C40010 , - HWPfChaFabPllResetq =0x00C40014 , - HWPfChaFabPllPhshft0 =0x00C40018 , - HWPfChaFabPllPhshft1 =0x00C4001C , - HWPfChaFabPllDivq0 =0x00C40020 , - HWPfChaFabPllDivq1 =0x00C40024 , - HWPfChaFabPllDivq2 =0x00C40028 , - HWPfChaFabPllDivq3 =0x00C4002C , - HWPfChaFabPllDivq4 =0x00C40030 , - HWPfChaFabPllDivq5 =0x00C40034 , - HWPfChaFabPllDivq6 =0x00C40038 , - HWPfChaFabPllDivq7 =0x00C4003C , - HWPfChaDl5gPllPllrst =0x00C40080 , - HWPfChaDl5gPllClk0 =0x00C40084 , - HWPfChaDl5gPllClk1 =0x00C40088 , - HWPfChaDl5gPllBwadj =0x00C4008C , - HWPfChaDl5gPllLbw =0x00C40090 , - HWPfChaDl5gPllResetq =0x00C40094 , HWPfChaDl5gPllPhshft0 =0x00C40098 , - HWPfChaDl5gPllPhshft1 =0x00C4009C , - HWPfChaDl5gPllDivq0 =0x00C400A0 , - HWPfChaDl5gPllDivq1 =0x00C400A4 , - HWPfChaDl5gPllDivq2 =0x00C400A8 , - HWPfChaDl5gPllDivq3 =0x00C400AC , - HWPfChaDl5gPllDivq4 =0x00C400B0 , - HWPfChaDl5gPllDivq5 =0x00C400B4 , - HWPfChaDl5gPllDivq6 =0x00C400B8 , - HWPfChaDl5gPllDivq7 =0x00C400BC , - HWPfChaDl4gPllPllrst =0x00C40100 , - HWPfChaDl4gPllClk0 =0x00C40104 , - HWPfChaDl4gPllClk1 =0x00C40108 , - HWPfChaDl4gPllBwadj =0x00C4010C , - HWPfChaDl4gPllLbw =0x00C40110 , - HWPfChaDl4gPllResetq =0x00C40114 , - HWPfChaDl4gPllPhshft0 =0x00C40118 , - HWPfChaDl4gPllPhshft1 =0x00C4011C , - HWPfChaDl4gPllDivq0 =0x00C40120 , - HWPfChaDl4gPllDivq1 =0x00C40124 , - HWPfChaDl4gPllDivq2 =0x00C40128 , - HWPfChaDl4gPllDivq3 =0x00C4012C , - HWPfChaDl4gPllDivq4 =0x00C40130 , - HWPfChaDl4gPllDivq5 =0x00C40134 , - HWPfChaDl4gPllDivq6 =0x00C40138 , - HWPfChaDl4gPllDivq7 =0x00C4013C , - HWPfChaUl5gPllPllrst =0x00C40180 , - HWPfChaUl5gPllClk0 =0x00C40184 , - HWPfChaUl5gPllClk1 =0x00C40188 , - HWPfChaUl5gPllBwadj =0x00C4018C , - HWPfChaUl5gPllLbw =0x00C40190 , - HWPfChaUl5gPllResetq =0x00C40194 , - HWPfChaUl5gPllPhshft0 =0x00C40198 , - HWPfChaUl5gPllPhshft1 =0x00C4019C , - HWPfChaUl5gPllDivq0 =0x00C401A0 , - HWPfChaUl5gPllDivq1 =0x00C401A4 , - HWPfChaUl5gPllDivq2 =0x00C401A8 , - HWPfChaUl5gPllDivq3 =0x00C401AC , - HWPfChaUl5gPllDivq4 =0x00C401B0 , - HWPfChaUl5gPllDivq5 =0x00C401B4 , - HWPfChaUl5gPllDivq6 =0x00C401B8 , - HWPfChaUl5gPllDivq7 =0x00C401BC , - HWPfChaUl4gPllPllrst =0x00C40200 , - HWPfChaUl4gPllClk0 =0x00C40204 , - HWPfChaUl4gPllClk1 =0x00C40208 , - HWPfChaUl4gPllBwadj =0x00C4020C , - HWPfChaUl4gPllLbw =0x00C40210 , - HWPfChaUl4gPllResetq =0x00C40214 , - HWPfChaUl4gPllPhshft0 =0x00C40218 , - HWPfChaUl4gPllPhshft1 =0x00C4021C , - HWPfChaUl4gPllDivq0 =0x00C40220 , - HWPfChaUl4gPllDivq1 =0x00C40224 , - HWPfChaUl4gPllDivq2 =0x00C40228 , - HWPfChaUl4gPllDivq3 =0x00C4022C , - HWPfChaUl4gPllDivq4 =0x00C40230 , - HWPfChaUl4gPllDivq5 =0x00C40234 , - HWPfChaUl4gPllDivq6 =0x00C40238 , - HWPfChaUl4gPllDivq7 =0x00C4023C , - HWPfChaDdrPllPllrst =0x00C40280 , - HWPfChaDdrPllClk0 =0x00C40284 , - HWPfChaDdrPllClk1 =0x00C40288 , - HWPfChaDdrPllBwadj =0x00C4028C , - HWPfChaDdrPllLbw =0x00C40290 , - HWPfChaDdrPllResetq =0x00C40294 , - HWPfChaDdrPllPhshft0 =0x00C40298 , - HWPfChaDdrPllPhshft1 =0x00C4029C , - HWPfChaDdrPllDivq0 =0x00C402A0 , - HWPfChaDdrPllDivq1 =0x00C402A4 , - HWPfChaDdrPllDivq2 =0x00C402A8 , - HWPfChaDdrPllDivq3 =0x00C402AC , - HWPfChaDdrPllDivq4 =0x00C402B0 , - HWPfChaDdrPllDivq5 =0x00C402B4 , - HWPfChaDdrPllDivq6 =0x00C402B8 , - HWPfChaDdrPllDivq7 =0x00C402BC , - HWPfChaErrStatus =0x00C40400 , - HWPfChaErrMask =0x00C40404 , - HWPfChaDebugPcieMsiFifo =0x00C40410 , - HWPfChaDebugDdrMsiFifo =0x00C40414 , - HWPfChaDebugMiscMsiFifo =0x00C40418 , - HWPfChaPwmSet =0x00C40420 , - HWPfChaDdrRstStatus =0x00C40430 , HWPfChaDdrStDoneStatus =0x00C40434 , HWPfChaDdrWbRstCfg =0x00C40438 , HWPfChaDdrApbRstCfg =0x00C4043C , HWPfChaDdrPhyRstCfg =0x00C40440 , HWPfChaDdrCpuRstCfg =0x00C40444 , HWPfChaDdrSifRstCfg =0x00C40448 , - HWPfChaPadcfgPcomp0 =0x00C41000 , - HWPfChaPadcfgNcomp0 =0x00C41004 , - HWPfChaPadcfgOdt0 =0x00C41008 , - HWPfChaPadcfgProtect0 =0x00C4100C , - HWPfChaPreemphasisProtect0 =0x00C41010 , - HWPfChaPreemphasisCompen0 =0x00C41040 , - HWPfChaPreemphasisOdten0 =0x00C41044 , - HWPfChaPadcfgPcomp1 =0x00C41100 , - HWPfChaPadcfgNcomp1 =0x00C41104 , - HWPfChaPadcfgOdt1 =0x00C41108 , - HWPfChaPadcfgProtect1 =0x00C4110C , - HWPfChaPreemphasisProtect1 =0x00C41110 , - HWPfChaPreemphasisCompen1 =0x00C41140 , - HWPfChaPreemphasisOdten1 =0x00C41144 , - HWPfChaPadcfgPcomp2 =0x00C41200 , - HWPfChaPadcfgNcomp2 =0x00C41204 , - HWPfChaPadcfgOdt2 =0x00C41208 , - HWPfChaPadcfgProtect2 =0x00C4120C , - HWPfChaPreemphasisProtect2 =0x00C41210 , - HWPfChaPreemphasisCompen2 =0x00C41240 , - HWPfChaPreemphasisOdten4 =0x00C41444 , - HWPfChaPreemphasisOdten2 =0x00C41244 , - HWPfChaPadcfgPcomp3 =0x00C41300 , - HWPfChaPadcfgNcomp3 =0x00C41304 , - HWPfChaPadcfgOdt3 =0x00C41308 , - HWPfChaPadcfgProtect3 =0x00C4130C , - HWPfChaPreemphasisProtect3 =0x00C41310 , - HWPfChaPreemphasisCompen3 =0x00C41340 , - HWPfChaPreemphasisOdten3 =0x00C41344 , - HWPfChaPadcfgPcomp4 =0x00C41400 , - HWPfChaPadcfgNcomp4 =0x00C41404 , - HWPfChaPadcfgOdt4 =0x00C41408 , - HWPfChaPadcfgProtect4 =0x00C4140C , - HWPfChaPreemphasisProtect4 =0x00C41410 , - HWPfChaPreemphasisCompen4 =0x00C41440 , - HWPfHiVfToPfDbellVf =0x00C80000 , - HWPfHiPfToVfDbellVf =0x00C80008 , - HWPfHiInfoRingBaseLoVf =0x00C80010 , - HWPfHiInfoRingBaseHiVf =0x00C80014 , - HWPfHiInfoRingPointerVf =0x00C80018 , - HWPfHiInfoRingIntWrEnVf =0x00C80020 , - HWPfHiInfoRingPf2VfWrEnVf =0x00C80024 , - HWPfHiMsixVectorMapperVf =0x00C80060 , - HWPfHiModuleVersionReg =0x00C84000 , - HWPfHiIosf2axiErrLogReg =0x00C84004 , - HWPfHiHardResetReg =0x00C84008 , HWPfHi5GHardResetReg =0x00C8400C , HWPfHiInfoRingBaseLoRegPf =0x00C84010 , HWPfHiInfoRingBaseHiRegPf =0x00C84014 , HWPfHiInfoRingPointerRegPf =0x00C84018 , HWPfHiInfoRingIntWrEnRegPf =0x00C84020 , HWPfHiInfoRingVf2pfLoWrEnReg =0x00C84024 , - HWPfHiInfoRingVf2pfHiWrEnReg =0x00C84028 , - HWPfHiLogParityErrStatusReg =0x00C8402C , - HWPfHiLogDataParityErrorVfStatusLo =0x00C84030 , - HWPfHiLogDataParityErrorVfStatusHi =0x00C84034 , HWPfHiBlockTransmitOnErrorEn =0x00C84038 , HWPfHiCfgMsiIntWrEnRegPf =0x00C84040 , HWPfHiCfgMsiVf2pfLoWrEnReg =0x00C84044 , - HWPfHiCfgMsiVf2pfHighWrEnReg =0x00C84048 , - HWPfHiMsixVectorMapperPf =0x00C84060 , - HWPfHiApbWrWaitTime =0x00C84100 , - HWPfHiXCounterMaxValue =0x00C84104 , HWPfHiPfMode =0x00C84108 , HWPfHiClkGateHystReg =0x00C8410C , - HWPfHiSnoopBitsReg =0x00C84110 , HWPfHiMsiDropEnableReg =0x00C84114 , - HWPfHiMsiStatReg =0x00C84120 , - HWPfHiFifoOflStatReg =0x00C84124 , - HWPfHiHiDebugReg =0x00C841F4 , - HWPfHiDebugMemSnoopMsiFifo =0x00C841F8 , - HWPfHiDebugMemSnoopInputFifo =0x00C841FC , - HWPfHiMsixMappingConfig =0x00C84200 , - HWPfHiJunkReg =0x00C8FF00 , - HWPfDdrUmmcVer =0x00D00000 , - HWPfDdrUmmcCap =0x00D00010 , HWPfDdrUmmcCtrl =0x00D00020 , - HWPfDdrMpcPe =0x00D00080 , - HWPfDdrMpcPpri3 =0x00D00090 , - HWPfDdrMpcPpri2 =0x00D000A0 , - HWPfDdrMpcPpri1 =0x00D000B0 , - HWPfDdrMpcPpri0 =0x00D000C0 , - HWPfDdrMpcPrwgrpCtrl =0x00D000D0 , - HWPfDdrMpcPbw7 =0x00D000E0 , - HWPfDdrMpcPbw6 =0x00D000F0 , - HWPfDdrMpcPbw5 =0x00D00100 , - HWPfDdrMpcPbw4 =0x00D00110 , - HWPfDdrMpcPbw3 =0x00D00120 , - HWPfDdrMpcPbw2 =0x00D00130 , - HWPfDdrMpcPbw1 =0x00D00140 , - HWPfDdrMpcPbw0 =0x00D00150 , - HWPfDdrMemoryInit =0x00D00200 , - HWPfDdrMemoryInitDone =0x00D00210 , HWPfDdrMemInitPhyTrng0 =0x00D00240 , - HWPfDdrMemInitPhyTrng1 =0x00D00250 , - HWPfDdrMemInitPhyTrng2 =0x00D00260 , - HWPfDdrMemInitPhyTrng3 =0x00D00270 , HWPfDdrBcDram =0x00D003C0 , HWPfDdrBcAddrMap =0x00D003D0 , HWPfDdrBcRef = 0x00D003E0,
@@ -565,502 +97,31 @@ enum { HWPfDdrBcTim8 =0x00D00480 , HWPfDdrBcTim9 =0x00D00490 , HWPfDdrBcTim10 =0x00D004A0 , - HWPfDdrBcTim12 =0x00D004C0 , HWPfDdrDfiInit =0x00D004D0 , - HWPfDdrDfiInitComplete =0x00D004E0 , HWPfDdrDfiTim0 =0x00D004F0 , HWPfDdrDfiTim1 =0x00D00500 , HWPfDdrDfiPhyUpdEn =0x00D00530 , - HWPfDdrMemStatus =0x00D00540 , - HWPfDdrUmmcErrStatus =0x00D00550 , - HWPfDdrUmmcIntStatus =0x00D00560 , HWPfDdrUmmcIntEn =0x00D00570 , HWPfDdrPhyRdLatency =0x00D48400 , HWPfDdrPhyRdLatencyDbi =0x00D48410 , HWPfDdrPhyWrLatency =0x00D48420 , HWPfDdrPhyTrngType =0x00D48430 , - HWPfDdrPhyMrsTiming2 =0x00D48440 , - HWPfDdrPhyMrsTiming0 =0x00D48450 , - HWPfDdrPhyMrsTiming1 =0x00D48460 , - HWPfDdrPhyDramTmrd =0x00D48470 , - HWPfDdrPhyDramTmod =0x00D48480 , - HWPfDdrPhyDramTwpre =0x00D48490 , - HWPfDdrPhyDramTrfc =0x00D484A0 , - HWPfDdrPhyDramTrwtp =0x00D484B0 , HWPfDdrPhyMr01Dimm =0x00D484C0 , HWPfDdrPhyMr01DimmDbi =0x00D484D0 , HWPfDdrPhyMr23Dimm =0x00D484E0 , HWPfDdrPhyMr45Dimm =0x00D484F0 , HWPfDdrPhyMr67Dimm =0x00D48500 , HWPfDdrPhyWrlvlWwRdlvlRr =0x00D48510 , - HWPfDdrPhyOdtEn =0x00D48520 , - HWPfDdrPhyFastTrng =0x00D48530 , - HWPfDdrPhyDynTrngGap =0x00D48540 , - HWPfDdrPhyDynRcalGap =0x00D48550 , HWPfDdrPhyIdletimeout =0x00D48560 , - HWPfDdrPhyRstCkeGap =0x00D48570 , - HWPfDdrPhyCkeMrsGap =0x00D48580 , - HWPfDdrPhyMemVrefMidVal =0x00D48590 , - HWPfDdrPhyVrefStep =0x00D485A0 , - HWPfDdrPhyVrefThreshold =0x00D485B0 , - HWPfDdrPhyPhyVrefMidVal =0x00D485C0 , HWPfDdrPhyDqsCountMax =0x00D485D0 , HWPfDdrPhyDqsCountNum =0x00D485E0 , - HWPfDdrPhyDramRow =0x00D485F0 , - HWPfDdrPhyDramCol =0x00D48600 , - HWPfDdrPhyDramBgBa =0x00D48610 , - HWPfDdrPhyDynamicUpdreqrel =0x00D48620 , - HWPfDdrPhyVrefLimits =0x00D48630 , - HWPfDdrPhyIdtmTcStatus =0x00D6C020 , HWPfDdrPhyIdtmFwVersion =0x00D6C410 , - HWPfDdrPhyRdlvlGateInitDelay =0x00D70000 , - HWPfDdrPhyRdenSmplabc =0x00D70008 , - HWPfDdrPhyVrefNibble0 =0x00D7000C , - HWPfDdrPhyVrefNibble1 =0x00D70010 , - HWPfDdrPhyRdlvlGateDqsSmpl0 =0x00D70014 , - HWPfDdrPhyRdlvlGateDqsSmpl1 =0x00D70018 , - HWPfDdrPhyRdlvlGateDqsSmpl2 =0x00D7001C , HWPfDdrPhyDqsCount =0x00D70020 , - HWPfDdrPhyWrlvlRdlvlGateStatus =0x00D70024 , - HWPfDdrPhyErrorFlags =0x00D70028 , - HWPfDdrPhyPowerDown =0x00D70030 , - HWPfDdrPhyPrbsSeedByte0 =0x00D70034 , - HWPfDdrPhyPrbsSeedByte1 =0x00D70038 , - HWPfDdrPhyPcompDq =0x00D70040 , - HWPfDdrPhyNcompDq =0x00D70044 , - HWPfDdrPhyPcompDqs =0x00D70048 , - HWPfDdrPhyNcompDqs =0x00D7004C , - HWPfDdrPhyPcompCmd =0x00D70050 , - HWPfDdrPhyNcompCmd =0x00D70054 , - HWPfDdrPhyPcompCk =0x00D70058 , - HWPfDdrPhyNcompCk =0x00D7005C , - HWPfDdrPhyRcalOdtDq =0x00D70060 , - HWPfDdrPhyRcalOdtDqs =0x00D70064 , - HWPfDdrPhyRcalMask1 =0x00D70068 , - HWPfDdrPhyRcalMask2 =0x00D7006C , - HWPfDdrPhyRcalCtrl =0x00D70070 , - HWPfDdrPhyRcalCnt =0x00D70074 , - HWPfDdrPhyRcalOverride =0x00D70078 , - HWPfDdrPhyRcalGateen =0x00D7007C , - HWPfDdrPhyCtrl =0x00D70080 , - HWPfDdrPhyWrlvlAlg =0x00D70084 , - HWPfDdrPhyRcalVreftTxcmdOdt =0x00D70088 , - HWPfDdrPhyRdlvlGateParam =0x00D7008C , - HWPfDdrPhyRdlvlGateParam2 =0x00D70090 , - HWPfDdrPhyRcalVreftTxdata =0x00D70094 , - HWPfDdrPhyCmdIntDelay =0x00D700A4 , - HWPfDdrPhyAlertN =0x00D700A8 , - HWPfDdrPhyTrngReqWpre2tck =0x00D700AC , - HWPfDdrPhyCmdPhaseSel =0x00D700B4 , - HWPfDdrPhyCmdDcdl =0x00D700B8 , - HWPfDdrPhyCkDcdl =0x00D700BC , - HWPfDdrPhySwTrngCtrl1 =0x00D700C0 , - HWPfDdrPhySwTrngCtrl2 =0x00D700C4 , - HWPfDdrPhyRcalPcompRden =0x00D700C8 , - HWPfDdrPhyRcalNcompRden =0x00D700CC , - HWPfDdrPhyRcalCompen =0x00D700D0 , - HWPfDdrPhySwTrngRdqs =0x00D700D4 , - HWPfDdrPhySwTrngWdqs =0x00D700D8 , - HWPfDdrPhySwTrngRdena =0x00D700DC , - HWPfDdrPhySwTrngRdenb =0x00D700E0 , - HWPfDdrPhySwTrngRdenc =0x00D700E4 , - HWPfDdrPhySwTrngWdq =0x00D700E8 , - HWPfDdrPhySwTrngRdq =0x00D700EC , - HWPfDdrPhyPcfgHmValue =0x00D700F0 , - HWPfDdrPhyPcfgTimerValue =0x00D700F4 , - HWPfDdrPhyPcfgSoftwareTraining =0x00D700F8 , - HWPfDdrPhyPcfgMcStatus =0x00D700FC , - HWPfDdrPhyWrlvlPhRank0 =0x00D70100 , - HWPfDdrPhyRdenPhRank0 =0x00D70104 , - HWPfDdrPhyRdenIntRank0 =0x00D70108 , - HWPfDdrPhyRdqsDcdlRank0 =0x00D7010C , - HWPfDdrPhyRdqsShadowDcdlRank0 =0x00D70110 , - HWPfDdrPhyWdqsDcdlRank0 =0x00D70114 , - HWPfDdrPhyWdmDcdlShadowRank0 =0x00D70118 , - HWPfDdrPhyWdmDcdlRank0 =0x00D7011C , - HWPfDdrPhyDbiDcdlRank0 =0x00D70120 , - HWPfDdrPhyRdenDcdlaRank0 =0x00D70124 , - HWPfDdrPhyDbiDcdlShadowRank0 =0x00D70128 , - HWPfDdrPhyRdenDcdlbRank0 =0x00D7012C , - HWPfDdrPhyWdqsShadowDcdlRank0 =0x00D70130 , - HWPfDdrPhyRdenDcdlcRank0 =0x00D70134 , - HWPfDdrPhyRdenShadowDcdlaRank0 =0x00D70138 , - HWPfDdrPhyWrlvlIntRank0 =0x00D7013C , - HWPfDdrPhyRdqDcdlBit0Rank0 =0x00D70200 , - HWPfDdrPhyRdqDcdlShadowBit0Rank0 =0x00D70204 , - HWPfDdrPhyWdqDcdlBit0Rank0 =0x00D70208 , - HWPfDdrPhyWdqDcdlShadowBit0Rank0 =0x00D7020C , - HWPfDdrPhyRdqDcdlBit1Rank0 =0x00D70240 , - HWPfDdrPhyRdqDcdlShadowBit1Rank0 =0x00D70244 , - HWPfDdrPhyWdqDcdlBit1Rank0 =0x00D70248 , - HWPfDdrPhyWdqDcdlShadowBit1Rank0 =0x00D7024C , - HWPfDdrPhyRdqDcdlBit2Rank0 =0x00D70280 , - HWPfDdrPhyRdqDcdlShadowBit2Rank0 =0x00D70284 , - HWPfDdrPhyWdqDcdlBit2Rank0 =0x00D70288 , - HWPfDdrPhyWdqDcdlShadowBit2Rank0 =0x00D7028C , - HWPfDdrPhyRdqDcdlBit3Rank0 =0x00D702C0 , - HWPfDdrPhyRdqDcdlShadowBit3Rank0 =0x00D702C4 , - HWPfDdrPhyWdqDcdlBit3Rank0 =0x00D702C8 , - HWPfDdrPhyWdqDcdlShadowBit3Rank0 =0x00D702CC , - HWPfDdrPhyRdqDcdlBit4Rank0 =0x00D70300 , - HWPfDdrPhyRdqDcdlShadowBit4Rank0 =0x00D70304 , - HWPfDdrPhyWdqDcdlBit4Rank0 =0x00D70308 , - HWPfDdrPhyWdqDcdlShadowBit4Rank0 =0x00D7030C , - HWPfDdrPhyRdqDcdlBit5Rank0 =0x00D70340 , - HWPfDdrPhyRdqDcdlShadowBit5Rank0 =0x00D70344 , - HWPfDdrPhyWdqDcdlBit5Rank0 =0x00D70348 , - HWPfDdrPhyWdqDcdlShadowBit5Rank0 =0x00D7034C , - HWPfDdrPhyRdqDcdlBit6Rank0 =0x00D70380 , - HWPfDdrPhyRdqDcdlShadowBit6Rank0 =0x00D70384 , - HWPfDdrPhyWdqDcdlBit6Rank0 =0x00D70388 , - HWPfDdrPhyWdqDcdlShadowBit6Rank0 =0x00D7038C , - HWPfDdrPhyRdqDcdlBit7Rank0 =0x00D703C0 , - HWPfDdrPhyRdqDcdlShadowBit7Rank0 =0x00D703C4 , - HWPfDdrPhyWdqDcdlBit7Rank0 =0x00D703C8 , - HWPfDdrPhyWdqDcdlShadowBit7Rank0 =0x00D703CC , - HWPfDdrPhyIdtmStatus =0x00D740D0 , - HWPfDdrPhyIdtmError =0x00D74110 , - HWPfDdrPhyIdtmDebug =0x00D74120 , - HWPfDdrPhyIdtmDebugInt =0x00D74130 , - HwPfPcieLnAsicCfgovr =0x00D80000 , - HwPfPcieLnAclkmixer =0x00D80004 , - HwPfPcieLnTxrampfreq =0x00D80008 , - HwPfPcieLnLanetest =0x00D8000C , - HwPfPcieLnDcctrl =0x00D80010 , - HwPfPcieLnDccmeas =0x00D80014 , - HwPfPcieLnDccovrAclk =0x00D80018 , - HwPfPcieLnDccovrTxa =0x00D8001C , - HwPfPcieLnDccovrTxk =0x00D80020 , - HwPfPcieLnDccovrDclk =0x00D80024 , - HwPfPcieLnDccovrEclk =0x00D80028 , - HwPfPcieLnDcctrimAclk =0x00D8002C , - HwPfPcieLnDcctrimTx =0x00D80030 , - HwPfPcieLnDcctrimDclk =0x00D80034 , - HwPfPcieLnDcctrimEclk =0x00D80038 , - HwPfPcieLnQuadCtrl =0x00D8003C , - HwPfPcieLnQuadCorrIndex =0x00D80040 , - HwPfPcieLnQuadCorrStatus =0x00D80044 , - HwPfPcieLnAsicRxovr1 =0x00D80048 , - HwPfPcieLnAsicRxovr2 =0x00D8004C , - HwPfPcieLnAsicEqinfovr =0x00D80050 , - HwPfPcieLnRxcsr =0x00D80054 , - HwPfPcieLnRxfectrl =0x00D80058 , - HwPfPcieLnRxtest =0x00D8005C , - HwPfPcieLnEscount =0x00D80060 , - HwPfPcieLnCdrctrl =0x00D80064 , - HwPfPcieLnCdrctrl2 =0x00D80068 , - HwPfPcieLnCdrcfg0Ctrl0 =0x00D8006C , - HwPfPcieLnCdrcfg0Ctrl1 =0x00D80070 , - HwPfPcieLnCdrcfg0Ctrl2 =0x00D80074 , - HwPfPcieLnCdrcfg1Ctrl0 =0x00D80078 , - HwPfPcieLnCdrcfg1Ctrl1 =0x00D8007C , - HwPfPcieLnCdrcfg1Ctrl2 =0x00D80080 , - HwPfPcieLnCdrcfg2Ctrl0 =0x00D80084 , - HwPfPcieLnCdrcfg2Ctrl1 =0x00D80088 , - HwPfPcieLnCdrcfg2Ctrl2 =0x00D8008C , - HwPfPcieLnCdrcfg3Ctrl0 =0x00D80090 , - HwPfPcieLnCdrcfg3Ctrl1 =0x00D80094 , - HwPfPcieLnCdrcfg3Ctrl2 =0x00D80098 , - HwPfPcieLnCdrphase =0x00D8009C , - HwPfPcieLnCdrfreq =0x00D800A0 , - HwPfPcieLnCdrstatusPhase =0x00D800A4 , - HwPfPcieLnCdrstatusFreq =0x00D800A8 , - HwPfPcieLnCdroffset =0x00D800AC , - HwPfPcieLnRxvosctl =0x00D800B0 , - HwPfPcieLnRxvosctl2 =0x00D800B4 , - HwPfPcieLnRxlosctl =0x00D800B8 , - HwPfPcieLnRxlos =0x00D800BC , - HwPfPcieLnRxlosvval =0x00D800C0 , - HwPfPcieLnRxvosd0 =0x00D800C4 , - HwPfPcieLnRxvosd1 =0x00D800C8 , - HwPfPcieLnRxvosep0 =0x00D800CC , - HwPfPcieLnRxvosep1 =0x00D800D0 , - HwPfPcieLnRxvosen0 =0x00D800D4 , - HwPfPcieLnRxvosen1 =0x00D800D8 , - HwPfPcieLnRxvosafe =0x00D800DC , - HwPfPcieLnRxvosa0 =0x00D800E0 , - HwPfPcieLnRxvosa0Out =0x00D800E4 , - HwPfPcieLnRxvosa1 =0x00D800E8 , - HwPfPcieLnRxvosa1Out =0x00D800EC , - HwPfPcieLnRxmisc =0x00D800F0 , - HwPfPcieLnRxbeacon =0x00D800F4 , - HwPfPcieLnRxdssout =0x00D800F8 , - HwPfPcieLnRxdssout2 =0x00D800FC , - HwPfPcieLnAlphapctrl =0x00D80100 , - HwPfPcieLnAlphanctrl =0x00D80104 , HwPfPcieLnAdaptctrl =0x00D80108 , - HwPfPcieLnAdaptctrl1 =0x00D8010C , - HwPfPcieLnAdaptstatus =0x00D80110 , - HwPfPcieLnAdaptvga1 =0x00D80114 , - HwPfPcieLnAdaptvga2 =0x00D80118 , - HwPfPcieLnAdaptvga3 =0x00D8011C , - HwPfPcieLnAdaptvga4 =0x00D80120 , - HwPfPcieLnAdaptboost1 =0x00D80124 , - HwPfPcieLnAdaptboost2 =0x00D80128 , - HwPfPcieLnAdaptboost3 =0x00D8012C , - HwPfPcieLnAdaptboost4 =0x00D80130 , - HwPfPcieLnAdaptsslms1 =0x00D80134 , - HwPfPcieLnAdaptsslms2 =0x00D80138 , - HwPfPcieLnAdaptvgaStatus =0x00D8013C , - HwPfPcieLnAdaptboostStatus =0x00D80140 , - HwPfPcieLnAdaptsslmsStatus1 =0x00D80144 , - HwPfPcieLnAdaptsslmsStatus2 =0x00D80148 , - HwPfPcieLnAfectrl1 =0x00D8014C , - HwPfPcieLnAfectrl2 =0x00D80150 , - HwPfPcieLnAfectrl3 =0x00D80154 , - HwPfPcieLnAfedefault1 =0x00D80158 , - HwPfPcieLnAfedefault2 =0x00D8015C , - HwPfPcieLnDfectrl1 =0x00D80160 , - HwPfPcieLnDfectrl2 =0x00D80164 , - HwPfPcieLnDfectrl3 =0x00D80168 , - HwPfPcieLnDfectrl4 =0x00D8016C , - HwPfPcieLnDfectrl5 =0x00D80170 , - HwPfPcieLnDfectrl6 =0x00D80174 , - HwPfPcieLnAfestatus1 =0x00D80178 , - HwPfPcieLnAfestatus2 =0x00D8017C , - HwPfPcieLnDfestatus1 =0x00D80180 , - HwPfPcieLnDfestatus2 =0x00D80184 , - HwPfPcieLnDfestatus3 =0x00D80188 , - HwPfPcieLnDfestatus4 =0x00D8018C , - HwPfPcieLnDfestatus5 =0x00D80190 , - HwPfPcieLnAlphastatus =0x00D80194 , - HwPfPcieLnFomctrl1 =0x00D80198 , - HwPfPcieLnFomctrl2 =0x00D8019C , - HwPfPcieLnFomctrl3 =0x00D801A0 , - HwPfPcieLnAclkcalStatus =0x00D801A4 , - HwPfPcieLnOffscorrStatus =0x00D801A8 , - HwPfPcieLnEyewidthStatus =0x00D801AC , - HwPfPcieLnEyeheightStatus =0x00D801B0 , - HwPfPcieLnAsicTxovr1 =0x00D801B4 , - HwPfPcieLnAsicTxovr2 =0x00D801B8 , - HwPfPcieLnAsicTxovr3 =0x00D801BC , - HwPfPcieLnTxbiasadjOvr =0x00D801C0 , - HwPfPcieLnTxcsr =0x00D801C4 , - HwPfPcieLnTxtest =0x00D801C8 , - HwPfPcieLnTxtestword =0x00D801CC , - HwPfPcieLnTxtestwordHigh =0x00D801D0 , - HwPfPcieLnTxdrive =0x00D801D4 , - HwPfPcieLnMtcsLn =0x00D801D8 , - HwPfPcieLnStatsumLn =0x00D801DC , - HwPfPcieLnRcbusScratch =0x00D801E0 , - HwPfPcieLnRcbusMinorrev =0x00D801F0 , - HwPfPcieLnRcbusMajorrev =0x00D801F4 , - HwPfPcieLnRcbusBlocktype =0x00D801F8 , - HwPfPcieSupPllcsr =0x00D80800 , - HwPfPcieSupPlldiv =0x00D80804 , - HwPfPcieSupPllcal =0x00D80808 , - HwPfPcieSupPllcalsts =0x00D8080C , - HwPfPcieSupPllmeas =0x00D80810 , - HwPfPcieSupPlldactrim =0x00D80814 , - HwPfPcieSupPllbiastrim =0x00D80818 , - HwPfPcieSupPllbwtrim =0x00D8081C , - HwPfPcieSupPllcaldly =0x00D80820 , - HwPfPcieSupRefclkonpclkctrl =0x00D80824 , - HwPfPcieSupPclkdelay =0x00D80828 , - HwPfPcieSupPhyconfig =0x00D8082C , - HwPfPcieSupRcalIntf =0x00D80830 , - HwPfPcieSupAuxcsr =0x00D80834 , - HwPfPcieSupVref =0x00D80838 , - HwPfPcieSupLinkmode =0x00D8083C , - HwPfPcieSupRrefcalctl =0x00D80840 , - HwPfPcieSupRrefcal =0x00D80844 , - HwPfPcieSupRrefcaldly =0x00D80848 , - HwPfPcieSupTximpcalctl =0x00D8084C , - HwPfPcieSupTximpcal =0x00D80850 , - HwPfPcieSupTximpoffset =0x00D80854 , - HwPfPcieSupTximpcaldly =0x00D80858 , - HwPfPcieSupRximpcalctl =0x00D8085C , - HwPfPcieSupRximpcal =0x00D80860 , - HwPfPcieSupRximpoffset =0x00D80864 , - HwPfPcieSupRximpcaldly =0x00D80868 , - HwPfPcieSupFence =0x00D8086C , - HwPfPcieSupMtcs =0x00D80870 , - HwPfPcieSupStatsum =0x00D809B8 , - HwPfPciePcsDpStatus0 =0x00D81000 , - HwPfPciePcsDpControl0 =0x00D81004 , - HwPfPciePcsPmaStatusLane0 =0x00D81008 , - HwPfPciePcsPipeStatusLane0 =0x00D8100C , - HwPfPciePcsTxdeemph0Lane0 =0x00D81010 , - HwPfPciePcsTxdeemph1Lane0 =0x00D81014 , - HwPfPciePcsInternalStatusLane0 =0x00D81018 , - HwPfPciePcsDpStatus1 =0x00D8101C , - HwPfPciePcsDpControl1 =0x00D81020 , - HwPfPciePcsPmaStatusLane1 =0x00D81024 , - HwPfPciePcsPipeStatusLane1 =0x00D81028 , - HwPfPciePcsTxdeemph0Lane1 =0x00D8102C , - HwPfPciePcsTxdeemph1Lane1 =0x00D81030 , - HwPfPciePcsInternalStatusLane1 =0x00D81034 , - HwPfPciePcsDpStatus2 =0x00D81038 , - HwPfPciePcsDpControl2 =0x00D8103C , - HwPfPciePcsPmaStatusLane2 =0x00D81040 , - HwPfPciePcsPipeStatusLane2 =0x00D81044 , - HwPfPciePcsTxdeemph0Lane2 =0x00D81048 , - HwPfPciePcsTxdeemph1Lane2 =0x00D8104C , - HwPfPciePcsInternalStatusLane2 =0x00D81050 , - HwPfPciePcsDpStatus3 =0x00D81054 , - HwPfPciePcsDpControl3 =0x00D81058 , - HwPfPciePcsPmaStatusLane3 =0x00D8105C , - HwPfPciePcsPipeStatusLane3 =0x00D81060 , - HwPfPciePcsTxdeemph0Lane3 =0x00D81064 , - HwPfPciePcsTxdeemph1Lane3 =0x00D81068 , - HwPfPciePcsInternalStatusLane3 =0x00D8106C , - HwPfPciePcsEbStatus0 =0x00D81070 , - HwPfPciePcsEbStatus1 =0x00D81074 , - HwPfPciePcsEbStatus2 =0x00D81078 , - HwPfPciePcsEbStatus3 =0x00D8107C , - HwPfPciePcsPllSettingPcieG1 =0x00D81088 , - HwPfPciePcsPllSettingPcieG2 =0x00D8108C , - HwPfPciePcsPllSettingPcieG3 =0x00D81090 , - HwPfPciePcsControl =0x00D81094 , HwPfPciePcsEqControl =0x00D81098 , - HwPfPciePcsEqTimer =0x00D8109C , - HwPfPciePcsEqErrStatus =0x00D810A0 , - HwPfPciePcsEqErrCount =0x00D810A4 , - HwPfPciePcsStatus =0x00D810A8 , - HwPfPciePcsMiscRegister =0x00D810AC , - HwPfPciePcsObsControl =0x00D810B0 , - HwPfPciePcsPrbsCount0 =0x00D81200 , - HwPfPciePcsBistControl0 =0x00D81204 , - HwPfPciePcsBistStaticWord00 =0x00D81208 , - HwPfPciePcsBistStaticWord10 =0x00D8120C , - HwPfPciePcsBistStaticWord20 =0x00D81210 , - HwPfPciePcsBistStaticWord30 =0x00D81214 , - HwPfPciePcsPrbsCount1 =0x00D81220 , - HwPfPciePcsBistControl1 =0x00D81224 , - HwPfPciePcsBistStaticWord01 =0x00D81228 , - HwPfPciePcsBistStaticWord11 =0x00D8122C , - HwPfPciePcsBistStaticWord21 =0x00D81230 , - HwPfPciePcsBistStaticWord31 =0x00D81234 , - HwPfPciePcsPrbsCount2 =0x00D81240 , - HwPfPciePcsBistControl2 =0x00D81244 , - HwPfPciePcsBistStaticWord02 =0x00D81248 , - HwPfPciePcsBistStaticWord12 =0x00D8124C , - HwPfPciePcsBistStaticWord22 =0x00D81250 , - HwPfPciePcsBistStaticWord32 =0x00D81254 , - HwPfPciePcsPrbsCount3 =0x00D81260 , - HwPfPciePcsBistControl3 =0x00D81264 , - HwPfPciePcsBistStaticWord03 =0x00D81268 , - HwPfPciePcsBistStaticWord13 =0x00D8126C , - HwPfPciePcsBistStaticWord23 =0x00D81270 , - HwPfPciePcsBistStaticWord33 =0x00D81274 , - HwPfPcieGpexLtssmStateCntrl =0x00D90400 , - HwPfPcieGpexLtssmStateStatus =0x00D90404 , - HwPfPcieGpexSkipFreqTimer =0x00D90408 , - HwPfPcieGpexLaneSelect =0x00D9040C , - HwPfPcieGpexLaneDeskew =0x00D90410 , - HwPfPcieGpexRxErrorStatus =0x00D90414 , - HwPfPcieGpexLaneNumControl =0x00D90418 , - HwPfPcieGpexNFstControl =0x00D9041C , - HwPfPcieGpexLinkStatus =0x00D90420 , - HwPfPcieGpexAckReplayTimeout =0x00D90438 , - HwPfPcieGpexSeqNumberStatus =0x00D9043C , - HwPfPcieGpexCoreClkRatio =0x00D90440 , - HwPfPcieGpexDllTholdControl =0x00D90448 , - HwPfPcieGpexPmTimer =0x00D90450 , - HwPfPcieGpexPmeTimeout =0x00D90454 , - HwPfPcieGpexAspmL1Timer =0x00D90458 , - HwPfPcieGpexAspmReqTimer =0x00D9045C , - HwPfPcieGpexAspmL1Dis =0x00D90460 , - HwPfPcieGpexAdvisoryErrorControl =0x00D90468 , - HwPfPcieGpexId =0x00D90470 , - HwPfPcieGpexClasscode =0x00D90474 , - HwPfPcieGpexSubsystemId =0x00D90478 , - HwPfPcieGpexDeviceCapabilities =0x00D9047C , - HwPfPcieGpexLinkCapabilities =0x00D90480 , - HwPfPcieGpexFunctionNumber =0x00D90484 , - HwPfPcieGpexPmCapabilities =0x00D90488 , - HwPfPcieGpexFunctionSelect =0x00D9048C , - HwPfPcieGpexErrorCounter =0x00D904AC , - HwPfPcieGpexConfigReady =0x00D904B0 , - HwPfPcieGpexFcUpdateTimeout =0x00D904B8 , - HwPfPcieGpexFcUpdateTimer =0x00D904BC , - HwPfPcieGpexVcBufferLoad =0x00D904C8 , - HwPfPcieGpexVcBufferSizeThold =0x00D904CC , - HwPfPcieGpexVcBufferSelect =0x00D904D0 , - HwPfPcieGpexBarEnable =0x00D904D4 , - HwPfPcieGpexBarDwordLower =0x00D904D8 , - HwPfPcieGpexBarDwordUpper =0x00D904DC , - HwPfPcieGpexBarSelect =0x00D904E0 , - HwPfPcieGpexCreditCounterSelect =0x00D904E4 , - HwPfPcieGpexCreditCounterStatus =0x00D904E8 , - HwPfPcieGpexTlpHeaderSelect =0x00D904EC , - HwPfPcieGpexTlpHeaderDword0 =0x00D904F0 , - HwPfPcieGpexTlpHeaderDword1 =0x00D904F4 , - HwPfPcieGpexTlpHeaderDword2 =0x00D904F8 , - HwPfPcieGpexTlpHeaderDword3 =0x00D904FC , - HwPfPcieGpexRelaxOrderControl =0x00D90500 , - HwPfPcieGpexBarPrefetch =0x00D90504 , - HwPfPcieGpexFcCheckControl =0x00D90508 , - HwPfPcieGpexFcUpdateTimerTraffic =0x00D90518 , - HwPfPcieGpexPhyControl0 =0x00D9053C , - HwPfPcieGpexPhyControl1 =0x00D90544 , - HwPfPcieGpexPhyControl2 =0x00D9054C , - HwPfPcieGpexUserControl0 =0x00D9055C , - HwPfPcieGpexUncorrErrorStatus =0x00D905F0 , - HwPfPcieGpexRxCplError =0x00D90620 , - HwPfPcieGpexRxCplErrorDword0 =0x00D90624 , - HwPfPcieGpexRxCplErrorDword1 =0x00D90628 , - HwPfPcieGpexRxCplErrorDword2 =0x00D9062C , - HwPfPcieGpexPabSwResetEn =0x00D90630 , - HwPfPcieGpexGen3Control0 =0x00D90634 , - HwPfPcieGpexGen3Control1 =0x00D90638 , - HwPfPcieGpexGen3Control2 =0x00D9063C , - HwPfPcieGpexGen2ControlCsr =0x00D90640 , - HwPfPcieGpexTotalVfInitialVf0 =0x00D90644 , - HwPfPcieGpexTotalVfInitialVf1 =0x00D90648 , - HwPfPcieGpexSriovLinkDevId0 =0x00D90684 , - HwPfPcieGpexSriovLinkDevId1 =0x00D90688 , - HwPfPcieGpexSriovPageSize0 =0x00D906C4 , - HwPfPcieGpexSriovPageSize1 =0x00D906C8 , - HwPfPcieGpexIdVersion =0x00D906FC , - HwPfPcieGpexSriovVfOffsetStride0 =0x00D90704 , - HwPfPcieGpexSriovVfOffsetStride1 =0x00D90708 , - HwPfPcieGpexGen3DeskewControl =0x00D907B4 , - HwPfPcieGpexGen3EqControl =0x00D907B8 , - HwPfPcieGpexBridgeVersion =0x00D90800 , - HwPfPcieGpexBridgeCapability =0x00D90804 , HwPfPcieGpexBridgeControl =0x00D90808 , - HwPfPcieGpexBridgeStatus =0x00D9080C , - HwPfPcieGpexEngineActivityStatus =0x00D9081C , - HwPfPcieGpexEngineResetControl =0x00D90820 , HwPfPcieGpexAxiPioControl =0x00D90840 , - HwPfPcieGpexAxiPioStatus =0x00D90844 , - HwPfPcieGpexAmbaSlaveCmdStatus =0x00D90848 , - HwPfPcieGpexPexPioControl =0x00D908C0 , - HwPfPcieGpexPexPioStatus =0x00D908C4 , - HwPfPcieGpexAmbaMasterStatus =0x00D908C8 , - HwPfPcieGpexCsrSlaveCmdStatus =0x00D90920 , - HwPfPcieGpexMailboxAxiControl =0x00D90A50 , - HwPfPcieGpexMailboxAxiData =0x00D90A54 , - HwPfPcieGpexMailboxPexControl =0x00D90A90 , - HwPfPcieGpexMailboxPexData =0x00D90A94 , - HwPfPcieGpexPexInterruptEnable =0x00D90AD0 , - HwPfPcieGpexPexInterruptStatus =0x00D90AD4 , - HwPfPcieGpexPexInterruptAxiPioVector =0x00D90AD8 , - HwPfPcieGpexPexInterruptPexPioVector =0x00D90AE0 , - HwPfPcieGpexPexInterruptMiscVector =0x00D90AF8 , - HwPfPcieGpexAmbaInterruptPioEnable =0x00D90B00 , - HwPfPcieGpexAmbaInterruptMiscEnable =0x00D90B0C , - HwPfPcieGpexAmbaInterruptPioStatus =0x00D90B10 , - HwPfPcieGpexAmbaInterruptMiscStatus =0x00D90B1C , - HwPfPcieGpexPexPmControl =0x00D90B80 , - HwPfPcieGpexSlotMisc =0x00D90B88 , - HwPfPcieGpexAxiAddrMappingControl =0x00D90BA0 , - HwPfPcieGpexAxiAddrMappingWindowAxiBase =0x00D90BA4 , - HwPfPcieGpexAxiAddrMappingWindowPexBaseLow =0x00D90BA8 , HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh = 0x00D90BAC, - HwPfPcieGpexPexBarAddrFunc0Bar0 =0x00D91BA0 , - HwPfPcieGpexPexBarAddrFunc0Bar1 =0x00D91BA4 , - HwPfPcieGpexAxiAddrMappingPcieHdrParam =0x00D95BA0 , - HwPfPcieGpexExtAxiAddrMappingAxiBase =0x00D980A0 , - HwPfPcieGpexPexExtBarAddrFunc0Bar0 =0x00D984A0 , - HwPfPcieGpexPexExtBarAddrFunc0Bar1 =0x00D984A4 , - HwPfPcieGpexAmbaInterruptFlrEnable =0x00D9B960 , - HwPfPcieGpexAmbaInterruptFlrStatus =0x00D9B9A0 , - HwPfPcieGpexExtAxiAddrMappingSize =0x00D9BAF0 , - HwPfPcieGpexPexPioAwcacheControl =0x00D9C300 , - HwPfPcieGpexPexPioArcacheControl =0x00D9C304 , - HwPfPcieGpexPabObSizeControlVc0 =0x00D9C310 };/* TIP PF Interrupt numbers */
Signature · 1 line
2.37.1
PATCH v8 2/14 baseband/acc100: refactor to segregate common code
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Refactored shareable common code to be used by future PMD (including ACC200 in this patchset) and
following PMDs in roadmap) by gathering such structures or inline methods. No functionality change.
Signed-off-by Nic Chautru <[email protected]>
Acked-by Bruce Richardson <[email protected]>
Reviewed-by Maxime Coquelin <[email protected]>
--- app/test-bbdev/test_bbdev_perf.c | 6 +- drivers/baseband/acc100/acc100_pmd.h | 449 +---- drivers/baseband/acc100/acc101_pmd.h | 10 - drivers/baseband/acc100/acc_common.h | 1304 +++++++++++++ drivers/baseband/acc100/rte_acc100_cfg.h | 70 +- drivers/baseband/acc100/rte_acc100_pmd.c | 1773 ++++++------------ drivers/baseband/acc100/rte_acc_common_cfg.h | 101 + 7 files changed, 1982 insertions(+), 1731 deletions(-) create mode 100644 drivers/baseband/acc100/acc_common.h create mode 100644 drivers/baseband/acc100/rte_acc_common_cfg.h
app/test-bbdev/test_bbdev_perf.c +3 -3
@@ -709,18 +709,18 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info,#ifdef RTE_BASEBAND_ACC100 if ((get_init_device () == true) && (!strcmp (info->drv.driver_name,ACC100PF_DRIVER_NAME ))) { -struct rte_acc100_conf conf; +struct rte_acc_conf conf;unsigned int i;printf ("Configure ACC100/ACC101 FEC Driver %s with default values\n" , info->drv.driver_name);/* clear default configuration before initialization */ -memset (&conf,0 ,sizeof (struct rte_acc100_conf )); +memset (&conf,0 ,sizeof (struct rte_acc_conf ));/* Always set in PF mode for built-in configuration */ conf.pf_mode_en = true; -for (i =0 ; i <RTE_ACC100_NUM_VFS ; ++i) { +for (i =0 ; i <RTE_ACC_NUM_VFS ; ++i) { conf.arb_dl_4g[i].gbr_threshold1 =ACC100_QOS_GBR ; conf.arb_dl_4g[i].gbr_threshold1 =ACC100_QOS_GBR ; conf.arb_dl_4g[i].round_robin_weight =ACC100_QMGR_RR ;
drivers/baseband/acc100/acc100_pmd.h +1 -448
505 lines not on this page · raw message
drivers/baseband/acc100/acc101_pmd.h +0 -10
@@ -11,16 +11,9 @@#define ACC101_NUM_VFS 16#define ACC101_NUM_QGRPS 8#define ACC101_NUM_AQS 16 -/* All ACC101 Registers alignment are 32bits = 4B */ -#define ACC101_BYTES_IN_WORD 4 -#define ACC101_TMPL_PRI_0 0x03020100 -#define ACC101_TMPL_PRI_1 0x07060504 -#define ACC101_TMPL_PRI_2 0x0b0a0908 -#define ACC101_TMPL_PRI_3 0x0f0e0d0c#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4) -#define ACC101_NUM_TMPL 32/* Mapping of signals for the available engines */ #define ACC101_SIG_UL_5G 0#define ACC101_SIG_UL_5G_LAST 8
@@ -31,7 +24,6 @@#define ACC101_SIG_DL_4G 27#define ACC101_SIG_DL_4G_LAST 31#define ACC101_NUM_ACCS 5 -#define ACC101_PF_VAL 2/* ACC101 Configuration */ #define ACC101_CFG_DMA_ERROR 0x3D7
@@ -39,8 +31,6 @@#define ACC101_CFG_QMGR_HI_P 0x0F0F#define ACC101_CFG_PCI_AXI 0xC003#define ACC101_CFG_PCI_BRIDGE 0x40006033 -#define ACC101_ENGINE_OFFSET 0x1000 -#define ACC101_LONG_WAIT 1000#define ACC101_GPEX_AXIMAP_NUM 17#define ACC101_CLOCK_GATING_EN 0x30000#define ACC101_DMA_INBOUND 0x104
drivers/baseband/acc100/acc_common.h new file +1304 -0
1,304 lines not on this page · raw message
drivers/baseband/acc100/rte_acc100_cfg.h +3 -67
91 lines not on this page · raw message
drivers/baseband/acc100/rte_acc100_pmd.c +570 -1203
1,048 lines not on this page · raw message
drivers/baseband/acc100/rte_acc_common_cfg.h new file +101 -0
101 lines not on this page · raw message
The rest of this diff is not shown. View the raw message.
Signature · 1 line
2.37.1
Part of the diff is not shown here. View the raw message.
PATCH v8 3/14 baseband/acc: rename directory from acc100 to acc
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Used a common directory for the ACC PMDs
Signed-off-by Nic Chautru <[email protected]>
Reviewed-by Maxime Coquelin <[email protected]>
---
MAINTAINERS | 2 +-
app/test-bbdev/meson.build | 4 ++--
app/test-bbdev/test_bbdev_perf.c | 4 ++--
drivers/baseband/{acc100 => acc}/acc100_pf_enum.h | 0
drivers/baseband/{acc100 => acc}/acc100_pmd.h | 0
drivers/baseband/{acc100 => acc}/acc100_vf_enum.h | 0
drivers/baseband/{acc100 => acc}/acc101_pmd.h | 0
drivers/baseband/{acc100 => acc}/acc_common.h | 0
drivers/baseband/{acc100 => acc}/meson.build | 0
drivers/baseband/{acc100 => acc}/rte_acc100_cfg.h | 0
drivers/baseband/{acc100 => acc}/rte_acc100_pmd.c | 0
drivers/baseband/{acc100 => acc}/rte_acc_common_cfg.h | 0
drivers/baseband/{acc100 => acc}/version.map | 0
drivers/baseband/meson.build | 2 +-
14 files changed, 6 insertions(+), 6 deletions(-)
rename drivers/baseband/{acc100 => acc}/acc100_pf_enum.h (100%)
rename drivers/baseband/{acc100 => acc}/acc100_pmd.h (100%)
rename drivers/baseband/{acc100 => acc}/acc100_vf_enum.h (100%)
rename drivers/baseband/{acc100 => acc}/acc101_pmd.h (100%)
rename drivers/baseband/{acc100 => acc}/acc_common.h (100%)
rename drivers/baseband/{acc100 => acc}/meson.build (100%)
rename drivers/baseband/{acc100 => acc}/rte_acc100_cfg.h (100%)
rename drivers/baseband/{acc100 => acc}/rte_acc100_pmd.c (100%)
rename drivers/baseband/{acc100 => acc}/rte_acc_common_cfg.h (100%)
rename drivers/baseband/{acc100 => acc}/version.map (100%)MAINTAINERS +1 -1
@@ -1339,7 +1339,7 @@ F: doc/guides/bbdevs/features/fpga_lte_fec.ini F: drivers/baseband/fpga_5gnr_fec/ F: doc/guides/bbdevs/fpga_5gnr_fec.rst F: doc/guides/bbdevs/features/fpga_5gnr_fec.ini -F: drivers/baseband/acc100/ +F: drivers/baseband/acc/ F: doc/guides/bbdevs/acc100.rst F: doc/guides/bbdevs/features/acc100.ini F: doc/guides/bbdevs/features/acc101.ini
app/test-bbdev/meson.build +2 -2
@@ -20,8 +20,8 @@ endif if dpdk_conf.has('RTE_BASEBAND_FPGA_5GNR_FEC') deps += ['baseband_fpga_5gnr_fec'] endif -if dpdk_conf.has('RTE_BASEBAND_ACC100') - deps += ['baseband_acc100'] +if dpdk_conf.has('RTE_BASEBAND_ACC') + deps += ['baseband_acc'] endif if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_LA12XX') deps += ['baseband_la12xx']
app/test-bbdev/test_bbdev_perf.c +2 -2
@@ -53,7 +53,7 @@#define DL_5G_LOAD_BALANCE 128#endif -#ifdef RTE_BASEBAND_ACC100 +#ifdef RTE_BASEBAND_ACC #include <rte_acc100_cfg.h> #define ACC100PF_DRIVER_NAME ("intel_acc100_pf")#define ACC100VF_DRIVER_NAME ("intel_acc100_vf")
@@ -706,7 +706,7 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info, info->dev_name); }#endif -#ifdef RTE_BASEBAND_ACC100 +#ifdef RTE_BASEBAND_ACC if ((get_init_device () == true) && (!strcmp (info->drv.driver_name,ACC100PF_DRIVER_NAME ))) {struct rte_acc_conf conf;
drivers/baseband/acc/acc100_pf_enum.h renamed from drivers/baseband/acc100/acc100_pf_enum.h +0 -0
drivers/baseband/acc/acc100_pmd.h renamed from drivers/baseband/acc100/acc100_pmd.h +0 -0
drivers/baseband/acc/acc100_vf_enum.h renamed from drivers/baseband/acc100/acc100_vf_enum.h +0 -0
drivers/baseband/acc/acc101_pmd.h renamed from drivers/baseband/acc100/acc101_pmd.h +0 -0
drivers/baseband/acc/acc_common.h renamed from drivers/baseband/acc100/acc_common.h +0 -0
drivers/baseband/acc/meson.build renamed from drivers/baseband/acc100/meson.build +0 -0
drivers/baseband/acc/rte_acc100_cfg.h renamed from drivers/baseband/acc100/rte_acc100_cfg.h +0 -0
drivers/baseband/acc/rte_acc100_pmd.c renamed from drivers/baseband/acc100/rte_acc100_pmd.c +0 -0
drivers/baseband/acc/rte_acc_common_cfg.h renamed from drivers/baseband/acc100/rte_acc_common_cfg.h +0 -0
drivers/baseband/acc/version.map renamed from drivers/baseband/acc100/version.map +0 -0
drivers/baseband/meson.build +1 -1
@@ -6,7 +6,7 @@ if is_windows endif drivers = [ - 'acc100', + 'acc', 'fpga_5gnr_fec', 'fpga_lte_fec', 'la12xx',
Signature · 1 line
2.37.1
PATCH v8 4/14 baseband/acc: introduce PMD for ACC200
In reply to Nicolas ChautruIntroduced stubs for device driver for the ACC200
integrated VRAN accelerator on SPR-EEC
Signed-off-by Nicolas Chautru <[email protected]>
Reviewed-by Maxime Coquelin <[email protected]>
--- MAINTAINERS | 3 + doc/guides/bbdevs/acc200.rst | 257 +++++++++++++++++++++++++ doc/guides/bbdevs/features/acc200.ini | 14 ++ doc/guides/bbdevs/features/default.ini | 1 + doc/guides/bbdevs/index.rst | 1 + doc/guides/rel_notes/release_22_11.rst | 6 + drivers/baseband/acc/acc200_pmd.h | 32 +++ drivers/baseband/acc/meson.build | 2 +- drivers/baseband/acc/rte_acc200_pmd.c | 143 ++++++++++++++ 9 files changed, 458 insertions(+), 1 deletion(-) create mode 100644 doc/guides/bbdevs/acc200.rst create mode 100644 doc/guides/bbdevs/features/acc200.ini create mode 100644 drivers/baseband/acc/acc200_pmd.h create mode 100644 drivers/baseband/acc/rte_acc200_pmd.c
MAINTAINERS +3 -0
@@ -1343,6 +1343,9 @@ F: drivers/baseband/acc/ F: doc/guides/bbdevs/acc100.rst F: doc/guides/bbdevs/features/acc100.ini F: doc/guides/bbdevs/features/acc101.ini +F: drivers/baseband/acc200/ +F: doc/guides/bbdevs/acc200.rst +F: doc/guides/bbdevs/features/acc200.ini Null baseband M: Nicolas Chautru <[email protected]>
doc/guides/bbdevs/acc200.rst new file +257 -0
257 lines not on this page · raw message
doc/guides/bbdevs/features/acc200.ini new file +14 -0
@@ -0,0 +1,14 @@ +; +; Supported features of the 'acc200' bbdev driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Turbo Decoder (4G) = Y +Turbo Encoder (4G) = Y +LDPC Decoder (5G) = Y +LDPC Encoder (5G) = Y +LLR/HARQ Compression = Y +FFT/SRS = Y +External DDR Access = N +HW Accelerated = Y
doc/guides/bbdevs/features/default.ini +1 -0
@@ -11,5 +11,6 @@ Turbo Encoder (4G) = LDPC Decoder (5G) = LDPC Encoder (5G) = LLR/HARQ Compression = +FFT/SRS = External DDR Access = HW Accelerated =
doc/guides/bbdevs/index.rst +1 -0
@@ -14,4 +14,5 @@ Baseband Device Drivers fpga_lte_fec fpga_5gnr_fec acc100 + acc200 la12xx
doc/guides/rel_notes/release_22_11.rst +6 -0
@@ -152,6 +152,12 @@ New Features into single event containing ``rte_event_vector`` whose event type is ``RTE_EVENT_TYPE_CRYPTODEV_VECTOR``. +* **Added Intel ACC200 bbdev PMD.** + + Added a new ``acc200`` bbdev driver for the Intel\ |reg| ACC200 accelerator + integrated on SPR-EE. See the + :doc:`../bbdevs/acc200` BBDEV guide for more details on this new driver. + Removed Items -------------
drivers/baseband/acc/acc200_pmd.h new file +32 -0
@@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: BSD-3-Clause +* Copyright(c) 2022 Intel Corporation +*/ + +#ifndef _RTE_ACC200_PMD_H_ +#define _RTE_ACC200_PMD_H_ + +#include "acc_common.h" + +/* Helper macro for logging */ +#define rte_bbdev_log (level, fmt, ...) \ + rte_log(RTE_LOG_ ## level, acc200_logtype, fmt "\n", \ + ##__VA_ARGS__) + +#ifdef RTE_LIBRTE_BBDEV_DEBUG +#define rte_bbdev_log_debug (fmt, ...) \ + rte_bbdev_log(DEBUG, "acc200_pmd: " fmt, \ + ##__VA_ARGS__) +#else +#define rte_bbdev_log_debug (fmt, ...) +#endif + +/* ACC200 PF and VF driver names */ +#define ACC200PF_DRIVER_NAME intel_acc200_pf +#define ACC200VF_DRIVER_NAME intel_acc200_vf + +/* ACC200 PCI vendor & device IDs */ +#define RTE_ACC200_VENDOR_ID (0x8086) +#define RTE_ACC200_PF_DEVICE_ID (0x57C0) +#define RTE_ACC200_VF_DEVICE_ID (0x57C1) + +#endif /* _RTE_ACC200_PMD_H_ */
drivers/baseband/acc/meson.build +1 -1
@@ -3,6 +3,6 @@ deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci'] -sources = files('rte_acc100_pmd.c') +sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c') headers = files('rte_acc100_cfg.h')
drivers/baseband/acc/rte_acc200_pmd.c new file +143 -0
143 lines not on this page · raw message
Signature · 1 line
2.37.1
PATCH v8 5/14 baseband/acc: add HW register definitions for ACC200
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Added registers list and structure to access the device.
Signed-off-by Nic Chautru <[email protected]>
Reviewed-by Maxime Coquelin <[email protected]>
--- drivers/baseband/acc/acc200_pf_enum.h | 108 +++++++++++++++++ drivers/baseband/acc/acc200_pmd.h | 163 ++++++++++++++++++++++++++ drivers/baseband/acc/acc200_vf_enum.h | 83 +++++++++++++ 3 files changed, 354 insertions(+) create mode 100644 drivers/baseband/acc/acc200_pf_enum.h create mode 100644 drivers/baseband/acc/acc200_vf_enum.h
drivers/baseband/acc/acc200_pf_enum.h new file +108 -0
@@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: BSD-3-Clause +* Copyright(c) 2021 Intel Corporation +*/ + +#ifndef ACC200_PF_ENUM_H +#define ACC200_PF_ENUM_H + +/* +* ACC200 Register mapping on PF BAR0 +* This is automatically generated from RDL, format may change with new RDL +* Release. +* Variable names are as is +*/ +enum { + HWPfQmgrEgressQueuesTemplate =0x0007FC00 , + HWPfQmgrIngressAq =0x00080000 , + HWPfQmgrDepthLog2Grp =0x00A00200 , + HWPfQmgrTholdGrp =0x00A00300 , + HWPfQmgrGrpTmplateReg0Indx =0x00A00600 , + HWPfQmgrGrpTmplateReg1Indx =0x00A00700 , + HWPfQmgrGrpTmplateReg2indx =0x00A00800 , + HWPfQmgrGrpTmplateReg3Indx =0x00A00900 , + HWPfQmgrGrpTmplateReg4Indx =0x00A00A00 , + HWPfQmgrVfBaseAddr =0x00A01000 , + HWPfQmgrArbQDepthGrp =0x00A02F00 , + HWPfQmgrGrpFunction0 =0x00A02F40 , + HWPfQmgrGrpFunction1 =0x00A02F44 , + HWPfQmgrGrpPriority =0x00A02F48 , + HWPfQmgrAqEnableVf =0x00A10000 , + HWPfQmgrRingSizeVf =0x00A20004 , + HWPfQmgrGrpDepthLog20Vf =0x00A20008 , + HWPfQmgrGrpDepthLog21Vf =0x00A2000C , + HWPfFabricM2iBufferReg =0x00B30000 , + HWPfFabricI2Mdma_weight =0x00B31044 , + HwPfFecUl5gIbDebugReg =0x00B40200 , + HWPfFftConfig0 =0x00B58004 , + HWPfFftRamPageAccess =0x00B5800C , + HWPfFftRamOff =0x00B58800 , + HWPfDmaConfig0Reg =0x00B80000 , + HWPfDmaConfig1Reg =0x00B80004 , + HWPfDmaQmgrAddrReg =0x00B80008 , + HWPfDmaAxcacheReg =0x00B80010 , + HWPfDmaAxiControl =0x00B8002C , + HWPfDmaQmanen =0x00B80040 , + HWPfDma4gdlIbThld =0x00B800CC , + HWPfDmaCfgRrespBresp =0x00B80814 , + HWPfDmaDescriptorSignatuture =0x00B80868 , + HWPfDmaErrorDetectionEn =0x00B80870 , + HWPfDmaFec5GulDescBaseLoRegVf =0x00B88020 , + HWPfDmaFec5GulDescBaseHiRegVf =0x00B88024 , + HWPfDmaFec5GulRespPtrLoRegVf =0x00B88028 , + HWPfDmaFec5GulRespPtrHiRegVf =0x00B8802C , + HWPfDmaFec5GdlDescBaseLoRegVf =0x00B88040 , + HWPfDmaFec5GdlDescBaseHiRegVf =0x00B88044 , + HWPfDmaFec5GdlRespPtrLoRegVf =0x00B88048 , + HWPfDmaFec5GdlRespPtrHiRegVf =0x00B8804C , + HWPfDmaFec4GulDescBaseLoRegVf =0x00B88060 , + HWPfDmaFec4GulDescBaseHiRegVf =0x00B88064 , + HWPfDmaFec4GulRespPtrLoRegVf =0x00B88068 , + HWPfDmaFec4GulRespPtrHiRegVf =0x00B8806C , + HWPfDmaFec4GdlDescBaseLoRegVf =0x00B88080 , + HWPfDmaFec4GdlDescBaseHiRegVf =0x00B88084 , + HWPfDmaFec4GdlRespPtrLoRegVf =0x00B88088 , + HWPfDmaFec4GdlRespPtrHiRegVf =0x00B8808C , + HWPDmaFftDescBaseLoRegVf =0x00B880A0 , + HWPDmaFftDescBaseHiRegVf =0x00B880A4 , + HWPDmaFftRespPtrLoRegVf =0x00B880A8 , + HWPDmaFftRespPtrHiRegVf =0x00B880AC , + HWPfQosmonAEvalOverflow0 =0x00B90008 , + HWPfPermonACntrlRegVf =0x00B98000 , + HWPfQosmonBEvalOverflow0 =0x00BA0008 , + HWPfPermonBCntrlRegVf =0x00BA8000 , + HWPfPermonCCntrlRegVf =0x00BB8000 , + HWPfHiInfoRingBaseLoRegPf =0x00C84014 , + HWPfHiInfoRingBaseHiRegPf =0x00C84018 , + HWPfHiInfoRingPointerRegPf =0x00C8401C , + HWPfHiInfoRingIntWrEnRegPf =0x00C84020 , + HWPfHiBlockTransmitOnErrorEn =0x00C84038 , + HWPfHiCfgMsiIntWrEnRegPf =0x00C84040 , + HWPfHiMsixVectorMapperPf =0x00C84060 , + HWPfHiPfMode =0x00C84108 , + HWPfHiClkGateHystReg =0x00C8410C , + HWPfHiMsiDropEnableReg =0x00C84114 , + HWPfHiSectionPowerGatingReq =0x00C84128 , + HWPfHiSectionPowerGatingAck =0x00C8412C , +}; + +/* TIP PF Interrupt numbers */ +enum { +ACC200_PF_INT_QMGR_AQ_OVERFLOW =0 , +ACC200_PF_INT_DOORBELL_VF_2_PF =1 , +ACC200_PF_INT_ILLEGAL_FORMAT =2 , +ACC200_PF_INT_QMGR_DISABLED_ACCESS =3 , +ACC200_PF_INT_QMGR_AQ_OVERTHRESHOLD =4 , +ACC200_PF_INT_DMA_DL_DESC_IRQ =5 , +ACC200_PF_INT_DMA_UL_DESC_IRQ =6 , +ACC200_PF_INT_DMA_FFT_DESC_IRQ =7 , +ACC200_PF_INT_DMA_UL5G_DESC_IRQ =8 , +ACC200_PF_INT_DMA_DL5G_DESC_IRQ =9 , +ACC200_PF_INT_DMA_MLD_DESC_IRQ =10 , +ACC200_PF_INT_ARAM_ECC_1BIT_ERR =11 , +ACC200_PF_INT_PARITY_ERR =12 , +ACC200_PF_INT_QMGR_ERR =13 , +ACC200_PF_INT_INT_REQ_OVERFLOW =14 , +ACC200_PF_INT_APB_TIMEOUT =15 , +}; + +#endif /* ACC200_PF_ENUM_H */
drivers/baseband/acc/acc200_pmd.h +163 -0
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drivers/baseband/acc/acc200_vf_enum.h new file +83 -0
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Signature · 1 line
2.37.1
PATCH v8 6/14 baseband/acc: add info get function for ACC200
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Added support for info_get to allow to query the device. Null capability exposed.
Signed-off-by Nic Chautru <[email protected]>
Reviewed-by Maxime Coquelin <[email protected]>
--- drivers/baseband/acc/acc200_pmd.h | 1 + drivers/baseband/acc/rte_acc200_pmd.c | 239 ++++++++++++++++++++++++++ 2 files changed, 240 insertions(+)
drivers/baseband/acc/acc200_pmd.h +1 -0
@@ -8,6 +8,7 @@#include "acc_common.h" #include "acc200_pf_enum.h" #include "acc200_vf_enum.h" +#include "rte_acc200_cfg.h" /* Helper macro for logging */ #define rte_bbdev_log (level, fmt, ...) \
drivers/baseband/acc/rte_acc200_pmd.c +239 -0
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Signature · 1 line
2.37.1
PATCH v8 7/14 baseband/acc: add queue configuration for ACC200
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Added function to create and configure queues for the device.
Signed-off-by Nic Chautru <[email protected]>
Reviewed-by Maxime Coquelin <[email protected]>
--- drivers/baseband/acc/acc_common.h | 1 + drivers/baseband/acc/rte_acc200_pmd.c | 391 +++++++++++++++++++++++++- 2 files changed, 391 insertions(+), 1 deletion(-)
drivers/baseband/acc/acc_common.h +1 -0
@@ -100,6 +100,7 @@#define ACC_LIMIT_DL_MUX_BITS 534#define ACC_NUM_QGRPS_PER_WORD 8#define ACC_MAX_NUM_QGRPS 32 +#define ACC_RING_SIZE_GRANULARITY 64/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ #define ACC_N_ZC_1 66/* N = 66 Zc for BG 1 */
drivers/baseband/acc/rte_acc200_pmd.c +390 -1
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Signature · 1 line
2.37.1
PATCH v8 8/14 baseband/acc: add LDPC processing functions
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Added LDPC encode and decode processing functions.
Signed-off-by Nic Chautru <[email protected]>
Reviewed-by Maxime Coquelin <[email protected]>
--- drivers/baseband/acc/acc_common.h | 84 ++ drivers/baseband/acc/rte_acc200_pmd.c | 1321 ++++++++++++++++++++++++- 2 files changed, 1400 insertions(+), 5 deletions(-)
drivers/baseband/acc/acc_common.h +84 -0
@@ -1302,4 +1302,88 @@ acc_pci_remove(struct rte_pci_device *pci_dev)return 0 ; } +static inline void +acc_enqueue_status (struct rte_bbdev_queue_data *q_data, +enum rte_bbdev_enqueue_status status) +{ + q_data->enqueue_status = status; + q_data->queue_stats.enqueue_status_count[status]++; + +rte_acc_log (WARNING ,"Enqueue Status: %s %#" PRIx64"" , +rte_bbdev_enqueue_status_str (status), + q_data->queue_stats.enqueue_status_count[status]); +} + +static inline void +acc_enqueue_invalid (struct rte_bbdev_queue_data *q_data) +{ +acc_enqueue_status (q_data,RTE_BBDEV_ENQ_STATUS_INVALID_OP ); +} + +static inline void +acc_enqueue_ring_full (struct rte_bbdev_queue_data *q_data) +{ +acc_enqueue_status (q_data,RTE_BBDEV_ENQ_STATUS_RING_FULL ); +} + +static inline void +acc_enqueue_queue_full (struct rte_bbdev_queue_data *q_data) +{ +acc_enqueue_status (q_data,RTE_BBDEV_ENQ_STATUS_QUEUE_FULL ); +} + +/* Number of available descriptor in ring to enqueue */ +static inline uint32_t +acc_ring_avail_enq (struct acc_queue *q) +{ +return (q->sw_ring_depth -1 + q->sw_ring_tail - q->sw_ring_head) & q->sw_ring_wrap_mask; +} + +/* Number of available descriptor in ring to dequeue */ +static inline uint32_t +acc_ring_avail_deq (struct acc_queue *q) +{ +return (q->sw_ring_depth + q->sw_ring_head - q->sw_ring_tail) & q->sw_ring_wrap_mask; +} + +/* Check room in AQ for the enqueues batches into Qmgr */ +static inline int32_t +acc_aq_avail (struct rte_bbdev_queue_data *q_data,uint16_t num_ops) +{ +struct acc_queue *q = q_data->queue_private; +int32_t aq_avail = q->aq_depth - + ((q->aq_enqueued - q->aq_dequeued + +ACC_MAX_QUEUE_DEPTH ) %ACC_MAX_QUEUE_DEPTH ) + - (num_ops >>7 ); +if (aq_avail <=0 ) +acc_enqueue_queue_full (q_data); +return aq_avail; +} + +/* Calculates number of CBs in processed encoder TB based on 'r' and input +* length. +*/ +static inline uint8_t +get_num_cbs_in_tb_ldpc_enc (struct rte_bbdev_op_ldpc_enc *ldpc_enc) +{ +uint8_t c, r, crc24_bits =0 ; +uint16_t k = (ldpc_enc->basegraph ==1 ?22 :10 ) * ldpc_enc->z_c + - ldpc_enc->n_filler; +uint8_t cbs_in_tb =0 ; +int32_t length; + + length = ldpc_enc->input.length; + r = ldpc_enc->tb_params.r; + c = ldpc_enc->tb_params.c; + crc24_bits =0 ; +if (check_bit (ldpc_enc->op_flags,RTE_BBDEV_LDPC_CRC_24B_ATTACH )) + crc24_bits =24 ; +while (length >0 && r < c) { + length -= (k - crc24_bits) >>3 ; + r++; + cbs_in_tb++; + } +return cbs_in_tb; +} +#endif /* _ACC_COMMON_H_ */
drivers/baseband/acc/rte_acc200_pmd.c +1316 -5
1,363 lines not on this page · raw message
Signature · 1 line
2.37.1
PATCH v8 9/14 baseband/acc: add LTE processing functions
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Added functions and capability for 4G FEC
Signed-off-by Nic Chautru <[email protected]>
--- drivers/baseband/acc/rte_acc200_pmd.c | 851 +++++++++++++++++++++++++- 1 file changed, 846 insertions(+), 5 deletions(-)
drivers/baseband/acc/rte_acc200_pmd.c +846 -5
@@ -657,6 +657,46 @@ acc200_dev_info_get(struct rte_bbdev *dev,struct acc_device *d = dev->data->dev_private;int i;static const struct rte_bbdev_op_cap bbdev_capabilities[] = { + { + .type =RTE_BBDEV_OP_TURBO_DEC , + .cap.turbo_dec = { + .capability_flags = +RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE | +RTE_BBDEV_TURBO_CRC_TYPE_24B | +RTE_BBDEV_TURBO_EQUALIZER | +RTE_BBDEV_TURBO_SOFT_OUT_SATURATE | +RTE_BBDEV_TURBO_HALF_ITERATION_EVEN | +RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH | +RTE_BBDEV_TURBO_SOFT_OUTPUT | +RTE_BBDEV_TURBO_EARLY_TERMINATION | +RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN | +RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT | +RTE_BBDEV_TURBO_MAP_DEC | +RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP | +RTE_BBDEV_TURBO_DEC_SCATTER_GATHER , + .max_llr_modulus =INT8_MAX , + .num_buffers_src = +RTE_BBDEV_TURBO_MAX_CODE_BLOCKS , + .num_buffers_hard_out = +RTE_BBDEV_TURBO_MAX_CODE_BLOCKS , + .num_buffers_soft_out = +RTE_BBDEV_TURBO_MAX_CODE_BLOCKS , + } + }, + { + .type =RTE_BBDEV_OP_TURBO_ENC , + .cap.turbo_enc = { + .capability_flags = +RTE_BBDEV_TURBO_CRC_24B_ATTACH | +RTE_BBDEV_TURBO_RV_INDEX_BYPASS | +RTE_BBDEV_TURBO_RATE_MATCH | +RTE_BBDEV_TURBO_ENC_SCATTER_GATHER , + .num_buffers_src = +RTE_BBDEV_TURBO_MAX_CODE_BLOCKS , + .num_buffers_dst = +RTE_BBDEV_TURBO_MAX_CODE_BLOCKS , + } + }, { .type =RTE_BBDEV_OP_LDPC_ENC , .cap.ldpc_enc = {
@@ -708,15 +748,17 @@ acc200_dev_info_get(struct rte_bbdev *dev,/* Exposed number of queues. */ dev_info->num_queues[RTE_BBDEV_OP_NONE ] =0 ; - dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC ] =0 ; - dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC ] =0 ; + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC ] = d->acc_conf.q_ul_4g.num_aqs_per_groups * + d->acc_conf.q_ul_4g.num_qgroups; + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC ] = d->acc_conf.q_dl_4g.num_aqs_per_groups * + d->acc_conf.q_dl_4g.num_qgroups; dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC ] = d->acc_conf.q_ul_5g.num_aqs_per_groups * d->acc_conf.q_ul_5g.num_qgroups; dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC ] = d->acc_conf.q_dl_5g.num_aqs_per_groups * d->acc_conf.q_dl_5g.num_qgroups; dev_info->num_queues[RTE_BBDEV_OP_FFT ] =0 ; - dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC ] =0 ; - dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC ] =0 ; + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC ] = d->acc_conf.q_ul_4g.num_qgroups; + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC ] = d->acc_conf.q_dl_4g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC ] = d->acc_conf.q_ul_5g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC ] = d->acc_conf.q_dl_5g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_FFT ] =0 ;
@@ -761,6 +803,70 @@ static struct rte_pci_id pci_id_acc200_vf_map[] = { {.device_id = 0}, }; +/* Fill in a frame control word for turbo decoding. */ +static inline void +acc200_fcw_td_fill (const struct rte_bbdev_dec_op *op,struct acc_fcw_td *fcw) +{ + fcw->fcw_ver =1 ; + fcw->num_maps =ACC_FCW_TD_AUTOMAP ; + fcw->bypass_sb_deint = !check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE ); +if (op->turbo_dec.code_block_mode ==RTE_BBDEV_TRANSPORT_BLOCK ) { +/* FIXME for TB block */ + fcw->k_pos = op->turbo_dec.tb_params.k_pos; + fcw->k_neg = op->turbo_dec.tb_params.k_neg; + }else { + fcw->k_pos = op->turbo_dec.cb_params.k; + fcw->k_neg = op->turbo_dec.cb_params.k; + } + fcw->c =1 ; + fcw->c_neg =1 ; +if (check_bit (op->turbo_dec.op_flags,RTE_BBDEV_TURBO_SOFT_OUTPUT )) { + fcw->soft_output_en =1 ; + fcw->sw_soft_out_dis =0 ; + fcw->sw_et_cont =check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH ); + fcw->sw_soft_out_saturation =check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_SOFT_OUT_SATURATE ); +if (check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_EQUALIZER )) { + fcw->bypass_teq =0 ; + fcw->ea = op->turbo_dec.cb_params.e; + fcw->eb = op->turbo_dec.cb_params.e; +if (op->turbo_dec.rv_index ==0 ) + fcw->k0_start_col =ACC_FCW_TD_RVIDX_0 ; +else if (op->turbo_dec.rv_index ==1 ) + fcw->k0_start_col =ACC_FCW_TD_RVIDX_1 ; +else if (op->turbo_dec.rv_index ==2 ) + fcw->k0_start_col =ACC_FCW_TD_RVIDX_2 ; +else + fcw->k0_start_col =ACC_FCW_TD_RVIDX_3 ; + }else { + fcw->bypass_teq =1 ; + fcw->eb =64 ;/* avoid undefined value */ + } + }else { + fcw->soft_output_en =0 ; + fcw->sw_soft_out_dis =1 ; + fcw->bypass_teq =0 ; + } + + fcw->code_block_mode =1 ;/* FIXME */ + fcw->turbo_crc_type =check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_CRC_TYPE_24B ); + + fcw->ext_td_cold_reg_en =1 ; + fcw->raw_decoder_input_on =0 ; + fcw->max_iter =RTE_MAX ((uint8_t ) op->turbo_dec.iter_max,2 ); + fcw->min_iter =2 ; + fcw->half_iter_on = !check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_HALF_ITERATION_EVEN ); + + fcw->early_stop_en =check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_EARLY_TERMINATION ) & !fcw->soft_output_en; + fcw->ext_scale =0xF ; +} +/* Fill in a frame control word for LDPC decoding. */ static inline void acc200_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
@@ -884,7 +990,206 @@ acc200_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, }static inline int -acc200_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, struct acc_dma_req_desc *desc, +acc200_dma_desc_te_fill (struct rte_bbdev_enc_op *op, +struct acc_dma_req_desc *desc,struct rte_mbuf **input, +struct rte_mbuf *output,uint32_t *in_offset, +uint32_t *out_offset,uint32_t *out_length, +uint32_t *mbuf_total_left,uint32_t *seg_total_left,uint8_t r) +{ +int next_triplet =1 ;/* FCW already done. */ +uint32_t e, ea, eb, length; +uint16_t k, k_neg, k_pos; +uint8_t cab, c_neg; + + desc->word0 =ACC_DMA_DESC_TYPE ; + desc->word1 =0 ;/**< Timestamp could be disabled. */ + desc->word2 =0 ; + desc->word3 =0 ; + desc->numCBs =1 ; + +if (op->turbo_enc.code_block_mode ==RTE_BBDEV_TRANSPORT_BLOCK ) { + ea = op->turbo_enc.tb_params.ea; + eb = op->turbo_enc.tb_params.eb; + cab = op->turbo_enc.tb_params.cab; + k_neg = op->turbo_enc.tb_params.k_neg; + k_pos = op->turbo_enc.tb_params.k_pos; + c_neg = op->turbo_enc.tb_params.c_neg; + e = (r < cab) ? ea : eb; + k = (r < c_neg) ? k_neg : k_pos; + }else { + e = op->turbo_enc.cb_params.e; + k = op->turbo_enc.cb_params.k; + } + +if (check_bit (op->turbo_enc.op_flags,RTE_BBDEV_TURBO_CRC_24B_ATTACH )) + length = (k -24 ) >>3 ; +else + length = k >>3 ; + +if (unlikely ((*mbuf_total_left ==0 ) || (*mbuf_total_left < length))) { +rte_bbdev_log (ERR , +"Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u" , + *mbuf_total_left, length); +return -1 ; + } + + next_triplet =acc_dma_fill_blk_type_in (desc, input, in_offset, + length, seg_total_left, next_triplet, +check_bit (op->turbo_enc.op_flags,RTE_BBDEV_TURBO_ENC_SCATTER_GATHER )); +if (unlikely (next_triplet <0 )) { +rte_bbdev_log (ERR , +"Mismatch between data to process and mbuf data length in bbdev_op: %p" , + op); +return -1 ; + } + desc->data_ptrs[next_triplet -1 ].last =1 ; + desc->m2dlen = next_triplet; + *mbuf_total_left -= length; + +/* Set output length. */ +if (check_bit (op->turbo_enc.op_flags,RTE_BBDEV_TURBO_RATE_MATCH )) +/* Integer round up division by 8. */ + *out_length = (e +7 ) >>3 ; +else + *out_length = (k >>3 ) *3 +2 ; + + next_triplet =acc_dma_fill_blk_type (desc, output, *out_offset, + *out_length, next_triplet,ACC_DMA_BLKID_OUT_ENC ); +if (unlikely (next_triplet <0 )) { +rte_bbdev_log (ERR , +"Mismatch between data to process and mbuf data length in bbdev_op: %p" , + op); +return -1 ; + } + op->turbo_enc.output.length += *out_length; + *out_offset += *out_length; + desc->data_ptrs[next_triplet -1 ].last =1 ; + desc->d2mlen = next_triplet - desc->m2dlen; + + desc->op_addr = op; + +return 0 ; +} + +static inline int +acc200_dma_desc_td_fill (struct rte_bbdev_dec_op *op, +struct acc_dma_req_desc *desc,struct rte_mbuf **input, +struct rte_mbuf *h_output,struct rte_mbuf *s_output, +uint32_t *in_offset,uint32_t *h_out_offset, +uint32_t *s_out_offset,uint32_t *h_out_length, +uint32_t *s_out_length,uint32_t *mbuf_total_left, +uint32_t *seg_total_left,uint8_t r) +{ +int next_triplet =1 ;/* FCW already done. */ +uint16_t k; +uint16_t crc24_overlap =0 ; +uint32_t e, kw; + + desc->word0 =ACC_DMA_DESC_TYPE ; + desc->word1 =0 ;/**< Timestamp could be disabled. */ + desc->word2 =0 ; + desc->word3 =0 ; + desc->numCBs =1 ; + +if (op->turbo_dec.code_block_mode ==RTE_BBDEV_TRANSPORT_BLOCK ) { + k = (r < op->turbo_dec.tb_params.c_neg) + ? op->turbo_dec.tb_params.k_neg + : op->turbo_dec.tb_params.k_pos; + e = (r < op->turbo_dec.tb_params.cab) + ? op->turbo_dec.tb_params.ea + : op->turbo_dec.tb_params.eb; + }else { + k = op->turbo_dec.cb_params.k; + e = op->turbo_dec.cb_params.e; + } + +if ((op->turbo_dec.code_block_mode ==RTE_BBDEV_TRANSPORT_BLOCK ) + && !check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP )) + crc24_overlap =24 ; + +/* Calculates circular buffer size. +* According to 3gpp 36.212 section 5.1.4.2 +* Kw = 3 * Kpi, +* where: +* Kpi = nCol * nRow +* where nCol is 32 and nRow can be calculated from: +* D =< nCol * nRow +* where D is the size of each output from turbo encoder block (k + 4). +*/ + kw =RTE_ALIGN_CEIL (k +4 ,32 ) *3 ; + +if (unlikely ((*mbuf_total_left ==0 ) || (*mbuf_total_left < kw))) { +rte_bbdev_log (ERR , +"Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u" , + *mbuf_total_left, kw); +return -1 ; + } + + next_triplet =acc_dma_fill_blk_type_in (desc, input, in_offset, kw, + seg_total_left, next_triplet, +check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_DEC_SCATTER_GATHER )); +if (unlikely (next_triplet <0 )) { +rte_bbdev_log (ERR , +"Mismatch between data to process and mbuf data length in bbdev_op: %p" , + op); +return -1 ; + } + desc->data_ptrs[next_triplet -1 ].last =1 ; + desc->m2dlen = next_triplet; + *mbuf_total_left -= kw; + *h_out_length = ((k - crc24_overlap) >>3 ); + next_triplet =acc_dma_fill_blk_type ( + desc, h_output, *h_out_offset, + *h_out_length, next_triplet,ACC_DMA_BLKID_OUT_HARD ); +if (unlikely (next_triplet <0 )) { +rte_bbdev_log (ERR , +"Mismatch between data to process and mbuf data length in bbdev_op: %p" , + op); +return -1 ; + } + + op->turbo_dec.hard_output.length += *h_out_length; + *h_out_offset += *h_out_length; + +/* Soft output. */ +if (check_bit (op->turbo_dec.op_flags,RTE_BBDEV_TURBO_SOFT_OUTPUT )) { +if (op->turbo_dec.soft_output.data ==0 ) { +rte_bbdev_log (ERR ,"Soft output is not defined" ); +return -1 ; + } +if (check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_EQUALIZER )) + *s_out_length = e; +else + *s_out_length = (k *3 ) +12 ; + + next_triplet =acc_dma_fill_blk_type (desc, s_output, + *s_out_offset, *s_out_length, next_triplet, +ACC_DMA_BLKID_OUT_SOFT ); +if (unlikely (next_triplet <0 )) { +rte_bbdev_log (ERR , +"Mismatch between data to process and mbuf data length in bbdev_op: %p" , + op); +return -1 ; + } + + op->turbo_dec.soft_output.length += *s_out_length; + *s_out_offset += *s_out_length; + } + + desc->data_ptrs[next_triplet -1 ].last =1 ; + desc->d2mlen = next_triplet - desc->m2dlen; + + desc->op_addr = op; + +return 0 ; +} + +static inline int +acc200_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, + struct acc_dma_req_desc *desc, struct rte_mbuf **input, struct rte_mbuf *h_output, uint32_t *in_offset, uint32_t *h_out_offset, uint32_t *h_out_length, uint32_t *mbuf_total_left,
@@ -1042,6 +1347,49 @@ acc200_dma_desc_ld_update(struct rte_bbdev_dec_op *op, desc->op_addr = op; } +/* Enqueue one encode operations for ACC200 device in CB mode */ +static inline int +enqueue_enc_one_op_cb (struct acc_queue *q,struct rte_bbdev_enc_op *op, +uint16_t total_enqueued_cbs) +{ +union acc_dma_desc *desc =NULL ; +int ret; +uint32_t in_offset, out_offset, out_length, mbuf_total_left, + seg_total_left; +struct rte_mbuf *input, *output_head, *output; + +uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) + & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; +acc_fcw_te_fill (op, &desc->req.fcw_te); + + input = op->turbo_enc.input.data; + output_head = output = op->turbo_enc.output.data; + in_offset = op->turbo_enc.input.offset; + out_offset = op->turbo_enc.output.offset; + out_length =0 ; + mbuf_total_left = op->turbo_enc.input.length; + seg_total_left =rte_pktmbuf_data_len (op->turbo_enc.input.data) + - in_offset; + + ret =acc200_dma_desc_te_fill (op, &desc->req, &input, output, + &in_offset, &out_offset, &out_length, &mbuf_total_left, + &seg_total_left,0 ); + +if (unlikely (ret <0 )) +return ret; + +mbuf_append (output_head, output, out_length); + +#ifdef RTE_LIBRTE_BBDEV_DEBUG +rte_memdump (stderr,"FCW" , &desc->req.fcw_te, +sizeof (desc->req.fcw_te) -8 ); +rte_memdump (stderr,"Req Desc." , desc,sizeof (*desc)); +#endif +/* One CB (one op) was successfully prepared to enqueue */ +return 1 ; +} +/* Enqueue one encode operations for ACC200 device in CB mode * multiplexed on the same descriptor. */
@@ -1154,6 +1502,78 @@ enqueue_ldpc_enc_part_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, } +/* Enqueue one encode operations for ACC200 device in TB mode. */ +static inline int +enqueue_enc_one_op_tb (struct acc_queue *q,struct rte_bbdev_enc_op *op, +uint16_t total_enqueued_cbs,uint8_t cbs_in_tb) +{ +union acc_dma_desc *desc =NULL ; +int ret; +uint8_t r, c; +uint32_t in_offset, out_offset, out_length, mbuf_total_left, + seg_total_left; +struct rte_mbuf *input, *output_head, *output; +uint16_t current_enqueued_cbs =0 ; + +uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) + & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; +uint64_t fcw_offset = (desc_idx <<8 ) +ACC_DESC_FCW_OFFSET ; +acc_fcw_te_fill (op, &desc->req.fcw_te); + + input = op->turbo_enc.input.data; + output_head = output = op->turbo_enc.output.data; + in_offset = op->turbo_enc.input.offset; + out_offset = op->turbo_enc.output.offset; + out_length =0 ; + mbuf_total_left = op->turbo_enc.input.length; + + c = op->turbo_enc.tb_params.c; + r = op->turbo_enc.tb_params.r; + +while (mbuf_total_left >0 && r < c) { + seg_total_left =rte_pktmbuf_data_len (input) - in_offset; +/* Set up DMA descriptor */ + desc = q->ring_addr + ((q->sw_ring_head + total_enqueued_cbs) + & q->sw_ring_wrap_mask); + desc->req.data_ptrs[0 ].address = q->ring_addr_iova + fcw_offset; + desc->req.data_ptrs[0 ].blen =ACC_FCW_TE_BLEN ; + + ret =acc200_dma_desc_te_fill (op, &desc->req, &input, output, + &in_offset, &out_offset, &out_length, + &mbuf_total_left, &seg_total_left, r); +if (unlikely (ret <0 )) +return ret; +mbuf_append (output_head, output, out_length); + +/* Set total number of CBs in TB */ + desc->req.cbs_in_tb = cbs_in_tb; +#ifdef RTE_LIBRTE_BBDEV_DEBUG +rte_memdump (stderr,"FCW" , &desc->req.fcw_te, +sizeof (desc->req.fcw_te) -8 ); +rte_memdump (stderr,"Req Desc." , desc,sizeof (*desc)); +#endif + +if (seg_total_left ==0 ) { +/* Go to the next mbuf */ + input = input->next; + in_offset =0 ; + output = output->next; + out_offset =0 ; + } + + total_enqueued_cbs++; + current_enqueued_cbs++; + r++; + } + +/* Set SDone on last CB descriptor for TB mode. */ + desc->req.sdone_enable =1 ; + desc->req.irq_enable = q->irq_enable; + +return current_enqueued_cbs; +} +/* Enqueue one encode operations for ACC200 device in TB mode. * returns the number of descs used. */
@@ -1221,6 +1641,62 @@ enqueue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op,/** Enqueue one decode operations for ACC200 device in CB mode. */ static inline int +enqueue_dec_one_op_cb (struct acc_queue *q,struct rte_bbdev_dec_op *op, +uint16_t total_enqueued_cbs) +{ +union acc_dma_desc *desc =NULL ; +int ret; +uint32_t in_offset, h_out_offset, s_out_offset, s_out_length, + h_out_length, mbuf_total_left, seg_total_left; +struct rte_mbuf *input, *h_output_head, *h_output, + *s_output_head, *s_output; + +uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) + & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; +acc200_fcw_td_fill (op, &desc->req.fcw_td); + + input = op->turbo_dec.input.data; + h_output_head = h_output = op->turbo_dec.hard_output.data; + s_output_head = s_output = op->turbo_dec.soft_output.data; + in_offset = op->turbo_dec.input.offset; + h_out_offset = op->turbo_dec.hard_output.offset; + s_out_offset = op->turbo_dec.soft_output.offset; + h_out_length = s_out_length =0 ; + mbuf_total_left = op->turbo_dec.input.length; + seg_total_left =rte_pktmbuf_data_len (input) - in_offset; + +/* Set up DMA descriptor */ + desc = q->ring_addr + ((q->sw_ring_head + total_enqueued_cbs) + & q->sw_ring_wrap_mask); + + ret =acc200_dma_desc_td_fill (op, &desc->req, &input, h_output, + s_output, &in_offset, &h_out_offset, &s_out_offset, + &h_out_length, &s_out_length, &mbuf_total_left, + &seg_total_left,0 ); + +if (unlikely (ret <0 )) +return ret; + +/* Hard output */ +mbuf_append (h_output_head, h_output, h_out_length); + +/* Soft output */ +if (check_bit (op->turbo_dec.op_flags,RTE_BBDEV_TURBO_SOFT_OUTPUT )) +mbuf_append (s_output_head, s_output, s_out_length); + +#ifdef RTE_LIBRTE_BBDEV_DEBUG +rte_memdump (stderr,"FCW" , &desc->req.fcw_td, +sizeof (desc->req.fcw_td)); +rte_memdump (stderr,"Req Desc." , desc,sizeof (*desc)); +#endif + +/* One CB (one op) was successfully prepared to enqueue */ +return 1 ; +} + +/** Enqueue one decode operations for ACC200 device in CB mode */ +static inline int enqueue_ldpc_dec_one_op_cb (struct acc_queue *q,struct rte_bbdev_dec_op *op,uint16_t total_enqueued_cbs,bool same_op) {
@@ -1403,6 +1879,139 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op,return current_enqueued_cbs; } +/* Enqueue one decode operations for ACC200 device in TB mode */ +static inline int +enqueue_dec_one_op_tb (struct acc_queue *q,struct rte_bbdev_dec_op *op, +uint16_t total_enqueued_cbs,uint8_t cbs_in_tb) +{ +union acc_dma_desc *desc =NULL ; +int ret; +uint8_t r, c; +uint32_t in_offset, h_out_offset, s_out_offset, s_out_length, + h_out_length, mbuf_total_left, seg_total_left; +struct rte_mbuf *input, *h_output_head, *h_output, + *s_output_head, *s_output; +uint16_t current_enqueued_cbs =0 ; + +uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) + & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; +uint64_t fcw_offset = (desc_idx <<8 ) +ACC_DESC_FCW_OFFSET ; +acc200_fcw_td_fill (op, &desc->req.fcw_td); + + input = op->turbo_dec.input.data; + h_output_head = h_output = op->turbo_dec.hard_output.data; + s_output_head = s_output = op->turbo_dec.soft_output.data; + in_offset = op->turbo_dec.input.offset; + h_out_offset = op->turbo_dec.hard_output.offset; + s_out_offset = op->turbo_dec.soft_output.offset; + h_out_length = s_out_length =0 ; + mbuf_total_left = op->turbo_dec.input.length; + c = op->turbo_dec.tb_params.c; + r = op->turbo_dec.tb_params.r; + +while (mbuf_total_left >0 && r < c) { + + seg_total_left =rte_pktmbuf_data_len (input) - in_offset; + +/* Set up DMA descriptor */ + desc = q->ring_addr + ((q->sw_ring_head + total_enqueued_cbs) + & q->sw_ring_wrap_mask); + desc->req.data_ptrs[0 ].address = q->ring_addr_iova + fcw_offset; + desc->req.data_ptrs[0 ].blen =ACC_FCW_TD_BLEN ; + ret =acc200_dma_desc_td_fill (op, &desc->req, &input, + h_output, s_output, &in_offset, &h_out_offset, + &s_out_offset, &h_out_length, &s_out_length, + &mbuf_total_left, &seg_total_left, r); + +if (unlikely (ret <0 )) +return ret; + +/* Hard output */ +mbuf_append (h_output_head, h_output, h_out_length); + +/* Soft output */ +if (check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_SOFT_OUTPUT )) +mbuf_append (s_output_head, s_output, s_out_length); + +/* Set total number of CBs in TB */ + desc->req.cbs_in_tb = cbs_in_tb; +#ifdef RTE_LIBRTE_BBDEV_DEBUG +rte_memdump (stderr,"FCW" , &desc->req.fcw_td, +sizeof (desc->req.fcw_td) -8 ); +rte_memdump (stderr,"Req Desc." , desc,sizeof (*desc)); +#endif + +if (seg_total_left ==0 ) { +/* Go to the next mbuf */ + input = input->next; + in_offset =0 ; + h_output = h_output->next; + h_out_offset =0 ; + +if (check_bit (op->turbo_dec.op_flags, +RTE_BBDEV_TURBO_SOFT_OUTPUT )) { + s_output = s_output->next; + s_out_offset =0 ; + } + } + + total_enqueued_cbs++; + current_enqueued_cbs++; + r++; + } + +/* Set SDone on last CB descriptor for TB mode */ + desc->req.sdone_enable =1 ; + desc->req.irq_enable = q->irq_enable; + +return current_enqueued_cbs; +} + +/* Enqueue encode operations for ACC200 device in CB mode. */ +static uint16_t +acc200_enqueue_enc_cb (struct rte_bbdev_queue_data *q_data, +struct rte_bbdev_enc_op **ops,uint16_t num) +{ +struct acc_queue *q = q_data->queue_private; +int32_t avail =acc_ring_avail_enq (q); +uint16_t i; +union acc_dma_desc *desc; +int ret; + +for (i =0 ; i < num; ++i) { +/* Check if there are available space for further processing */ +if (unlikely (avail -1 <0 )) { +acc_enqueue_ring_full (q_data); +break ; + } + avail -=1 ; + + ret =enqueue_enc_one_op_cb (q, ops[i], i); +if (ret <0 ) { +acc_enqueue_invalid (q_data); +break ; + } + } + +if (unlikely (i ==0 )) +return 0 ;/* Nothing to enqueue */ + +/* Set SDone in last CB in enqueued ops for CB mode*/ + desc = q->ring_addr + ((q->sw_ring_head + i -1 ) + & q->sw_ring_wrap_mask); + desc->req.sdone_enable =1 ; + desc->req.irq_enable = q->irq_enable; + +acc_dma_enqueue (q, i, &q_data->queue_stats); + +/* Update stats */ + q_data->queue_stats.enqueued_count += i; + q_data->queue_stats.enqueue_err_count += num - i; +return i; +} +/** Enqueue encode operations for ACC200 device in CB mode. */ static inline uint16_t acc200_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data,
@@ -1450,6 +2059,45 @@ acc200_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data,return i; } +/* Enqueue encode operations for ACC200 device in TB mode. */ +static uint16_t +acc200_enqueue_enc_tb (struct rte_bbdev_queue_data *q_data, +struct rte_bbdev_enc_op **ops,uint16_t num) +{ +struct acc_queue *q = q_data->queue_private; +int32_t avail =acc_ring_avail_enq (q); +uint16_t i, enqueued_cbs =0 ; +uint8_t cbs_in_tb; +int ret; + +for (i =0 ; i < num; ++i) { + cbs_in_tb =get_num_cbs_in_tb_enc (&ops[i]->turbo_enc); +/* Check if there are available space for further processing */ +if (unlikely ((avail - cbs_in_tb <0 ) || (cbs_in_tb ==0 ))) { +acc_enqueue_ring_full (q_data); +break ; + } + avail -= cbs_in_tb; + + ret =enqueue_enc_one_op_tb (q, ops[i], enqueued_cbs, cbs_in_tb); +if (ret <=0 ) { +acc_enqueue_invalid (q_data); +break ; + } + enqueued_cbs += ret; + } +if (unlikely (enqueued_cbs ==0 )) +return 0 ;/* Nothing to enqueue */ + +acc_dma_enqueue (q, enqueued_cbs, &q_data->queue_stats); + +/* Update stats */ + q_data->queue_stats.enqueued_count += i; + q_data->queue_stats.enqueue_err_count += num - i; + +return i; +} +/* Enqueue LDPC encode operations for ACC200 device in TB mode. */ static uint16_t acc200_enqueue_ldpc_enc_tb(struct rte_bbdev_queue_data *q_data,
@@ -1489,6 +2137,20 @@ acc200_enqueue_ldpc_enc_tb(struct rte_bbdev_queue_data *q_data,return i; } +/* Enqueue encode operations for ACC200 device. */ +static uint16_t +acc200_enqueue_enc (struct rte_bbdev_queue_data *q_data, +struct rte_bbdev_enc_op **ops,uint16_t num) +{ +int32_t aq_avail =acc_aq_avail (q_data, num); +if (unlikely ((aq_avail <=0 ) || (num ==0 ))) +return 0 ; +if (ops[0 ]->turbo_enc.code_block_mode ==RTE_BBDEV_TRANSPORT_BLOCK ) +return acc200_enqueue_enc_tb (q_data, ops, num); +else +return acc200_enqueue_enc_cb (q_data, ops, num); +} +/* Enqueue encode operations for ACC200 device. */ static uint16_t acc200_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
@@ -1503,6 +2165,47 @@ acc200_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,return acc200_enqueue_ldpc_enc_cb (q_data, ops, num); } + +/* Enqueue decode operations for ACC200 device in CB mode. */ +static uint16_t +acc200_enqueue_dec_cb (struct rte_bbdev_queue_data *q_data, +struct rte_bbdev_dec_op **ops,uint16_t num) +{ +struct acc_queue *q = q_data->queue_private; +int32_t avail =acc_ring_avail_enq (q); +uint16_t i; +union acc_dma_desc *desc; +int ret; + +for (i =0 ; i < num; ++i) { +/* Check if there are available space for further processing. */ +if (unlikely (avail -1 <0 )) +break ; + avail -=1 ; + + ret =enqueue_dec_one_op_cb (q, ops[i], i); +if (ret <0 ) +break ; + } + +if (unlikely (i ==0 )) +return 0 ;/* Nothing to enqueue. */ + +/* Set SDone in last CB in enqueued ops for CB mode. */ + desc = q->ring_addr + ((q->sw_ring_head + i -1 ) + & q->sw_ring_wrap_mask); + desc->req.sdone_enable =1 ; + desc->req.irq_enable = q->irq_enable; + +acc_dma_enqueue (q, i, &q_data->queue_stats); + +/* Update stats. */ + q_data->queue_stats.enqueued_count += i; + q_data->queue_stats.enqueue_err_count += num - i; + +return i; +} +/* Enqueue decode operations for ACC200 device in TB mode. */ static uint16_t acc200_enqueue_ldpc_dec_tb(struct rte_bbdev_queue_data *q_data,
@@ -1587,6 +2290,58 @@ acc200_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data,return i; } + +/* Enqueue decode operations for ACC200 device in TB mode */ +static uint16_t +acc200_enqueue_dec_tb (struct rte_bbdev_queue_data *q_data, +struct rte_bbdev_dec_op **ops,uint16_t num) +{ +struct acc_queue *q = q_data->queue_private; +int32_t avail =acc_ring_avail_enq (q); +uint16_t i, enqueued_cbs =0 ; +uint8_t cbs_in_tb; +int ret; + +for (i =0 ; i < num; ++i) { + cbs_in_tb =get_num_cbs_in_tb_dec (&ops[i]->turbo_dec); +/* Check if there are available space for further processing */ +if (unlikely ((avail - cbs_in_tb <0 ) || (cbs_in_tb ==0 ))) { +acc_enqueue_ring_full (q_data); +break ; + } + avail -= cbs_in_tb; + + ret =enqueue_dec_one_op_tb (q, ops[i], enqueued_cbs, cbs_in_tb); +if (ret <=0 ) { +acc_enqueue_invalid (q_data); +break ; + } + enqueued_cbs += ret; + } + +acc_dma_enqueue (q, enqueued_cbs, &q_data->queue_stats); + +/* Update stats */ + q_data->queue_stats.enqueued_count += i; + q_data->queue_stats.enqueue_err_count += num - i; + +return i; +} + +/* Enqueue decode operations for ACC200 device. */ +static uint16_t +acc200_enqueue_dec (struct rte_bbdev_queue_data *q_data, +struct rte_bbdev_dec_op **ops,uint16_t num) +{ +int32_t aq_avail =acc_aq_avail (q_data, num); +if (unlikely ((aq_avail <=0 ) || (num ==0 ))) +return 0 ; +if (ops[0 ]->turbo_dec.code_block_mode ==RTE_BBDEV_TRANSPORT_BLOCK ) +return acc200_enqueue_dec_tb (q_data, ops, num); +else +return acc200_enqueue_dec_cb (q_data, ops, num); +} +/* Enqueue decode operations for ACC200 device. */ static uint16_t acc200_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
@@ -1913,6 +2668,48 @@ dequeue_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op **ref_op,return cb_idx; } +/* Dequeue encode operations from ACC200 device. */ +static uint16_t +acc200_dequeue_enc (struct rte_bbdev_queue_data *q_data, +struct rte_bbdev_enc_op **ops,uint16_t num) +{ +struct acc_queue *q = q_data->queue_private; +uint32_t avail =acc_ring_avail_deq (q); +uint32_t aq_dequeued =0 ; +uint16_t i, dequeued_ops =0 , dequeued_descs =0 ; +int ret, cbm; +struct rte_bbdev_enc_op *op; +if (avail ==0 ) +return 0 ; + op = (q->ring_addr + (q->sw_ring_tail & + q->sw_ring_wrap_mask))->req.op_addr; + + cbm = op->turbo_enc.code_block_mode; + +for (i =0 ; i < num; i++) { +if (cbm ==RTE_BBDEV_TRANSPORT_BLOCK ) + ret =dequeue_enc_one_op_tb (q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); +else + ret =dequeue_enc_one_op_cb (q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); +if (ret <0 ) +break ; +if (dequeued_ops >= num) +break ; + } + + q->aq_dequeued += aq_dequeued; + q->sw_ring_tail += dequeued_descs; + +/* Update enqueue stats */ + q_data->queue_stats.dequeued_count += dequeued_ops; + +return dequeued_ops; +} +/* Dequeue LDPC encode operations from ACC200 device. */ static uint16_t acc200_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
@@ -1953,6 +2750,46 @@ acc200_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,return dequeued_ops; } +/* Dequeue decode operations from ACC200 device. */ +static uint16_t +acc200_dequeue_dec (struct rte_bbdev_queue_data *q_data, +struct rte_bbdev_dec_op **ops,uint16_t num) +{ +struct acc_queue *q = q_data->queue_private; +uint16_t dequeue_num; +uint32_t avail =acc_ring_avail_deq (q); +uint32_t aq_dequeued =0 ; +uint16_t i; +uint16_t dequeued_cbs =0 ; +struct rte_bbdev_dec_op *op; +int ret; + + dequeue_num = (avail < num) ? avail : num; + +for (i =0 ; i < dequeue_num; ++i) { + op = (q->ring_addr + ((q->sw_ring_tail + dequeued_cbs) + & q->sw_ring_wrap_mask))->req.op_addr; +if (op->turbo_dec.code_block_mode ==RTE_BBDEV_TRANSPORT_BLOCK ) + ret =dequeue_dec_one_op_tb (q, &ops[i], dequeued_cbs, + &aq_dequeued); +else + ret =dequeue_dec_one_op_cb (q_data, q, &ops[i], + dequeued_cbs, &aq_dequeued); + +if (ret <=0 ) +break ; + dequeued_cbs += ret; + } + + q->aq_dequeued += aq_dequeued; + q->sw_ring_tail += dequeued_cbs; + +/* Update enqueue stats */ + q_data->queue_stats.dequeued_count += i; + +return i; +} +/* Dequeue decode operations from ACC200 device. */ static uint16_t acc200_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
@@ -2001,6 +2838,10 @@ acc200_bbdev_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)struct rte_pci_device *pci_dev =RTE_DEV_TO_PCI (dev->device); dev->dev_ops = &acc200_bbdev_ops; + dev->enqueue_enc_ops = acc200_enqueue_enc; + dev->enqueue_dec_ops = acc200_enqueue_dec; + dev->dequeue_enc_ops = acc200_dequeue_enc; + dev->dequeue_dec_ops = acc200_dequeue_dec; dev->enqueue_ldpc_enc_ops = acc200_enqueue_ldpc_enc; dev->enqueue_ldpc_dec_ops = acc200_enqueue_ldpc_dec; dev->dequeue_ldpc_enc_ops = acc200_dequeue_ldpc_enc;
Signature · 1 line
2.37.1
PATCH v8 10/14 baseband/acc: add support for FFT operations
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Added functions and capability for FFT processing
Signed-off-by Nic Chautru <[email protected]>
--- drivers/baseband/acc/rte_acc200_pmd.c | 240 +++++++++++++++++++++++++- 1 file changed, 238 insertions(+), 2 deletions(-)
drivers/baseband/acc/rte_acc200_pmd.c +238 -2
@@ -734,6 +734,21 @@ acc200_dev_info_get(struct rte_bbdev *dev, .num_buffers_soft_out = 0, } }, + { + .type = RTE_BBDEV_OP_FFT, + .cap.fft = { + .capability_flags = +RTE_BBDEV_FFT_WINDOWING | +RTE_BBDEV_FFT_CS_ADJUSTMENT | +RTE_BBDEV_FFT_DFT_BYPASS | +RTE_BBDEV_FFT_IDFT_BYPASS | + RTE_BBDEV_FFT_WINDOWING_BYPASS, + .num_buffers_src = + RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, + .num_buffers_dst = +RTE_BBDEV_LDPC_MAX_CODE_BLOCKS , + } + }, RTE_BBDEV_END_OF_CAPABILITIES_LIST() };
@@ -756,12 +771,13 @@ acc200_dev_info_get(struct rte_bbdev *dev, d->acc_conf.q_ul_5g.num_qgroups; dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC ] = d->acc_conf.q_dl_5g.num_aqs_per_groups * d->acc_conf.q_dl_5g.num_qgroups; - dev_info->num_queues[RTE_BBDEV_OP_FFT ] =0 ; + dev_info->num_queues[RTE_BBDEV_OP_FFT ] = d->acc_conf.q_fft.num_aqs_per_groups * + d->acc_conf.q_fft.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC ] = d->acc_conf.q_ul_4g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC ] = d->acc_conf.q_dl_4g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC ] = d->acc_conf.q_ul_5g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC ] = d->acc_conf.q_dl_5g.num_qgroups; - dev_info->queue_priority[RTE_BBDEV_OP_FFT ] =0 ; + dev_info->queue_priority[RTE_BBDEV_OP_FFT ] = d->acc_conf.q_fft.num_qgroups; dev_info->max_num_queues =0 ;for (i =RTE_BBDEV_OP_NONE ; i <=RTE_BBDEV_OP_FFT ; i++) dev_info->max_num_queues += dev_info->num_queues[i];
@@ -2831,6 +2847,224 @@ acc200_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,return i; } +/* Fill in a frame control word for FFT processing. */ +static inline void +acc200_fcw_fft_fill (struct rte_bbdev_fft_op *op,struct acc_fcw_fft *fcw) +{ + fcw->in_frame_size = op->fft.input_sequence_size; + fcw->leading_pad_size = op->fft.input_leading_padding; + fcw->out_frame_size = op->fft.output_sequence_size; + fcw->leading_depad_size = op->fft.output_leading_depadding; + fcw->cs_window_sel = op->fft.window_index[0 ] + + (op->fft.window_index[1 ] <<8 ) + + (op->fft.window_index[2 ] <<16 ) + + (op->fft.window_index[3 ] <<24 ); + fcw->cs_window_sel2 = op->fft.window_index[4 ] + + (op->fft.window_index[5 ] <<8 ); + fcw->cs_enable_bmap = op->fft.cs_bitmap; + fcw->num_antennas = op->fft.num_antennas_log2; + fcw->idft_size = op->fft.idft_log2; + fcw->dft_size = op->fft.dft_log2; + fcw->cs_offset = op->fft.cs_time_adjustment; + fcw->idft_shift = op->fft.idft_shift; + fcw->dft_shift = op->fft.dft_shift; + fcw->cs_multiplier = op->fft.ncs_reciprocal; +if (check_bit (op->fft.op_flags, +RTE_BBDEV_FFT_IDFT_BYPASS )) { +if (check_bit (op->fft.op_flags, +RTE_BBDEV_FFT_WINDOWING_BYPASS )) + fcw->bypass =2 ; +else + fcw->bypass =1 ; + }else if (check_bit (op->fft.op_flags, +RTE_BBDEV_FFT_DFT_BYPASS )) + fcw->bypass =3 ; +else + fcw->bypass =0 ; +} + +static inline int +acc200_dma_desc_fft_fill (struct rte_bbdev_fft_op *op, +struct acc_dma_req_desc *desc, +struct rte_mbuf *input,struct rte_mbuf *output, +uint32_t *in_offset,uint32_t *out_offset) +{ +/* FCW already done */ +acc_header_init (desc); + desc->data_ptrs[1 ].address = +rte_pktmbuf_iova_offset (input, *in_offset); + desc->data_ptrs[1 ].blen = op->fft.input_sequence_size *4 ; + desc->data_ptrs[1 ].blkid =ACC_DMA_BLKID_IN ; + desc->data_ptrs[1 ].last =1 ; + desc->data_ptrs[1 ].dma_ext =0 ; + desc->data_ptrs[2 ].address = +rte_pktmbuf_iova_offset (output, *out_offset); + desc->data_ptrs[2 ].blen = op->fft.output_sequence_size *4 ; + desc->data_ptrs[2 ].blkid =ACC_DMA_BLKID_OUT_HARD ; + desc->data_ptrs[2 ].last =1 ; + desc->data_ptrs[2 ].dma_ext =0 ; + desc->m2dlen =2 ; + desc->d2mlen =1 ; + desc->ib_ant_offset = op->fft.input_sequence_size; + desc->num_ant = op->fft.num_antennas_log2 -3 ; +int num_cs =0 , i; +for (i =0 ; i <12 ; i++) +if (check_bit (op->fft.cs_bitmap,1 << i)) + num_cs++; + desc->num_cs = num_cs; + desc->ob_cyc_offset = op->fft.output_sequence_size; + desc->ob_ant_offset = op->fft.output_sequence_size * num_cs; + desc->op_addr = op; +return 0 ; +} + + +/** Enqueue one FFT operation for ACC200 device. */ +static inline int +enqueue_fft_one_op (struct acc_queue *q,struct rte_bbdev_fft_op *op, +uint16_t total_enqueued_cbs) +{ +union acc_dma_desc *desc; +uint16_t desc_idx; +struct rte_mbuf *input, *output; +uint32_t in_offset, out_offset; +struct acc_fcw_fft *fcw; + + desc_idx = (q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask; + desc = q->ring_addr + desc_idx; + input = op->fft.base_input.data; + output = op->fft.base_output.data; + in_offset = op->fft.base_input.offset; + out_offset = op->fft.base_output.offset; + fcw = &desc->req.fcw_fft; + +acc200_fcw_fft_fill (op, fcw); +acc200_dma_desc_fft_fill (op, &desc->req, input, output, &in_offset, &out_offset); +#ifdef RTE_LIBRTE_BBDEV_DEBUG +rte_memdump (stderr,"FCW" , &desc->req.fcw_fft, +sizeof (desc->req.fcw_fft)); +rte_memdump (stderr,"Req Desc." , desc,sizeof (*desc)); +#endif +return 1 ; +} + +/* Enqueue decode operations for ACC200 device. */ +static uint16_t +acc200_enqueue_fft (struct rte_bbdev_queue_data *q_data, +struct rte_bbdev_fft_op **ops,uint16_t num) +{ +struct acc_queue *q; +int32_t aq_avail, avail; +uint16_t i; +union acc_dma_desc *desc; +int ret; + + aq_avail =acc_aq_avail (q_data, num); +if (unlikely ((aq_avail <=0 ) || (num ==0 ))) +return 0 ; + q = q_data->queue_private; + avail =acc_ring_avail_enq (q); + +for (i =0 ; i < num; ++i) { +/* Check if there are available space for further processing. */ +if (unlikely (avail <1 )) +break ; + avail -=1 ; + ret =enqueue_fft_one_op (q, ops[i], i); +if (ret <0 ) +break ; + } + +if (unlikely (i ==0 )) +return 0 ;/* Nothing to enqueue. */ + +/* Set SDone in last CB in enqueued ops for CB mode. */ + desc = q->ring_addr + ((q->sw_ring_head + i -1 ) & q->sw_ring_wrap_mask); + + desc->req.sdone_enable =1 ; + desc->req.irq_enable = q->irq_enable; +acc_dma_enqueue (q, i, &q_data->queue_stats); + +/* Update stats */ + q_data->queue_stats.enqueued_count += i; + q_data->queue_stats.enqueue_err_count += num - i; +return i; +} + + +/* Dequeue one FFT operations from ACC200 device. */ +static inline int +dequeue_fft_one_op (struct rte_bbdev_queue_data *q_data, +struct acc_queue *q,struct rte_bbdev_fft_op **ref_op, +uint16_t dequeued_cbs,uint32_t *aq_dequeued) +{ +union acc_dma_desc *desc, atom_desc; +union acc_dma_rsp_desc rsp; +struct rte_bbdev_fft_op *op; + + desc = q->ring_addr + ((q->sw_ring_tail + dequeued_cbs) & q->sw_ring_wrap_mask); + atom_desc.atom_hdr =__atomic_load_n ((uint64_t *)desc, __ATOMIC_RELAXED); + +/* Check fdone bit */ +if (!(atom_desc.rsp.val &ACC_FDONE )) +return -1 ; + + rsp.val = atom_desc.rsp.val; +#ifdef RTE_LIBRTE_BBDEV_DEBUG +rte_memdump (stderr,"Resp" , &desc->rsp.val, +sizeof (desc->rsp.val)); +#endif +/* Dequeue. */ + op = desc->req.op_addr; + +/* Clearing status, it will be set based on response. */ + op->status =0 ; + op->status |= rsp.input_err <<RTE_BBDEV_DATA_ERROR ; + op->status |= rsp.dma_err <<RTE_BBDEV_DRV_ERROR ; + op->status |= rsp.fcw_err <<RTE_BBDEV_DRV_ERROR ; +if (op->status !=0 ) + q_data->queue_stats.dequeue_err_count++; + +/* Check if this is the last desc in batch (Atomic Queue). */ +if (desc->req.last_desc_in_batch) { + (*aq_dequeued)++; + desc->req.last_desc_in_batch =0 ; + } + desc->rsp.val =ACC_DMA_DESC_TYPE ; + desc->rsp.add_info_0 =0 ; + *ref_op = op; +/* One CB (op) was successfully dequeued. */ +return 1 ; +} + + +/* Dequeue FFT operations from ACC200 device. */ +static uint16_t +acc200_dequeue_fft (struct rte_bbdev_queue_data *q_data, +struct rte_bbdev_fft_op **ops,uint16_t num) +{ +struct acc_queue *q = q_data->queue_private; +uint16_t dequeue_num, i, dequeued_cbs =0 ; +uint32_t avail =acc_ring_avail_deq (q); +uint32_t aq_dequeued =0 ; +int ret; + + dequeue_num =RTE_MIN (avail, num); + +for (i =0 ; i < dequeue_num; ++i) { + ret =dequeue_fft_one_op (q_data, q, &ops[i], dequeued_cbs, &aq_dequeued); +if (ret <=0 ) +break ; + dequeued_cbs += ret; + } + + q->aq_dequeued += aq_dequeued; + q->sw_ring_tail += dequeued_cbs; +/* Update enqueue stats. */ + q_data->queue_stats.dequeued_count += i; +return i; +} +/* Initialization Function */ static void acc200_bbdev_init (struct rte_bbdev *dev,struct rte_pci_driver *drv)
@@ -2846,6 +3080,8 @@ acc200_bbdev_init(struct rte_bbdev *dev, struct rte_pci_driver *drv) dev->enqueue_ldpc_dec_ops = acc200_enqueue_ldpc_dec; dev->dequeue_ldpc_enc_ops = acc200_dequeue_ldpc_enc; dev->dequeue_ldpc_dec_ops = acc200_dequeue_ldpc_dec; + dev->enqueue_fft_ops = acc200_enqueue_fft; + dev->dequeue_fft_ops = acc200_dequeue_fft; ((struct acc_device *) dev->data->dev_private)->pf_device = !strcmp(drv->driver.name,
Signature · 1 line
2.37.1
PATCH v8 11/14 baseband/acc: support interrupt
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Added support for capability and functions for MSI/MSI-X interrupt and underlying information ring.
Signed-off-by Nic Chautru <[email protected]>
--- drivers/baseband/acc/rte_acc200_pmd.c | 302 +++++++++++++++++++++++++- 1 file changed, 299 insertions(+), 3 deletions(-)
drivers/baseband/acc/rte_acc200_pmd.c +299 -3
@@ -219,6 +219,149 @@ fetch_acc200_config(struct rte_bbdev *dev) acc_conf->q_fft.aq_depth_log2); } +/* Checks PF Info Ring to find the interrupt cause and handles it accordingly. */ +static inline void +acc200_check_ir (struct acc_device *acc200_dev) +{ +volatile union acc_info_ring_data *ring_data; +uint16_t info_ring_head = acc200_dev->info_ring_head; +if (unlikely (acc200_dev->info_ring ==NULL )) +return ; + + ring_data = acc200_dev->info_ring + (acc200_dev->info_ring_head &ACC_INFO_RING_MASK ); + +while (ring_data->valid) { +if ((ring_data->int_nb <ACC200_PF_INT_DMA_DL_DESC_IRQ ) || ( + ring_data->int_nb >ACC200_PF_INT_DMA_DL5G_DESC_IRQ )) { +rte_bbdev_log (WARNING ,"InfoRing: ITR:%d Info:0x%x" , + ring_data->int_nb, ring_data->detailed_info); +/* Initialize Info Ring entry and move forward. */ + ring_data->val =0 ; + } + info_ring_head++; + ring_data = acc200_dev->info_ring + (info_ring_head &ACC_INFO_RING_MASK ); + } +} + +/* Interrupt handler triggered by ACC200 dev for handling specific interrupt. */ +static void +acc200_dev_interrupt_handler (void *cb_arg) +{ +struct rte_bbdev *dev = cb_arg; +struct acc_device *acc200_dev = dev->data->dev_private; +volatile union acc_info_ring_data *ring_data; +struct acc_deq_intr_details deq_intr_det; + + ring_data = acc200_dev->info_ring + (acc200_dev->info_ring_head &ACC_INFO_RING_MASK ); + +while (ring_data->valid) { +if (acc200_dev->pf_device) { +rte_bbdev_log_debug ( +"ACC200 PF Interrupt received, Info Ring data: 0x%x -> %d" , + ring_data->val, ring_data->int_nb); + +switch (ring_data->int_nb) { +case ACC200_PF_INT_DMA_DL_DESC_IRQ : +case ACC200_PF_INT_DMA_UL_DESC_IRQ : +case ACC200_PF_INT_DMA_FFT_DESC_IRQ : +case ACC200_PF_INT_DMA_UL5G_DESC_IRQ : +case ACC200_PF_INT_DMA_DL5G_DESC_IRQ : + deq_intr_det.queue_id =get_queue_id_from_ring_info ( + dev->data, *ring_data); +if (deq_intr_det.queue_id ==UINT16_MAX ) { +rte_bbdev_log (ERR , +"Couldn't find queue: aq_id: %u, qg_id: %u, vf_id: %u" , + ring_data->aq_id, + ring_data->qg_id, + ring_data->vf_id); +return ; + } +rte_bbdev_pmd_callback_process (dev, +RTE_BBDEV_EVENT_DEQUEUE , &deq_intr_det); +break ; +default : +rte_bbdev_pmd_callback_process (dev,RTE_BBDEV_EVENT_ERROR ,NULL ); +break ; + } + }else { +rte_bbdev_log_debug ( +"ACC200 VF Interrupt received, Info Ring data: 0x%x\n" , + ring_data->val); +switch (ring_data->int_nb) { +case ACC200_VF_INT_DMA_DL_DESC_IRQ : +case ACC200_VF_INT_DMA_UL_DESC_IRQ : +case ACC200_VF_INT_DMA_FFT_DESC_IRQ : +case ACC200_VF_INT_DMA_UL5G_DESC_IRQ : +case ACC200_VF_INT_DMA_DL5G_DESC_IRQ : +/* VFs are not aware of their vf_id - it's set to 0. */ + ring_data->vf_id =0 ; + deq_intr_det.queue_id =get_queue_id_from_ring_info ( + dev->data, *ring_data); +if (deq_intr_det.queue_id ==UINT16_MAX ) { +rte_bbdev_log (ERR , +"Couldn't find queue: aq_id: %u, qg_id: %u" , + ring_data->aq_id, + ring_data->qg_id); +return ; + } +rte_bbdev_pmd_callback_process (dev, +RTE_BBDEV_EVENT_DEQUEUE , &deq_intr_det); +break ; +default : +rte_bbdev_pmd_callback_process (dev,RTE_BBDEV_EVENT_ERROR ,NULL ); +break ; + } + } + +/* Initialize Info Ring entry and move forward. */ + ring_data->val =0 ; + ++acc200_dev->info_ring_head; + ring_data = acc200_dev->info_ring + + (acc200_dev->info_ring_head &ACC_INFO_RING_MASK ); + } +} + +/* Allocate and setup inforing. */ +static int +allocate_info_ring (struct rte_bbdev *dev) +{ +struct acc_device *d = dev->data->dev_private; +const struct acc200_registry_addr *reg_addr; +rte_iova_t info_ring_iova; +uint32_t phys_low, phys_high; + +if (d->info_ring !=NULL ) +return 0 ;/* Already configured. */ + +/* Choose correct registry addresses for the device type. */ +if (d->pf_device) + reg_addr = &pf_reg_addr; +else + reg_addr = &vf_reg_addr; +/* Allocate InfoRing */ + d->info_ring =rte_zmalloc_socket ("Info Ring" ,ACC_INFO_RING_NUM_ENTRIES * +sizeof (*d->info_ring),RTE_CACHE_LINE_SIZE , dev->data->socket_id); +if (d->info_ring ==NULL ) { +rte_bbdev_log (ERR , +"Failed to allocate Info Ring for %s:%u" , + dev->device->driver->name, + dev->data->dev_id); +return -ENOMEM ; + } + info_ring_iova =rte_malloc_virt2iova (d->info_ring); + +/* Setup Info Ring. */ + phys_high = (uint32_t )(info_ring_iova >>32 ); + phys_low = (uint32_t )(info_ring_iova); +acc_reg_write (d, reg_addr->info_ring_hi, phys_high); +acc_reg_write (d, reg_addr->info_ring_lo, phys_low); +acc_reg_write (d, reg_addr->info_ring_en,ACC200_REG_IRQ_EN_ALL ); + d->info_ring_head = (acc_reg_read (d, reg_addr->info_ring_ptr) & +0xFFF ) /sizeof (union acc_info_ring_data ); +return 0 ; +} + +/* Allocate 64MB memory used for all software rings. */ static int acc200_setup_queues (struct rte_bbdev *dev,uint16_t num_queues,int socket_id)
@@ -327,6 +470,14 @@ acc200_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)acc_reg_write (d, reg_addr->tail_ptrs_fft_hi, phys_high);acc_reg_write (d, reg_addr->tail_ptrs_fft_lo, phys_low); + ret =allocate_info_ring (dev); +if (ret <0 ) { +rte_bbdev_log (ERR ,"Failed to allocate info_ring for %s:%u" , + dev->device->driver->name, + dev->data->dev_id); +/* Continue */ + } +if (d->harq_layout ==NULL ) d->harq_layout = rte_zmalloc_socket("HARQ Layout", ACC_HARQ_LAYOUT * sizeof(*d->harq_layout),
@@ -357,17 +508,120 @@ acc200_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)return ret; } +static int +acc200_intr_enable (struct rte_bbdev *dev) +{ +int ret; +struct acc_device *d = dev->data->dev_private; +/* +* MSI/MSI-X are supported. +* Option controlled by vfio-intr through EAL parameter. +*/ +if (rte_intr_type_get (dev->intr_handle) ==RTE_INTR_HANDLE_VFIO_MSI ) { + + ret =allocate_info_ring (dev); +if (ret <0 ) { +rte_bbdev_log (ERR , +"Couldn't allocate info ring for device: %s" , + dev->data->name); +return ret; + } + ret =rte_intr_enable (dev->intr_handle); +if (ret <0 ) { +rte_bbdev_log (ERR , +"Couldn't enable interrupts for device: %s" , + dev->data->name); +rte_free (d->info_ring); +return ret; + } + ret =rte_intr_callback_register (dev->intr_handle, + acc200_dev_interrupt_handler, dev); +if (ret <0 ) { +rte_bbdev_log (ERR , +"Couldn't register interrupt callback for device: %s" , + dev->data->name); +rte_free (d->info_ring); +return ret; + } + +return 0 ; + }else if (rte_intr_type_get (dev->intr_handle) ==RTE_INTR_HANDLE_VFIO_MSIX ) { +int i, max_queues; +struct acc_device *acc200_dev = dev->data->dev_private; + + ret =allocate_info_ring (dev); +if (ret <0 ) { +rte_bbdev_log (ERR , +"Couldn't allocate info ring for device: %s" , + dev->data->name); +return ret; + } + +if (acc200_dev->pf_device) + max_queues =ACC200_MAX_PF_MSIX ; +else + max_queues =ACC200_MAX_VF_MSIX ; + +if (rte_intr_efd_enable (dev->intr_handle, max_queues)) { +rte_bbdev_log (ERR ,"Failed to create fds for %u queues" , + dev->data->num_queues); +return -1 ; + } + +for (i =0 ; i < max_queues; ++i) { +if (rte_intr_efds_index_set (dev->intr_handle, i, +rte_intr_fd_get (dev->intr_handle))) +return -rte_errno; + } + +if (rte_intr_vec_list_alloc (dev->intr_handle,"intr_vec" , + dev->data->num_queues)) { +rte_bbdev_log (ERR ,"Failed to allocate %u vectors" , + dev->data->num_queues); +return -ENOMEM ; + } + + ret =rte_intr_enable (dev->intr_handle); + +if (ret <0 ) { +rte_bbdev_log (ERR , +"Couldn't enable interrupts for device: %s" , + dev->data->name); +rte_free (d->info_ring); +return ret; + } + ret =rte_intr_callback_register (dev->intr_handle, + acc200_dev_interrupt_handler, dev); +if (ret <0 ) { +rte_bbdev_log (ERR , +"Couldn't register interrupt callback for device: %s" , + dev->data->name); +rte_free (d->info_ring); +return ret; + } + +return 0 ; + } + +rte_bbdev_log (ERR ,"ACC200 (%s) supports only VFIO MSI/MSI-X interrupts\n" , + dev->data->name); +return -ENOTSUP ; +} +/* Free memory used for software rings. */ static int acc200_dev_close (struct rte_bbdev *dev) {struct acc_device *d = dev->data->dev_private; +acc200_check_ir (d);if (d->sw_rings_base !=NULL ) {rte_free (d->tail_ptrs); +rte_free (d->info_ring);rte_free (d->sw_rings_base);rte_free (d->harq_layout); - d->sw_rings_base =NULL ; d->tail_ptrs =NULL ; + d->info_ring =NULL ; + d->sw_rings_base =NULL ; d->harq_layout =NULL ; }/* Ensure all in flight HW transactions are completed. */
@@ -669,6 +923,7 @@ acc200_dev_info_get(struct rte_bbdev *dev,RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH |RTE_BBDEV_TURBO_SOFT_OUTPUT |RTE_BBDEV_TURBO_EARLY_TERMINATION | +RTE_BBDEV_TURBO_DEC_INTERRUPTS |RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN |RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT | RTE_BBDEV_TURBO_MAP_DEC |
@@ -690,6 +945,7 @@ acc200_dev_info_get(struct rte_bbdev *dev,RTE_BBDEV_TURBO_CRC_24B_ATTACH |RTE_BBDEV_TURBO_RV_INDEX_BYPASS |RTE_BBDEV_TURBO_RATE_MATCH | +RTE_BBDEV_TURBO_ENC_INTERRUPTS | RTE_BBDEV_TURBO_ENC_SCATTER_GATHER, .num_buffers_src = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
@@ -703,7 +959,8 @@ acc200_dev_info_get(struct rte_bbdev *dev, .capability_flags =RTE_BBDEV_LDPC_RATE_MATCH |RTE_BBDEV_LDPC_CRC_24B_ATTACH | - RTE_BBDEV_LDPC_INTERLEAVER_BYPASS, +RTE_BBDEV_LDPC_INTERLEAVER_BYPASS | + RTE_BBDEV_LDPC_ENC_INTERRUPTS, .num_buffers_src = RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, .num_buffers_dst =
@@ -724,7 +981,8 @@ acc200_dev_info_get(struct rte_bbdev *dev,RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS |RTE_BBDEV_LDPC_DEC_SCATTER_GATHER |RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION | - RTE_BBDEV_LDPC_LLR_COMPRESSION, +RTE_BBDEV_LDPC_LLR_COMPRESSION | + RTE_BBDEV_LDPC_DEC_INTERRUPTS, .llr_size = 8, .llr_decimals = 1, .num_buffers_src =
@@ -792,15 +1050,46 @@ acc200_dev_info_get(struct rte_bbdev *dev, dev_info->min_alignment =1 ; dev_info->capabilities = bbdev_capabilities; dev_info->harq_buffer_size =0 ; + +acc200_check_ir (d); +} + +static int +acc200_queue_intr_enable (struct rte_bbdev *dev,uint16_t queue_id) +{ +struct acc_queue *q = dev->data->queues[queue_id].queue_private; + +if (rte_intr_type_get (dev->intr_handle) !=RTE_INTR_HANDLE_VFIO_MSI && +rte_intr_type_get (dev->intr_handle) !=RTE_INTR_HANDLE_VFIO_MSIX ) +return -ENOTSUP ; + + q->irq_enable =1 ; +return 0 ; +} + +static int +acc200_queue_intr_disable (struct rte_bbdev *dev,uint16_t queue_id) +{ +struct acc_queue *q = dev->data->queues[queue_id].queue_private; + +if (rte_intr_type_get (dev->intr_handle) !=RTE_INTR_HANDLE_VFIO_MSI && +rte_intr_type_get (dev->intr_handle) !=RTE_INTR_HANDLE_VFIO_MSIX ) +return -ENOTSUP ; + + q->irq_enable =0 ; +return 0 ; }static const struct rte_bbdev_ops acc200_bbdev_ops = { .setup_queues = acc200_setup_queues, + .intr_enable = acc200_intr_enable, .close = acc200_dev_close, .info_get = acc200_dev_info_get, .queue_setup = acc200_queue_setup, .queue_release = acc200_queue_release, .queue_stop = acc_queue_stop, + .queue_intr_enable = acc200_queue_intr_enable, + .queue_intr_disable = acc200_queue_intr_disable };/* ACC200 PCI PF address map. */
@@ -2522,6 +2811,7 @@ dequeue_dec_one_op_cb(struct rte_bbdev_queue_data *q_data,if (op->status !=0 ) {/* These errors are not expected. */ q_data->queue_stats.dequeue_err_count++; +acc200_check_ir (q->d); }/* CRC invalid if error exists. */
@@ -2586,6 +2876,9 @@ dequeue_ldpc_dec_one_op_cb(struct rte_bbdev_queue_data *q_data, op->ldpc_dec.iter_count = (uint8_t ) rsp.iter_cnt; +if (op->status & (1 <<RTE_BBDEV_DRV_ERROR )) +acc200_check_ir (q->d); +/* Check if this is the last desc in batch (Atomic Queue). */ if (desc->req.last_desc_in_batch) { (*aq_dequeued)++;
@@ -3025,6 +3318,9 @@ dequeue_fft_one_op(struct rte_bbdev_queue_data *q_data,if (op->status !=0 ) q_data->queue_stats.dequeue_err_count++; +if (op->status & (1 <<RTE_BBDEV_DRV_ERROR )) +acc200_check_ir (q->d); +/* Check if this is the last desc in batch (Atomic Queue). */ if (desc->req.last_desc_in_batch) { (*aq_dequeued)++;
Signature · 1 line
2.37.1
PATCH v8 12/14 baseband/acc: add device status and vf2pf comms
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Added support to expose the device status seen from the host through v2pf mailbox communication.
Signed-off-by Nic Chautru <[email protected]>
Reviewed-by Maxime Coquelin <[email protected]>
--- drivers/baseband/acc/rte_acc200_pmd.c | 64 ++++++++++++++++++++------- 1 file changed, 47 insertions(+), 17 deletions(-)
drivers/baseband/acc/rte_acc200_pmd.c +47 -17
@@ -200,23 +200,50 @@ fetch_acc200_config(struct rte_bbdev *dev)rte_bbdev_log_debug ("%s Config LLR SIGN IN/OUT %s %s QG %u %u %u %u %u AQ %u %u %u %u %u Len %u %u %u %u %u\n" , (d->pf_device) ?"PF" :"VF" , - (acc_conf->input_pos_llr_1_bit) ?"POS" :"NEG" , - (acc_conf->output_pos_llr_1_bit) ?"POS" :"NEG" , - acc_conf->q_ul_4g.num_qgroups, - acc_conf->q_dl_4g.num_qgroups, - acc_conf->q_ul_5g.num_qgroups, - acc_conf->q_dl_5g.num_qgroups, - acc_conf->q_fft.num_qgroups, - acc_conf->q_ul_4g.num_aqs_per_groups, - acc_conf->q_dl_4g.num_aqs_per_groups, - acc_conf->q_ul_5g.num_aqs_per_groups, - acc_conf->q_dl_5g.num_aqs_per_groups, - acc_conf->q_fft.num_aqs_per_groups, - acc_conf->q_ul_4g.aq_depth_log2, - acc_conf->q_dl_4g.aq_depth_log2, - acc_conf->q_ul_5g.aq_depth_log2, - acc_conf->q_dl_5g.aq_depth_log2, - acc_conf->q_fft.aq_depth_log2); + (acc200_conf->input_pos_llr_1_bit) ?"POS" :"NEG" , + (acc200_conf->output_pos_llr_1_bit) ?"POS" :"NEG" , + acc200_conf->q_ul_4g.num_qgroups, + acc200_conf->q_dl_4g.num_qgroups, + acc200_conf->q_ul_5g.num_qgroups, + acc200_conf->q_dl_5g.num_qgroups, + acc200_conf->q_fft.num_qgroups, + acc200_conf->q_ul_4g.num_aqs_per_groups, + acc200_conf->q_dl_4g.num_aqs_per_groups, + acc200_conf->q_ul_5g.num_aqs_per_groups, + acc200_conf->q_dl_5g.num_aqs_per_groups, + acc200_conf->q_fft.num_aqs_per_groups, + acc200_conf->q_ul_4g.aq_depth_log2, + acc200_conf->q_dl_4g.aq_depth_log2, + acc200_conf->q_ul_5g.aq_depth_log2, + acc200_conf->q_dl_5g.aq_depth_log2, + acc200_conf->q_fft.aq_depth_log2); +} + +static inline void +acc200_vf2pf (struct acc_device *d,unsigned int payload) +{ +acc_reg_write (d, HWVfHiVfToPfDbellVf, payload); +} + +/* Request device status information. */ +static inline uint32_t +acc200_device_status (struct rte_bbdev *dev) +{ +struct acc_device *d = dev->data->dev_private; +uint32_t reg, time_out =0 ; + +if (d->pf_device) +return RTE_BBDEV_DEV_NOT_SUPPORTED ; + +acc200_vf2pf (d,ACC_VF2PF_STATUS_REQUEST ); + reg =acc_reg_read (d, HWVfHiPfToVfDbellVf); +while ((time_out <ACC200_STATUS_TO ) && (reg ==RTE_BBDEV_DEV_NOSTATUS )) { +usleep (ACC200_STATUS_WAIT );/*< Wait or VF->PF->VF Comms */ + reg =acc_reg_read (d, HWVfHiPfToVfDbellVf); + time_out++; + } + +return reg; }/* Checks PF Info Ring to find the interrupt cause and handles it accordingly. */
@@ -492,6 +519,7 @@ acc200_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)/* Mark as configured properly */ d->configured = true; +acc200_vf2pf (d,ACC_VF2PF_USING_VF );rte_bbdev_log_debug ( "ACC200 (%s) configured sw_rings = %p, sw_rings_iova = %#"
@@ -1018,6 +1046,8 @@ acc200_dev_info_get(struct rte_bbdev *dev,/* Read and save the populated config from ACC200 registers. */ fetch_acc200_config (dev); +/* Check the status of device. */ + dev_info->device_status =acc200_device_status (dev);/* Exposed number of queues. */ dev_info->num_queues[RTE_BBDEV_OP_NONE ] =0 ;
Signature · 1 line
2.37.1
PATCH v8 13/14 baseband/acc: add PF configure companion function
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Added configure function notably to configure the device from the PF within DPDK and bbdev-test (without external dependency).
Signed-off-by Nic Chautru <[email protected]>
Acked-by Hernan Vargas <[email protected]>
--- app/test-bbdev/test_bbdev_perf.c | 71 ++++ drivers/baseband/acc/meson.build | 2 +- drivers/baseband/acc/rte_acc200_cfg.h | 48 +++ drivers/baseband/acc/rte_acc200_pmd.c | 466 +++++++++++++++++++++++++- drivers/baseband/acc/version.map | 1 + 5 files changed, 582 insertions(+), 6 deletions(-) create mode 100644 drivers/baseband/acc/rte_acc200_cfg.h
app/test-bbdev/test_bbdev_perf.c +71 -0
@@ -63,6 +63,15 @@#define ACC100_QMGR_INVALID_IDX -1#define ACC100_QMGR_RR 1#define ACC100_QOS_GBR 0 +#include <rte_acc200_cfg.h> +#define ACC200PF_DRIVER_NAME ("intel_acc200_pf") +#define ACC200VF_DRIVER_NAME ("intel_acc200_vf") +#define ACC200_QMGR_NUM_AQS 16 +#define ACC200_QMGR_NUM_QGS 2 +#define ACC200_QMGR_AQ_DEPTH 5 +#define ACC200_QMGR_INVALID_IDX -1 +#define ACC200_QMGR_RR 1 +#define ACC200_QOS_GBR 0#endif #define OPS_CACHE_SIZE 256U
@@ -762,6 +771,68 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info,"Failed to configure ACC100 PF for bbdev %s" , info->dev_name); } +if ((get_init_device () == true) && + (!strcmp (info->drv.driver_name,ACC200PF_DRIVER_NAME ))) { +struct rte_acc_conf conf; +unsigned int i; + +printf ("Configure ACC200 FEC Driver %s with default values\n" , + info->drv.driver_name); + +/* clear default configuration before initialization */ +memset (&conf,0 ,sizeof (struct rte_acc_conf )); + +/* Always set in PF mode for built-in configuration */ + conf.pf_mode_en = true; +for (i =0 ; i <RTE_ACC_NUM_VFS ; ++i) { + conf.arb_dl_4g[i].gbr_threshold1 =ACC200_QOS_GBR ; + conf.arb_dl_4g[i].gbr_threshold1 =ACC200_QOS_GBR ; + conf.arb_dl_4g[i].round_robin_weight =ACC200_QMGR_RR ; + conf.arb_ul_4g[i].gbr_threshold1 =ACC200_QOS_GBR ; + conf.arb_ul_4g[i].gbr_threshold1 =ACC200_QOS_GBR ; + conf.arb_ul_4g[i].round_robin_weight =ACC200_QMGR_RR ; + conf.arb_dl_5g[i].gbr_threshold1 =ACC200_QOS_GBR ; + conf.arb_dl_5g[i].gbr_threshold1 =ACC200_QOS_GBR ; + conf.arb_dl_5g[i].round_robin_weight =ACC200_QMGR_RR ; + conf.arb_ul_5g[i].gbr_threshold1 =ACC200_QOS_GBR ; + conf.arb_ul_5g[i].gbr_threshold1 =ACC200_QOS_GBR ; + conf.arb_ul_5g[i].round_robin_weight =ACC200_QMGR_RR ; + conf.arb_fft[i].gbr_threshold1 =ACC200_QOS_GBR ; + conf.arb_fft[i].gbr_threshold1 =ACC200_QOS_GBR ; + conf.arb_fft[i].round_robin_weight =ACC200_QMGR_RR ; + } + + conf.input_pos_llr_1_bit = true; + conf.output_pos_llr_1_bit = true; + conf.num_vf_bundles =1 ;/**< Number of VF bundles to setup */ + + conf.q_ul_4g.num_qgroups =ACC200_QMGR_NUM_QGS ; + conf.q_ul_4g.first_qgroup_index =ACC200_QMGR_INVALID_IDX ; + conf.q_ul_4g.num_aqs_per_groups =ACC200_QMGR_NUM_AQS ; + conf.q_ul_4g.aq_depth_log2 =ACC200_QMGR_AQ_DEPTH ; + conf.q_dl_4g.num_qgroups =ACC200_QMGR_NUM_QGS ; + conf.q_dl_4g.first_qgroup_index =ACC200_QMGR_INVALID_IDX ; + conf.q_dl_4g.num_aqs_per_groups =ACC200_QMGR_NUM_AQS ; + conf.q_dl_4g.aq_depth_log2 =ACC200_QMGR_AQ_DEPTH ; + conf.q_ul_5g.num_qgroups =ACC200_QMGR_NUM_QGS ; + conf.q_ul_5g.first_qgroup_index =ACC200_QMGR_INVALID_IDX ; + conf.q_ul_5g.num_aqs_per_groups =ACC200_QMGR_NUM_AQS ; + conf.q_ul_5g.aq_depth_log2 =ACC200_QMGR_AQ_DEPTH ; + conf.q_dl_5g.num_qgroups =ACC200_QMGR_NUM_QGS ; + conf.q_dl_5g.first_qgroup_index =ACC200_QMGR_INVALID_IDX ; + conf.q_dl_5g.num_aqs_per_groups =ACC200_QMGR_NUM_AQS ; + conf.q_dl_5g.aq_depth_log2 =ACC200_QMGR_AQ_DEPTH ; + conf.q_fft.num_qgroups =ACC200_QMGR_NUM_QGS ; + conf.q_fft.first_qgroup_index =ACC200_QMGR_INVALID_IDX ; + conf.q_fft.num_aqs_per_groups =ACC200_QMGR_NUM_AQS ; + conf.q_fft.aq_depth_log2 =ACC200_QMGR_AQ_DEPTH ; + +/* setup PF with configuration information */ + ret =rte_acc200_configure (info->dev_name, &conf); +TEST_ASSERT_SUCCESS (ret, +"Failed to configure ACC200 PF for bbdev %s" , + info->dev_name); + }#endif /* Let's refresh this now this is configured */ rte_bbdev_info_get (dev_id, info);
drivers/baseband/acc/meson.build +1 -1
@@ -5,4 +5,4 @@ deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci'] sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c') -headers = files('rte_acc100_cfg.h') +headers = files('rte_acc100_cfg.h', 'rte_acc200_cfg.h')
drivers/baseband/acc/rte_acc200_cfg.h new file +48 -0
48 lines not on this page · raw message
drivers/baseband/acc/rte_acc200_pmd.c +461 -5
491 lines not on this page · raw message
drivers/baseband/acc/version.map +1 -0
@@ -6,4 +6,5 @@ EXPERIMENTAL { global: rte_acc10x_configure; + rte_acc200_configure; };
Signature · 1 line
2.37.1
PATCH v8 14/14 baseband/acc: simplify meson dependency
In reply to Nicolas ChautruFrom: Nic Chautru <[email protected]>
Removed some of libraries from the external dependency captured in meson build file which are not required.
Signed-off-by Nic Chautru <[email protected]>
--- drivers/baseband/acc/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/baseband/acc/meson.build +1 -1
@@ -1,7 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2020 Intel Corporation -deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci'] +deps += ['bbdev', 'bus_pci'] sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c')
Signature · 1 line
2.37.1