riscv,isa fixups
Subsystems (2)
v2 cover riscv,isa fixups
From: Conor Dooley <[email protected]>
I noticed ~today~ while looking at the isa manual that I had not accounted for another couple of edge cases with my regex. As before, I think attempting to validate the canonical order for multiletter stuff makes no sense - but we should totally try to avoid false-positives for combinations that are known to be valid.
All I've changed here for v2 is collecting tags & adding in the missing commit reference that Heiko pointed out.
@Palmer, either you can take this once the DT folks have ACKed it if you like, or I will take onto some v6.2-rcN fixes branch. I don't think that there is any urgency :)
Thanks,
Conor.
Conor Dooley (2):
dt-bindings: riscv: fix underscore requirement for addtional standard
extensions
dt-bindings: riscv: fix single letter canonical order
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Signature · 1 line
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PATCH v2 1/2 dt-bindings: riscv: fix underscore requirement for addtional standard extensions
From: Conor Dooley <[email protected]>
The RISC-V ISA Manual allows for the first Additional Standard Extension having no leading underscore. Only if there are multiple Additional Standard Extensions is it needed to have an underscore.
The dt-binding does not validate that a multi-letter extension is canonically ordered, as that'd need an even worse regex than is here, but it should not fail validation for valid ISA strings.
Allow the first Z multi-letter extension to appear immediately prior after the single-letter extensions.
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Documentation/devicetree/bindings/riscv/cpus.yaml +1 -1
@@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false
Signature · 1 line
2.38.1
Re: [PATCH v2 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions
Quoted 27 lines · Conor Dooley
From: Conor Dooley <[email protected]>
The RISC-V ISA Manual allows for the first Additional Standard Extension having no leading underscore. Only if there are multiple Additional Standard Extensions is it needed to have an underscore.
The dt-binding does not validate that a multi-letter extension is canonically ordered, as that'd need an even worse regex than is here, but it should not fail validation for valid ISA strings.
Allow the first Z multi-letter extension to appear immediately prior after the single-letter extensions.
Link https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5Fixes 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")Acked-by Guo Ren <[email protected]>Signed-off-by Conor Dooley <[email protected]>---
Documentation/devicetree/bindings/riscv/cpus.yaml| 2 +-1 file changed, 1 insertion(+), 1 deletion(-)Documentation/devicetree/bindings/riscv/cpus.yaml +0
-0
Documentation/devicetree/bindings/riscv/cpus.yaml properties: · line 83
Quoted 5 lines
Documentation/devicetree/bindings/riscv/cpus.yaml +1
-1@@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
Isn’t it any multi-letter extension, i.e, this should be [hsxz] again?
It certainly used to be at least; we use rv64gcxcheri...
Jess
Re: [PATCH v2 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions
Quoted 36 lines · Jessica Clarke
Quoted 27 lines · Conor Dooley
From: Conor Dooley <[email protected]>
The RISC-V ISA Manual allows for the first Additional Standard Extension having no leading underscore. Only if there are multiple Additional Standard Extensions is it needed to have an underscore.
The dt-binding does not validate that a multi-letter extension is canonically ordered, as that'd need an even worse regex than is here, but it should not fail validation for valid ISA strings.
Allow the first Z multi-letter extension to appear immediately prior after the single-letter extensions.
Link https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5Fixes 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")Acked-by Guo Ren <[email protected]>Signed-off-by Conor Dooley <[email protected]>---
Documentation/devicetree/bindings/riscv/cpus.yaml| 2 +-1 file changed, 1 insertion(+), 1 deletion(-)Documentation/devicetree/bindings/riscv/cpus.yaml +0
-0Documentation/devicetree/bindings/riscv/cpus.yaml properties: · line 83
Quoted 5 lines
Documentation/devicetree/bindings/riscv/cpus.yaml +1
-1@@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$Isn’t it any multi-letter extension, i.e, this should be [hsxz] again?
Quoted 1 line
It certainly used to be at least; we use rv64gcxcheri...
<quote>
Non-standard extensions must be listed after all standard extensions. They must be separated from other multi-letter extensions by an underscore
<\quote>
Nope, you're right. I realised that the other day with the non-binding series that was a response to v1. I had that itching feeling that I had forgotten to do something when I was writing my changelog but could not remember what...
Thanks Jess!
PATCH v2 2/2 dt-bindings: riscv: fix single letter canonical order
In reply to Conor DooleyFrom: Conor Dooley <[email protected]>
I used the wikipedia table for ordering extensions when updating the pattern here in commit 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators").
Unfortunately that table did not match canonical order, as defined by the RISC-V ISA Manual, which defines extension ordering in (what is currently) Table 41, "Standard ISA extension names". Fix things up by re-sorting v (vector) and adding p (packed-simd) & j (dynamic languages). The e (reduced integer) and g (general) extensions are still intentionally left out.
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Documentation/devicetree/bindings/riscv/cpus.yaml +1 -1
@@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false
Signature · 1 line
2.38.1