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Add CRG driver for Hi3798MV100 SoC

PATCH Superseded David Yang 3 participants 11 messages Mar 4, 2023 – Mar 6, 2023

Subsystems (2)
Device tree bindings Common clk

v2 of 7 Superseded Latest is v7 →

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David Yang

author
#0 lore raw

v2 cover Add CRG driver for Hi3798MV100 SoC

This series adds CRG driver for Hi3798MV100 SoC.

v2: move bindings to a separate patch

David Yang (6):
clk: hisilicon: Rename Hi3798CV200 to Hi3798
clk: hisilicon: Extract common functions
dt-bindings: clock: Add Hi3798MV100 CRG driver binding
clk: hisilicon: Rename some symbols for Hi3798CV200
clk: hisilicon: Add inner clocks for Hi3798MV100
clk: hisilicon: Add CRG driver for Hi3798MV100 SoC

 .../devicetree/bindings/clock/hisi-crg.txt    |   2 +
 drivers/clk/hisilicon/Kconfig                 |   6 +-
 drivers/clk/hisilicon/Makefile                |   2 +-
 drivers/clk/hisilicon/crg-hi3798.c            | 612 ++++++++++++++++++
 drivers/clk/hisilicon/crg-hi3798cv200.c       | 401 ------------
 include/dt-bindings/clock/histb-clock.h       |  10 +
 6 files changed, 628 insertions(+), 405 deletions(-)
 create mode 100644 drivers/clk/hisilicon/crg-hi3798.c
 delete mode 100644 drivers/clk/hisilicon/crg-hi3798cv200.c
Signature · 1 line
2.39.2
author
#1 lore raw

PATCH v2 1/6 clk: hisilicon: Rename Hi3798CV200 to Hi3798

Rename Hisilicon Hi3798CV200 to Hi3798, to be reused with other Hi3798 series SoCs.

Signed-off-by David Yang <[email protected]>
---
 drivers/clk/hisilicon/Kconfig                 |   6 +-
 drivers/clk/hisilicon/Makefile                |   2 +-
 .../{crg-hi3798cv200.c => crg-hi3798.c}       | 151 +++++++++---------
 3 files changed, 80 insertions(+), 79 deletions(-)
 rename drivers/clk/hisilicon/{crg-hi3798cv200.c => crg-hi3798.c} (73%)
drivers/clk/hisilicon/Kconfig +3 -3
index c1ec75aa4..fa2d9920f 100644
@@ -37,13 +37,13 @@ config COMMON_CLK_HI3670
 	help
 	  Build the clock driver for hi3670.
 
-config COMMON_CLK_HI3798CV200
-	tristate "Hi3798CV200 Clock Driver"
+config COMMON_CLK_HI3798
+	tristate "Hi3798 Clock Driver"
 	depends on ARCH_HISI || COMPILE_TEST
 	select RESET_HISI
 	default ARCH_HISI
 	help
-	  Build the clock driver for hi3798cv200.
+	  Build the clock driver for hi3798.
 
 config COMMON_CLK_HI6220
 	bool "Hi6220 Clock Driver"
drivers/clk/hisilicon/Makefile +1 -1
index 2978e56cb..cfef47a19 100644
@@ -13,7 +13,7 @@ obj-$(CONFIG_COMMON_CLK_HI3519)	+= clk-hi3519.o
 obj-$(CONFIG_COMMON_CLK_HI3559A)	+= clk-hi3559a.o
 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
 obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
-obj-$(CONFIG_COMMON_CLK_HI3798CV200)	+= crg-hi3798cv200.o
+obj-$(CONFIG_COMMON_CLK_HI3798)	+= crg-hi3798.o
 obj-$(CONFIG_COMMON_CLK_HI6220)	+= clk-hi6220.o
 obj-$(CONFIG_RESET_HISI)	+= reset.o
 obj-$(CONFIG_STUB_CLK_HI6220)	+= clk-hi6220-stub.o
drivers/clk/hisilicon/crg-hi3798.c renamed from drivers/clk/hisilicon/crg-hi3798cv200.c +76 -75

255 lines not on this page · raw message

Signature · 1 line
2.39.2
#2 lore raw

Re: [PATCH v2 1/6] clk: hisilicon: Rename Hi3798CV200 to Hi3798

Quoted 288 lines · David Yang

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Rename Hisilicon Hi3798CV200 to Hi3798, to be reused with other Hi3798 series SoCs.

Signed-off-by David Yang <[email protected]>
---
 drivers/clk/hisilicon/Kconfig                 |   6 +-
 drivers/clk/hisilicon/Makefile                |   2 +-
 .../{crg-hi3798cv200.c => crg-hi3798.c}       | 151 +++++++++---------
 3 files changed, 80 insertions(+), 79 deletions(-)
 rename drivers/clk/hisilicon/{crg-hi3798cv200.c => crg-hi3798.c} (73%)
drivers/clk/hisilicon/Kconfig +3 -3
index c1ec75aa4..fa2d9920f 100644
@@ -37,13 +37,13 @@ config COMMON_CLK_HI3670
        help
          Build the clock driver for hi3670.
 
-config COMMON_CLK_HI3798CV200
-       tristate "Hi3798CV200 Clock Driver"
+config COMMON_CLK_HI3798
+       tristate "Hi3798 Clock Driver"
        depends on ARCH_HISI || COMPILE_TEST
        select RESET_HISI
        default ARCH_HISI
        help
-         Build the clock driver for hi3798cv200.
+         Build the clock driver for hi3798.
 
 config COMMON_CLK_HI6220
        bool "Hi6220 Clock Driver"
drivers/clk/hisilicon/Makefile +1 -1
index 2978e56cb..cfef47a19 100644
@@ -13,7 +13,7 @@ obj-$(CONFIG_COMMON_CLK_HI3519)       += clk-hi3519.o
 obj-$(CONFIG_COMMON_CLK_HI3559A)       += clk-hi3559a.o
 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
 obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
-obj-$(CONFIG_COMMON_CLK_HI3798CV200)   += crg-hi3798cv200.o
+obj-$(CONFIG_COMMON_CLK_HI3798)        += crg-hi3798.o
 obj-$(CONFIG_COMMON_CLK_HI6220)        += clk-hi6220.o
 obj-$(CONFIG_RESET_HISI)       += reset.o
 obj-$(CONFIG_STUB_CLK_HI6220)  += clk-hi6220-stub.o
drivers/clk/hisilicon/crg-hi3798.c renamed from drivers/clk/hisilicon/crg-hi3798cv200.c +63 -65
similarity index 73%
rename from drivers/clk/hisilicon/crg-hi3798cv200.c
rename to drivers/clk/hisilicon/crg-hi3798.c
index 08a19ba77..bdce43fbe 100644
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Hi3798CV200 Clock and Reset Generator Driver
+ * Hi3798 Clock and Reset Generator Driver
  *
  * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
  */

@@ -14,49 +14,49 @@
 #include "crg.h"
 #include "reset.h"
 
-/* hi3798CV200 core CRG */
-#define HI3798CV200_INNER_CLK_OFFSET           64
-#define HI3798CV200_FIXED_24M                  65
-#define HI3798CV200_FIXED_25M                  66
-#define HI3798CV200_FIXED_50M                  67
-#define HI3798CV200_FIXED_75M                  68
-#define HI3798CV200_FIXED_100M                 69
-#define HI3798CV200_FIXED_150M                 70
-#define HI3798CV200_FIXED_200M                 71
-#define HI3798CV200_FIXED_250M                 72
-#define HI3798CV200_FIXED_300M                 73
-#define HI3798CV200_FIXED_400M                 74
-#define HI3798CV200_MMC_MUX                    75
-#define HI3798CV200_ETH_PUB_CLK                        76
-#define HI3798CV200_ETH_BUS_CLK                        77
-#define HI3798CV200_ETH_BUS0_CLK               78
-#define HI3798CV200_ETH_BUS1_CLK               79
-#define HI3798CV200_COMBPHY1_MUX               80
-#define HI3798CV200_FIXED_12M                  81
-#define HI3798CV200_FIXED_48M                  82
-#define HI3798CV200_FIXED_60M                  83
-#define HI3798CV200_FIXED_166P5M               84
-#define HI3798CV200_SDIO0_MUX                  85
-#define HI3798CV200_COMBPHY0_MUX               86
-
-#define HI3798CV200_CRG_NR_CLKS                        128
-
-static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
+/* hi3798 core CRG */
+#define HI3798_INNER_CLK_OFFSET                64
+#define HI3798_FIXED_24M                       65
+#define HI3798_FIXED_25M                       66
+#define HI3798_FIXED_50M                       67
+#define HI3798_FIXED_75M                       68
+#define HI3798_FIXED_100M                      69
+#define HI3798_FIXED_150M                      70
+#define HI3798_FIXED_200M                      71
+#define HI3798_FIXED_250M                      72
+#define HI3798_FIXED_300M                      73
+#define HI3798_FIXED_400M                      74
+#define HI3798_MMC_MUX                 75
+#define HI3798_ETH_PUB_CLK                     76
+#define HI3798_ETH_BUS_CLK                     77
+#define HI3798_ETH_BUS0_CLK            78
+#define HI3798_ETH_BUS1_CLK            79
+#define HI3798_COMBPHY1_MUX            80
+#define HI3798_FIXED_12M                       81
+#define HI3798_FIXED_48M                       82
+#define HI3798_FIXED_60M                       83
+#define HI3798_FIXED_166P5M            84
+#define HI3798_SDIO0_MUX                       85
+#define HI3798_COMBPHY0_MUX            86
+
+#define HI3798_CRG_NR_CLKS                     128
+
+static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = {
        { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
        { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
        { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
-       { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
-       { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
-       { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
-       { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
-       { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
-       { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
-       { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
-       { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
-       { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
-       { HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, },
-       { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
-       { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
+       { HI3798_FIXED_12M, "12m", NULL, 0, 12000000, },
+       { HI3798_FIXED_24M, "24m", NULL, 0, 24000000, },
+       { HI3798_FIXED_25M, "25m", NULL, 0, 25000000, },
+       { HI3798_FIXED_48M, "48m", NULL, 0, 48000000, },
+       { HI3798_FIXED_50M, "50m", NULL, 0, 50000000, },
+       { HI3798_FIXED_60M, "60m", NULL, 0, 60000000, },
+       { HI3798_FIXED_75M, "75m", NULL, 0, 75000000, },
+       { HI3798_FIXED_100M, "100m", NULL, 0, 100000000, },
+       { HI3798_FIXED_150M, "150m", NULL, 0, 150000000, },
+       { HI3798_FIXED_166P5M, "166p5m", NULL, 0, 165000000, },
+       { HI3798_FIXED_200M, "200m", NULL, 0, 200000000, },
+       { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, },
 };
 
 static const char *const mmc_mux_p[] = {

@@ -72,15 +72,15 @@ static const char *const sdio_mux_p[] = {
 static u32 sdio_mux_table[] = {0, 1, 2, 3};
 
 static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
-       { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
+       { HI3798_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
                CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
-       { HI3798CV200_COMBPHY0_MUX, "combphy0_mux",
+       { HI3798_COMBPHY0_MUX, "combphy0_mux",
                comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
                CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
-       { HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
+       { HI3798_COMBPHY1_MUX, "combphy1_mux",
                comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
                CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
-       { HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
+       { HI3798_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
                ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
                0x9c, 8, 2, 0, sdio_mux_table, },
 };

@@ -135,13 +135,13 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
        { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m",
                CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
        /* Ethernet */
-       { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL,
+       { HI3798_ETH_PUB_CLK, "clk_pub", NULL,
                CLK_SET_RATE_PARENT, 0xcc, 5, 0, },
-       { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub",
+       { HI3798_ETH_BUS_CLK, "clk_bus", "clk_pub",
                CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
-       { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus",
+       { HI3798_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus",
                CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
-       { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus",
+       { HI3798_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus",
                CLK_SET_RATE_PARENT, 0xcc, 2, 0, },
        { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0",
                CLK_SET_RATE_PARENT, 0xcc, 3, 0, },

@@ -199,7 +199,7 @@ static struct hisi_clock_data *hi3798cv200_clk_register(
        struct hisi_clock_data *clk_data;
        int ret;
 
-       clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS);
+       clk_data = hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS);
        if (!clk_data)
                return ERR_PTR(-ENOMEM);
 

@@ -211,8 +211,8 @@ static struct hisi_clock_data *hi3798cv200_clk_register(
        if (ret)
                return ERR_PTR(ret);
 
-       ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,
-                                    ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
+       ret = hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks,
+                                    ARRAY_SIZE(hi3798_fixed_rate_clks),
                                     clk_data);
        if (ret)
                return ERR_PTR(ret);

@@ -245,8 +245,8 @@ static struct hisi_clock_data *hi3798cv200_clk_register(
                                ARRAY_SIZE(hi3798cv200_mux_clks),
                                clk_data);
 unregister_fixed_rate:
-       hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
-                               ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
+       hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks,
+                               ARRAY_SIZE(hi3798_fixed_rate_clks),
                                clk_data);
        return ERR_PTR(ret);
 }

@@ -263,8 +263,8 @@ static void hi3798cv200_clk_unregister(struct platform_device *pdev)
        hisi_clk_unregister_mux(hi3798cv200_mux_clks,
                                ARRAY_SIZE(hi3798cv200_mux_clks),
                                crg->clk_data);
-       hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
-                               ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
+       hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks,
+                               ARRAY_SIZE(hi3798_fixed_rate_clks),
                                crg->clk_data);
 }
 

@@ -273,9 +273,9 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
        .unregister_clks = hi3798cv200_clk_unregister,
 };
 
-/* hi3798CV200 sysctrl CRG */
+/* hi3798 sysctrl CRG */
 
-#define HI3798CV200_SYSCTRL_NR_CLKS 16
+#define HI3798_SYSCTRL_NR_CLKS 16
 
 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
        { HISTB_IR_CLK, "clk_ir", "24m",

@@ -292,7 +292,7 @@ static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
        struct hisi_clock_data *clk_data;
        int ret;
 
-       clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
+       clk_data = hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS);
        if (!clk_data)
                return ERR_PTR(-ENOMEM);
 

@@ -332,16 +332,16 @@ static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
        .unregister_clks = hi3798cv200_sysctrl_clk_unregister,
 };
 
-static const struct of_device_id hi3798cv200_crg_match_table[] = {
+static const struct of_device_id hi3798_crg_match_table[] = {
        { .compatible = "hisilicon,hi3798cv200-crg",
                .data = &hi3798cv200_crg_funcs },
        { .compatible = "hisilicon,hi3798cv200-sysctrl",
                .data = &hi3798cv200_sysctrl_funcs },
        { }
 };
-MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table);
+MODULE_DEVICE_TABLE(of, hi3798_crg_match_table);
 
-static int hi3798cv200_crg_probe(struct platform_device *pdev)
+static int hi3798_crg_probe(struct platform_device *pdev)
 {
        struct hisi_crg_dev *crg;
 

@@ -367,7 +367,7 @@ static int hi3798cv200_crg_probe(struct platform_device *pdev)
        return 0;
 }
 
-static int hi3798cv200_crg_remove(struct platform_device *pdev)
+static int hi3798_crg_remove(struct platform_device *pdev)
 {
        struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
 

@@ -376,26 +376,27 @@ static int hi3798cv200_crg_remove(struct platform_device *pdev)
        return 0;
 }
 
-static struct platform_driver hi3798cv200_crg_driver = {
-       .probe          = hi3798cv200_crg_probe,

drivers/clk/hisilicon/crg-hi3798.c static int hi3798cv200_crg_remove(struct platform_device *pdev) · line 385

Quoted 10 lines
drivers/clk/hisilicon/crg-hi3798.c renamed from drivers/clk/hisilicon/crg-hi3798cv200.c +6 -3
-       .remove         = hi3798cv200_crg_remove,
+static struct platform_driver hi3798_crg_driver = {
+       .probe          = hi3798_crg_probe,
+       .remove         = hi3798_crg_remove,
        .driver         = {
-               .name   = "hi3798cv200-crg",
-               .of_match_table = hi3798cv200_crg_match_table,
+               .name   = "hi3798-crg",
+               .of_match_table = hi3798_crg_match_table,
+               .of_match_table = hi3798_crg_match_table,

These 2 lines are identical. One should be enough...

Quoted 27 lines
drivers/clk/hisilicon/crg-hi3798.c renamed from drivers/clk/hisilicon/crg-hi3798cv200.c +7 -8
        },
 };
 
-static int __init hi3798cv200_crg_init(void)
+static int __init hi3798_crg_init(void)
 {
-       return platform_driver_register(&hi3798cv200_crg_driver);
+       return platform_driver_register(&hi3798_crg_driver);
 }
-core_initcall(hi3798cv200_crg_init);
+core_initcall(hi3798_crg_init);
 
-static void __exit hi3798cv200_crg_exit(void)
+static void __exit hi3798_crg_exit(void)
 {
-       platform_driver_unregister(&hi3798cv200_crg_driver);
+       platform_driver_unregister(&hi3798_crg_driver);
 }
-module_exit(hi3798cv200_crg_exit);
+module_exit(hi3798_crg_exit);
 
 MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver");
+MODULE_DESCRIPTION("HiSilicon Hi3798 CRG Driver");
--

2.39.2

author
#3 lore raw

PATCH v2 2/6 clk: hisilicon: Extract common functions

In reply to David Yang

To be reused with other Hi3798 series SoCs.

Signed-off-by David Yang <[email protected]>
---
 drivers/clk/hisilicon/crg-hi3798.c | 238 ++++++++++++++++-------------
 1 file changed, 136 insertions(+), 102 deletions(-)
drivers/clk/hisilicon/crg-hi3798.c +136 -102
index bdce43fbe..9c933172b 100644
@@ -59,6 +59,124 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = {
 	{ HI3798_FIXED_250M, "250m", NULL, 0, 250000000, },
 };
 
+struct hi3798_crg_clks {
+	const struct hisi_phase_clock *phase_clks;
+	int phase_clks_nums;
+	const struct hisi_mux_clock *mux_clks;
+	int mux_clks_nums;
+	const struct hisi_gate_clock *gate_clks;
+	int gate_clks_nums;
+};
+
+static struct hisi_clock_data *hi3798_clk_register(
+		struct platform_device *pdev, const struct hi3798_crg_clks *clks)
+{
+	struct hisi_clock_data *clk_data;
+	int ret;
+
+	clk_data = hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS);
+	if (!clk_data)
+		return ERR_PTR(-ENOMEM);
+
+	/* hisi_phase_clock is resource managed */
+	ret = hisi_clk_register_phase(&pdev->dev, clks->phase_clks,
+				      clks->phase_clks_nums, clk_data);
+	if (ret)
+		return ERR_PTR(ret);
+
+	ret = hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks,
+					   ARRAY_SIZE(hi3798_fixed_rate_clks),
+					   clk_data);
+	if (ret)
+		return ERR_PTR(ret);
+
+	ret = hisi_clk_register_mux(clks->mux_clks, clks->mux_clks_nums, clk_data);
+	if (ret)
+		goto unregister_fixed_rate;
+
+	ret = hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk_data);
+	if (ret)
+		goto unregister_mux;
+
+	ret = of_clk_add_provider(pdev->dev.of_node,
+			of_clk_src_onecell_get, &clk_data->clk_data);
+	if (ret)
+		goto unregister_gate;
+
+	return clk_data;
+
+unregister_gate:
+	hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data);
+unregister_mux:
+	hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, clk_data);
+unregister_fixed_rate:
+	hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks,
+				       ARRAY_SIZE(hi3798_fixed_rate_clks),
+				       clk_data);
+	return ERR_PTR(ret);
+}
+
+static void hi3798_clk_unregister(
+		struct platform_device *pdev, const struct hi3798_crg_clks *clks)
+{
+	struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+	of_clk_del_provider(pdev->dev.of_node);
+
+	hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_data);
+	hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, crg->clk_data);
+	hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks,
+				       ARRAY_SIZE(hi3798_fixed_rate_clks),
+				       crg->clk_data);
+}
+
+/* hi3798 sysctrl CRG */
+
+#define HI3798_SYSCTRL_NR_CLKS 16
+
+struct hi3798_sysctrl_clks {
+	const struct hisi_gate_clock *gate_clks;
+	int gate_clks_nums;
+};
+
+static struct hisi_clock_data *hi3798_sysctrl_clk_register(
+		struct platform_device *pdev, const struct hi3798_sysctrl_clks *clks)
+{
+	struct hisi_clock_data *clk_data;
+	int ret;
+
+	clk_data = hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS);
+	if (!clk_data)
+		return ERR_PTR(-ENOMEM);
+
+	ret = hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk_data);
+	if (ret)
+		return ERR_PTR(ret);
+
+	ret = of_clk_add_provider(pdev->dev.of_node,
+			of_clk_src_onecell_get, &clk_data->clk_data);
+	if (ret)
+		goto unregister_gate;
+
+	return clk_data;
+
+unregister_gate:
+	hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data);
+	return ERR_PTR(ret);
+}
+
+static void hi3798_sysctrl_clk_unregister(
+		struct platform_device *pdev, const struct hi3798_sysctrl_clks *clks)
+{
+	struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+	of_clk_del_provider(pdev->dev.of_node);
+
+	hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_data);
+}
+
+/* hi3798CV200 */
+
 static const char *const mmc_mux_p[] = {
 		"100m", "50m", "25m", "200m", "150m" };
 static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};

@@ -193,79 +311,24 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
 		CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
 };
 
+static const struct hi3798_crg_clks hi3798cv200_crg_clks_data = {
+	.phase_clks = hi3798cv200_phase_clks,
+	.phase_clks_nums = ARRAY_SIZE(hi3798cv200_phase_clks),
+	.mux_clks = hi3798cv200_mux_clks,
+	.mux_clks_nums = ARRAY_SIZE(hi3798cv200_mux_clks),
+	.gate_clks = hi3798cv200_gate_clks,
+	.gate_clks_nums = ARRAY_SIZE(hi3798cv200_gate_clks),
+};
+
 static struct hisi_clock_data *hi3798cv200_clk_register(
 				struct platform_device *pdev)
 {
-	struct hisi_clock_data *clk_data;
-	int ret;
-
-	clk_data = hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS);
-	if (!clk_data)
-		return ERR_PTR(-ENOMEM);
-
-	/* hisi_phase_clock is resource managed */
-	ret = hisi_clk_register_phase(&pdev->dev,
-				hi3798cv200_phase_clks,
-				ARRAY_SIZE(hi3798cv200_phase_clks),
-				clk_data);
-	if (ret)
-		return ERR_PTR(ret);
-
-	ret = hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks,
-				     ARRAY_SIZE(hi3798_fixed_rate_clks),
-				     clk_data);
-	if (ret)
-		return ERR_PTR(ret);
-
-	ret = hisi_clk_register_mux(hi3798cv200_mux_clks,
-				ARRAY_SIZE(hi3798cv200_mux_clks),
-				clk_data);
-	if (ret)
-		goto unregister_fixed_rate;
-
-	ret = hisi_clk_register_gate(hi3798cv200_gate_clks,
-				ARRAY_SIZE(hi3798cv200_gate_clks),
-				clk_data);
-	if (ret)
-		goto unregister_mux;
-
-	ret = of_clk_add_provider(pdev->dev.of_node,
-			of_clk_src_onecell_get, &clk_data->clk_data);
-	if (ret)
-		goto unregister_gate;
-
-	return clk_data;
-
-unregister_gate:
-	hisi_clk_unregister_gate(hi3798cv200_gate_clks,
-				ARRAY_SIZE(hi3798cv200_gate_clks),
-				clk_data);
-unregister_mux:
-	hisi_clk_unregister_mux(hi3798cv200_mux_clks,
-				ARRAY_SIZE(hi3798cv200_mux_clks),
-				clk_data);
-unregister_fixed_rate:
-	hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks,
-				ARRAY_SIZE(hi3798_fixed_rate_clks),
-				clk_data);
-	return ERR_PTR(ret);
+	return hi3798_clk_register(pdev, &hi3798cv200_crg_clks_data);
 }
 
 static void hi3798cv200_clk_unregister(struct platform_device *pdev)
 {
-	struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
-	of_clk_del_provider(pdev->dev.of_node);
-
-	hisi_clk_unregister_gate(hi3798cv200_gate_clks,
-				ARRAY_SIZE(hi3798cv200_gate_clks),
-				crg->clk_data);
-	hisi_clk_unregister_mux(hi3798cv200_mux_clks,
-				ARRAY_SIZE(hi3798cv200_mux_clks),
-				crg->clk_data);
-	hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks,
-				ARRAY_SIZE(hi3798_fixed_rate_clks),
-				crg->clk_data);
+	hi3798_clk_unregister(pdev, &hi3798cv200_crg_clks_data);
 }
 
 static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {

@@ -273,10 +336,6 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
 	.unregister_clks = hi3798cv200_clk_unregister,
 };
 
-/* hi3798 sysctrl CRG */
-
-#define HI3798_SYSCTRL_NR_CLKS 16
-
 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
 	{ HISTB_IR_CLK, "clk_ir", "24m",
 		CLK_SET_RATE_PARENT, 0x48, 4, 0, },

@@ -286,45 +345,20 @@ static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
 		CLK_SET_RATE_PARENT, 0x48, 10, 0, },
 };
 
+static const struct hi3798_sysctrl_clks hi3798cv200_sysctrl_clks_data = {
+	.gate_clks = hi3798cv200_sysctrl_gate_clks,
+	.gate_clks_nums = ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
+};
+
 static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
 					struct platform_device *pdev)
 {
-	struct hisi_clock_data *clk_data;
-	int ret;
-
-	clk_data = hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS);
-	if (!clk_data)
-		return ERR_PTR(-ENOMEM);
-
-	ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
-				ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
-				clk_data);
-	if (ret)
-		return ERR_PTR(ret);
-
-	ret = of_clk_add_provider(pdev->dev.of_node,
-			of_clk_src_onecell_get, &clk_data->clk_data);
-	if (ret)
-		goto unregister_gate;
-
-	return clk_data;
-
-unregister_gate:
-	hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
-				ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
-				clk_data);
-	return ERR_PTR(ret);
+	return hi3798_sysctrl_clk_register(pdev, &hi3798cv200_sysctrl_clks_data);
 }
 
 static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
 {
-	struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
-	of_clk_del_provider(pdev->dev.of_node);
-
-	hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
-				ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
-				crg->clk_data);
+	hi3798_sysctrl_clk_unregister(pdev, &hi3798cv200_sysctrl_clks_data);
 }
 
 static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
Signature · 1 line
2.39.2
author
#4 lore raw

PATCH v2 3/6 dt-bindings: clk: Add Hi3798MV100 CRG driver binding

In reply to David Yang

Add CRG driver for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC.

Signed-off-by David Yang <[email protected]>
---
 Documentation/devicetree/bindings/clock/hisi-crg.txt |  2 ++
 include/dt-bindings/clock/histb-clock.h              | 10 ++++++++++
 2 files changed, 12 insertions(+)
Documentation/devicetree/bindings/clock/hisi-crg.txt +2 -0
index cc60b3d42..972c038c8 100644
@@ -13,6 +13,8 @@ Required Properties:
   - "hisilicon,hi3516cv300-crg"
   - "hisilicon,hi3516cv300-sysctrl"
   - "hisilicon,hi3519-crg"
+  - "hisilicon,hi3798mv100-crg"
+  - "hisilicon,hi3798mv100-sysctrl"
   - "hisilicon,hi3798cv200-crg"
   - "hisilicon,hi3798cv200-sysctrl"
include/dt-bindings/clock/histb-clock.h +10 -0
index e64e5770a..5042c2a7a 100644
@@ -58,6 +58,16 @@
 #define HISTB_USB3_UTMI_CLK1		48
 #define HISTB_USB3_PIPE_CLK1		49
 #define HISTB_USB3_SUSPEND_CLK1		50
+#define HISTB_USB2_UTMI_CLK1		51
+#define HISTB_USB2_2_BUS_CLK		52
+#define HISTB_USB2_2_PHY_CLK		53
+#define HISTB_USB2_2_UTMI_CLK		54
+#define HISTB_USB2_2_UTMI_CLK1		55
+#define HISTB_USB2_2_12M_CLK		56
+#define HISTB_USB2_2_48M_CLK		57
+#define HISTB_USB2_2_OTG_UTMI_CLK		58
+#define HISTB_USB2_2_PHY1_REF_CLK		59
+#define HISTB_USB2_2_PHY2_REF_CLK		60
 
 /* clocks provided by mcu CRG */
 #define HISTB_MCE_CLK			1
Signature · 1 line
2.39.2
Acked-by on v2 3/6
#5 lore raw

Re: [PATCH v2 3/6] dt-bindings: clk: Add Hi3798MV100 CRG driver binding

Quoted 2 lines · David Yang

Add CRG driver for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC.

Subject: drop second/last, redundant "binding". The "dt-bindings" prefix is already stating that these are bindings.

Drop also "driver". Bindings are for hardware, not driver.

Quoted 1 line

With both above:

Acked-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

author
#6 lore raw

PATCH v2 3/6 dt-bindings: clock: Add Hi3798MV100 CRG driver binding

In reply to David Yang

Add CRG driver for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC.

Signed-off-by David Yang <[email protected]>
---
 Documentation/devicetree/bindings/clock/hisi-crg.txt |  2 ++
 include/dt-bindings/clock/histb-clock.h              | 10 ++++++++++
 2 files changed, 12 insertions(+)
Documentation/devicetree/bindings/clock/hisi-crg.txt +2 -0
index cc60b3d42..972c038c8 100644
@@ -13,6 +13,8 @@ Required Properties:
   - "hisilicon,hi3516cv300-crg"
   - "hisilicon,hi3516cv300-sysctrl"
   - "hisilicon,hi3519-crg"
+  - "hisilicon,hi3798mv100-crg"
+  - "hisilicon,hi3798mv100-sysctrl"
   - "hisilicon,hi3798cv200-crg"
   - "hisilicon,hi3798cv200-sysctrl"
include/dt-bindings/clock/histb-clock.h +10 -0
index e64e5770a..5042c2a7a 100644
@@ -58,6 +58,16 @@
 #define HISTB_USB3_UTMI_CLK1		48
 #define HISTB_USB3_PIPE_CLK1		49
 #define HISTB_USB3_SUSPEND_CLK1		50
+#define HISTB_USB2_UTMI_CLK1		51
+#define HISTB_USB2_2_BUS_CLK		52
+#define HISTB_USB2_2_PHY_CLK		53
+#define HISTB_USB2_2_UTMI_CLK		54
+#define HISTB_USB2_2_UTMI_CLK1		55
+#define HISTB_USB2_2_12M_CLK		56
+#define HISTB_USB2_2_48M_CLK		57
+#define HISTB_USB2_2_OTG_UTMI_CLK		58
+#define HISTB_USB2_2_PHY1_REF_CLK		59
+#define HISTB_USB2_2_PHY2_REF_CLK		60
 
 /* clocks provided by mcu CRG */
 #define HISTB_MCE_CLK			1
Signature · 1 line
2.39.2
Acked-by on v2 3/6
#7 lore raw

Re: [PATCH v2 3/6] dt-bindings: clock: Add Hi3798MV100 CRG driver binding

Quoted 5 lines · David Yang

Add CRG driver for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC.

Signed-off-by David Yang <[email protected]>

---

Same comments for subject as for previous patch. With fixes:

Acked-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

author
#8 lore raw

PATCH v2 4/6 clk: hisilicon: Rename some symbols for Hi3798CV200

In reply to David Yang

These symbols might cause confusion when adding support for other Hi3798 series SoCs.

Signed-off-by David Yang <[email protected]>
---
 drivers/clk/hisilicon/crg-hi3798.c | 35 +++++++++++++++---------------
 1 file changed, 18 insertions(+), 17 deletions(-)
drivers/clk/hisilicon/crg-hi3798.c +18 -17
index 9c933172b..b52d44350 100644
@@ -177,30 +177,31 @@ static void hi3798_sysctrl_clk_unregister(
 
 /* hi3798CV200 */
 
-static const char *const mmc_mux_p[] = {
+static const char *const hi3798cv200_mmc_mux_p[] = {
 		"100m", "50m", "25m", "200m", "150m" };
-static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
+static u32 hi3798cv200_mmc_mux_table[] = {0, 1, 2, 3, 6};
 
-static const char *const comphy_mux_p[] = {
+static const char *const hi3798cv200_comphy_mux_p[] = {
 		"100m", "25m"};
-static u32 comphy_mux_table[] = {2, 3};
+static u32 hi3798cv200_comphy_mux_table[] = {2, 3};
 
-static const char *const sdio_mux_p[] = {
+static const char *const hi3798cv200_sdio_mux_p[] = {
 		"100m", "50m", "150m", "166p5m" };
-static u32 sdio_mux_table[] = {0, 1, 2, 3};
+static u32 hi3798cv200_sdio_mux_table[] = {0, 1, 2, 3};
 
 static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
-	{ HI3798_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-		CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
-	{ HI3798_COMBPHY0_MUX, "combphy0_mux",
-		comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
-		CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
-	{ HI3798_COMBPHY1_MUX, "combphy1_mux",
-		comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
-		CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
-	{ HI3798_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
-		ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
-		0x9c, 8, 2, 0, sdio_mux_table, },
+	{ HI3798_MMC_MUX, "mmc_mux", hi3798cv200_mmc_mux_p,
+		ARRAY_SIZE(hi3798cv200_mmc_mux_p), CLK_SET_RATE_PARENT,
+		0xa0, 8, 3, 0, hi3798cv200_mmc_mux_table, },
+	{ HI3798_COMBPHY0_MUX, "combphy0_mux", hi3798cv200_comphy_mux_p,
+		ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT,
+		0x188, 2, 2, 0, hi3798cv200_comphy_mux_table, },
+	{ HI3798_COMBPHY1_MUX, "combphy1_mux", hi3798cv200_comphy_mux_p,
+		ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT,
+		0x188, 10, 2, 0, hi3798cv200_comphy_mux_table, },
+	{ HI3798_SDIO0_MUX, "sdio0_mux", hi3798cv200_sdio_mux_p,
+		ARRAY_SIZE(hi3798cv200_sdio_mux_p), CLK_SET_RATE_PARENT,
+		0x9c, 8, 2, 0, hi3798cv200_sdio_mux_table, },
 };
 
 static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7};
Signature · 1 line
2.39.2
author
#9 lore raw

PATCH v2 5/6 clk: hisilicon: Add inner clocks for Hi3798MV100

In reply to David Yang

These are inner clocks for Hi3798MV100, but not exist on Hi3798CV200.

Signed-off-by David Yang <[email protected]>
---
 drivers/clk/hisilicon/crg-hi3798.c | 6 ++++++
 1 file changed, 6 insertions(+)
drivers/clk/hisilicon/crg-hi3798.c +6 -0
index b52d44350..8a6e978f3 100644
@@ -38,6 +38,9 @@
 #define HI3798_FIXED_166P5M		84
 #define HI3798_SDIO0_MUX			85
 #define HI3798_COMBPHY0_MUX		86
+#define HI3798_FIXED_3M				87
+#define HI3798_FIXED_15M			88
+#define HI3798_FIXED_83P3M			89
 
 #define HI3798_CRG_NR_CLKS			128
 

@@ -45,13 +48,16 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = {
 	{ HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
 	{ HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
 	{ HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
+	{ HI3798_FIXED_3M, "3m", NULL, 0, 3000000, },
 	{ HI3798_FIXED_12M, "12m", NULL, 0, 12000000, },
+	{ HI3798_FIXED_15M, "15m", NULL, 0, 15000000, },
 	{ HI3798_FIXED_24M, "24m", NULL, 0, 24000000, },
 	{ HI3798_FIXED_25M, "25m", NULL, 0, 25000000, },
 	{ HI3798_FIXED_48M, "48m", NULL, 0, 48000000, },
 	{ HI3798_FIXED_50M, "50m", NULL, 0, 50000000, },
 	{ HI3798_FIXED_60M, "60m", NULL, 0, 60000000, },
 	{ HI3798_FIXED_75M, "75m", NULL, 0, 75000000, },
+	{ HI3798_FIXED_83P3M, "83p3m", NULL, 0, 83333333, },
 	{ HI3798_FIXED_100M, "100m", NULL, 0, 100000000, },
 	{ HI3798_FIXED_150M, "150m", NULL, 0, 150000000, },
 	{ HI3798_FIXED_166P5M, "166p5m", NULL, 0, 165000000, },
Signature · 1 line
2.39.2
author
#10 lore raw

PATCH v2 6/6 clk: hisilicon: Add CRG driver for Hi3798MV100 SoC

In reply to David Yang

Add CRG driver for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC.

Signed-off-by David Yang <[email protected]>
---
 drivers/clk/hisilicon/crg-hi3798.c | 197 +++++++++++++++++++++++++++--
 1 file changed, 183 insertions(+), 14 deletions(-)
drivers/clk/hisilicon/crg-hi3798.c +183 -14
index 8a6e978f3..ad10b3bb5 100644
@@ -41,6 +41,7 @@
 #define HI3798_FIXED_3M				87
 #define HI3798_FIXED_15M			88
 #define HI3798_FIXED_83P3M			89
+#define HI3798_ETH_MUX			90
 
 #define HI3798_CRG_NR_CLKS			128
 

@@ -181,6 +182,182 @@ static void hi3798_sysctrl_clk_unregister(
 	hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_data);
 }
 
+/* hi3798MV100 */
+
+static const char *const hi3798mv100_mmc_mux_p[] = {
+		"75m", "100m", "50m", "15m" };
+static u32 hi3798mv100_mmc_mux_table[] = {0, 1, 2, 3};
+
+static const char *const hi3798mv100_eth_mux_p[] = {
+		"83p3m" };
+static u32 hi3798mv100_eth_mux_table[] = {2};
+
+static struct hisi_mux_clock hi3798mv100_mux_clks[] = {
+	{ HI3798_MMC_MUX, "mmc_mux", hi3798mv100_mmc_mux_p,
+		ARRAY_SIZE(hi3798mv100_mmc_mux_p), CLK_SET_RATE_PARENT,
+		0xa0, 8, 2, 0, hi3798mv100_mmc_mux_table, },
+	{ HI3798_SDIO0_MUX, "sdio0_mux", hi3798mv100_mmc_mux_p,
+		ARRAY_SIZE(hi3798mv100_mmc_mux_p), CLK_SET_RATE_PARENT,
+		0x9c, 8, 2, 0, hi3798mv100_mmc_mux_table, },
+	{ HI3798_ETH_MUX, "eth_mux", hi3798mv100_eth_mux_p,
+		ARRAY_SIZE(hi3798mv100_eth_mux_p), CLK_SET_RATE_PARENT,
+		0xcc, 2, 2, 0, hi3798mv100_eth_mux_table, },
+};
+
+static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7};
+static u32 mmc_phase_degrees[] = {0, 45, 90, 135, 180, 225, 270, 315};
+
+static struct hisi_phase_clock hi3798mv100_phase_clks[] = {
+	{ HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu",
+		CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
+		mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
+	{ HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu",
+		CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
+		mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
+};
+
+static const struct hisi_gate_clock hi3798mv100_gate_clks[] = {
+	/* NAND */
+	/* hi3798MV100 NAND driver does not get into mainline yet,
+	 * expose these clocks when it gets ready */
+	/* { HISTB_NAND_CLK, "clk_nand", "clk_apb",
+		CLK_SET_RATE_PARENT, 0x60, 0, 0, }, */
+	/* UART */
+	{ HISTB_UART1_CLK, "clk_uart1", "3m",
+		CLK_SET_RATE_PARENT, 0x68, 0, 0, },
+	{ HISTB_UART2_CLK, "clk_uart2", "83p3m",
+		CLK_SET_RATE_PARENT, 0x68, 4, 0, },
+	/* I2C */
+	{ HISTB_I2C0_CLK, "clk_i2c0", "clk_apb",
+		CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
+	{ HISTB_I2C1_CLK, "clk_i2c1", "clk_apb",
+		CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
+	{ HISTB_I2C2_CLK, "clk_i2c2", "clk_apb",
+		CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
+	/* SPI */
+	{ HISTB_SPI0_CLK, "clk_spi0", "clk_apb",
+		CLK_SET_RATE_PARENT, 0x70, 0, 0, },
+	/* SDIO */
+	{ HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
+		CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
+	{ HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux",
+		CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
+	/* EMMC */
+	{ HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
+		CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
+	{ HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
+		CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
+	/* Ethernet */
+	/* hi3798MV100 Ethernet driver does not get into mainline yet,
+	 * expose these clocks when it gets ready */
+	{ HI3798_ETH_BUS_CLK, "clk_bus", NULL,
+		CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
+	{ HI3798_ETH_PUB_CLK, "clk_pub", "eth_mux",
+		CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
+	/* USB2 */
+	{ HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb",
+		CLK_SET_RATE_PARENT, 0xb8, 0, 0, },
+	{ HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m",
+		CLK_SET_RATE_PARENT, 0xb8, 4, 0, },
+	{ HISTB_USB2_12M_CLK, "clk_u2_12m", "12m",
+		CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
+	{ HISTB_USB2_48M_CLK, "clk_u2_48m", "48m",
+		CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
+	{ HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",
+		CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
+	{ HISTB_USB2_UTMI_CLK1, "clk_u2_utmi1", "60m",
+		CLK_SET_RATE_PARENT, 0xb8, 6, 0 },
+	{ HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m",
+		CLK_SET_RATE_PARENT, 0xb8, 3, 0 },
+	{ HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",
+		CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
+	{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
+		CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
+	/* USB2 2 */
+	{ HISTB_USB2_2_BUS_CLK, "clk_u2_2_bus", "clk_ahb",
+		CLK_SET_RATE_PARENT, 0x198, 0, 0, },
+	{ HISTB_USB2_2_PHY_CLK, "clk_u2_2_phy", "60m",
+		CLK_SET_RATE_PARENT, 0x198, 4, 0, },
+	{ HISTB_USB2_2_12M_CLK, "clk_u2_2_12m", "12m",
+		CLK_SET_RATE_PARENT, 0x198, 2, 0 },
+	{ HISTB_USB2_2_48M_CLK, "clk_u2_2_48m", "48m",
+		CLK_SET_RATE_PARENT, 0x198, 1, 0 },
+	{ HISTB_USB2_2_UTMI_CLK, "clk_u2_2_utmi", "60m",
+		CLK_SET_RATE_PARENT, 0x198, 5, 0 },
+	{ HISTB_USB2_2_UTMI_CLK1, "clk_u2_2_utmi1", "60m",
+		CLK_SET_RATE_PARENT, 0x198, 6, 0 },
+	{ HISTB_USB2_2_OTG_UTMI_CLK, "clk_u2_2_otg_utmi", "60m",
+		CLK_SET_RATE_PARENT, 0x198, 3, 0 },
+	{ HISTB_USB2_2_PHY1_REF_CLK, "clk_u2_2_phy1_ref", "24m",
+		CLK_SET_RATE_PARENT, 0x190, 0, 0 },
+	{ HISTB_USB2_2_PHY2_REF_CLK, "clk_u2_2_phy2_ref", "24m",
+		CLK_SET_RATE_PARENT, 0x190, 2, 0 },
+	/* USB3 */
+	{ HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL,
+		CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
+	{ HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL,
+		CLK_SET_RATE_PARENT, 0xb0, 4, 0 },
+	{ HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL,
+		CLK_SET_RATE_PARENT, 0xb0, 3, 0 },
+	{ HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL,
+		CLK_SET_RATE_PARENT, 0xb0, 2, 0 },
+};
+
+static const struct hi3798_crg_clks hi3798mv100_crg_clks_data = {
+	.phase_clks = hi3798mv100_phase_clks,
+	.phase_clks_nums = ARRAY_SIZE(hi3798mv100_phase_clks),
+	.mux_clks = hi3798mv100_mux_clks,
+	.mux_clks_nums = ARRAY_SIZE(hi3798mv100_mux_clks),
+	.gate_clks = hi3798mv100_gate_clks,
+	.gate_clks_nums = ARRAY_SIZE(hi3798mv100_gate_clks),
+};
+
+static struct hisi_clock_data *hi3798mv100_clk_register(
+				struct platform_device *pdev)
+{
+	return hi3798_clk_register(pdev, &hi3798mv100_crg_clks_data);
+}
+
+static void hi3798mv100_clk_unregister(struct platform_device *pdev)
+{
+	hi3798_clk_unregister(pdev, &hi3798mv100_crg_clks_data);
+}
+
+static const struct hisi_crg_funcs hi3798mv100_crg_funcs = {
+	.register_clks = hi3798mv100_clk_register,
+	.unregister_clks = hi3798mv100_clk_unregister,
+};
+
+static const struct hisi_gate_clock hi3798mv100_sysctrl_gate_clks[] = {
+	{ HISTB_IR_CLK, "clk_ir", "24m",
+		CLK_SET_RATE_PARENT, 0x48, 4, 0, },
+	{ HISTB_TIMER01_CLK, "clk_timer01", "24m",
+		CLK_SET_RATE_PARENT, 0x48, 6, 0, },
+	{ HISTB_UART0_CLK, "clk_uart0", "83p3m",
+		CLK_SET_RATE_PARENT, 0x48, 12, 0, },
+};
+
+static const struct hi3798_sysctrl_clks hi3798mv100_sysctrl_clks_data = {
+	.gate_clks = hi3798mv100_sysctrl_gate_clks,
+	.gate_clks_nums = ARRAY_SIZE(hi3798mv100_sysctrl_gate_clks),
+};
+
+static struct hisi_clock_data *hi3798mv100_sysctrl_clk_register(
+					struct platform_device *pdev)
+{
+	return hi3798_sysctrl_clk_register(pdev, &hi3798mv100_sysctrl_clks_data);
+}
+
+static void hi3798mv100_sysctrl_clk_unregister(struct platform_device *pdev)
+{
+	hi3798_sysctrl_clk_unregister(pdev, &hi3798mv100_sysctrl_clks_data);
+}
+
+static const struct hisi_crg_funcs hi3798mv100_sysctrl_funcs = {
+	.register_clks = hi3798mv100_sysctrl_clk_register,
+	.unregister_clks = hi3798mv100_sysctrl_clk_unregister,
+};
+
 /* hi3798CV200 */
 
 static const char *const hi3798cv200_mmc_mux_p[] = {

@@ -210,18 +387,6 @@ static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
 		0x9c, 8, 2, 0, hi3798cv200_sdio_mux_table, },
 };
 
-static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7};
-static u32 mmc_phase_degrees[] = {0, 45, 90, 135, 180, 225, 270, 315};
-
-static struct hisi_phase_clock hi3798cv200_phase_clks[] = {
-	{ HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu",
-		CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
-		mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
-	{ HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu",
-		CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
-		mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
-};
-
 static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
 	/* UART */
 	{ HISTB_UART2_CLK, "clk_uart2", "75m",

@@ -319,8 +484,8 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
 };
 
 static const struct hi3798_crg_clks hi3798cv200_crg_clks_data = {
-	.phase_clks = hi3798cv200_phase_clks,
-	.phase_clks_nums = ARRAY_SIZE(hi3798cv200_phase_clks),
+	.phase_clks = hi3798mv100_phase_clks,
+	.phase_clks_nums = ARRAY_SIZE(hi3798mv100_phase_clks),
 	.mux_clks = hi3798cv200_mux_clks,
 	.mux_clks_nums = ARRAY_SIZE(hi3798cv200_mux_clks),
 	.gate_clks = hi3798cv200_gate_clks,

@@ -374,6 +539,10 @@ static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
 };
 
 static const struct of_device_id hi3798_crg_match_table[] = {
+	{ .compatible = "hisilicon,hi3798mv100-crg",
+		.data = &hi3798mv100_crg_funcs },
+	{ .compatible = "hisilicon,hi3798mv100-sysctrl",
+		.data = &hi3798mv100_sysctrl_funcs },
 	{ .compatible = "hisilicon,hi3798cv200-crg",
 		.data = &hi3798cv200_crg_funcs },
 	{ .compatible = "hisilicon,hi3798cv200-sysctrl",
Signature · 1 line
2.39.2