Add CRG driver for Hi3798MV100 SoC
Subsystems (2)
v7 cover Add CRG driver for Hi3798MV100 SoC
This series adds CRG driver for Hi3798MV100 SoC.
v2: move bindings to a separate patch
v3: fix bindings commit message, reorganize patches
v4: add ethernet and gpu clocks
v5: add complex clock
v6: migrate devm api
v7: fix devm api migration as requested
Links:
v1: https://lore.kernel.org/r/[email protected]
v2: https://lore.kernel.org/r/[email protected]
v3: https://lore.kernel.org/r/[email protected]
v4: https://lore.kernel.org/r/[email protected]
v5: https://lore.kernel.org/r/[email protected]
v6: https://lore.kernel.org/r/[email protected]
David Yang (9):
clk: hisilicon: Rename Hi3798CV200 to Hi3798
clk: hisilicon: Extract common functions
clk: hisilicon: Remove hisi_clk_alloc
clk: hisilicon: Add helper functions for platform driver
clk: hisilicon: Use helper functions
clk: hisilicon: Convert to platform_driver
clk: hisilicon: Migrate devm APIs
dt-bindings: clock: Add Hi3798MV100 CRG
clk: hisilicon: Add CRG driver for Hi3798MV100 SoC
.../devicetree/bindings/clock/hisi-crg.txt | 2 + drivers/clk/hisilicon/Kconfig | 6 +- drivers/clk/hisilicon/Makefile | 2 +- drivers/clk/hisilicon/clk-hi3519.c | 134 +---- drivers/clk/hisilicon/clk-hi3559a.c | 253 ++------- drivers/clk/hisilicon/clk-hi3620.c | 214 ++++---- drivers/clk/hisilicon/clk-hi3660.c | 204 +++---- drivers/clk/hisilicon/clk-hi3670.c | 267 ++++------ drivers/clk/hisilicon/clk-hi6220-stub.c | 9 +- drivers/clk/hisilicon/clk-hi6220.c | 229 ++++---- drivers/clk/hisilicon/clk-hip04.c | 38 +- drivers/clk/hisilicon/clk-hisi-phase.c | 13 +- drivers/clk/hisilicon/clk-hix5hd2.c | 90 ++-- drivers/clk/hisilicon/clk.c | 428 ++++++++------- drivers/clk/hisilicon/clk.h | 146 +++-- drivers/clk/hisilicon/clkdivider-hi6220.c | 24 +- drivers/clk/hisilicon/clkgate-separated.c | 26 +- drivers/clk/hisilicon/crg-hi3516cv300.c | 177 +------ drivers/clk/hisilicon/crg-hi3798.c | 498 ++++++++++++++++++ drivers/clk/hisilicon/crg-hi3798cv200.c | 401 -------------- drivers/clk/hisilicon/crg.h | 11 +- drivers/clk/hisilicon/reset.c | 64 ++- include/dt-bindings/clock/histb-clock.h | 13 + 23 files changed, 1463 insertions(+), 1786 deletions(-) create mode 100644 drivers/clk/hisilicon/crg-hi3798.c delete mode 100644 drivers/clk/hisilicon/crg-hi3798cv200.c
base-commit: 6015b1aca1a233379625385feb01dd014aca60b5
Signature · 1 line
2.39.2
PATCH v7 1/9 clk: hisilicon: Rename Hi3798CV200 to Hi3798
Rename Hisilicon Hi3798CV200 to Hi3798, to be reused with other Hi3798 series SoCs.
Signed-off-by David Yang <[email protected]>
---
drivers/clk/hisilicon/Kconfig | 6 +-
drivers/clk/hisilicon/Makefile | 2 +-
.../{crg-hi3798cv200.c => crg-hi3798.c} | 181 +++++++++---------
3 files changed, 95 insertions(+), 94 deletions(-)
rename drivers/clk/hisilicon/{crg-hi3798cv200.c => crg-hi3798.c} (68%)drivers/clk/hisilicon/Kconfig +3 -3
@@ -37,13 +37,13 @@ config COMMON_CLK_HI3670 help Build the clock driver for hi3670. -config COMMON_CLK_HI3798CV200 - tristate "Hi3798CV200 Clock Driver" +config COMMON_CLK_HI3798 + tristate "Hi3798 Clock Driver" depends on ARCH_HISI || COMPILE_TEST select RESET_HISI default ARCH_HISI help - Build the clock driver for hi3798cv200. + Build the clock driver for hi3798. config COMMON_CLK_HI6220 bool "Hi6220 Clock Driver"
drivers/clk/hisilicon/Makefile +1 -1
@@ -13,7 +13,7 @@ obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o obj-$(CONFIG_COMMON_CLK_HI3559A) += clk-hi3559a.o obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o -obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o +obj-$(CONFIG_COMMON_CLK_HI3798) += crg-hi3798.o obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o obj-$(CONFIG_RESET_HISI) += reset.o obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
drivers/clk/hisilicon/crg-hi3798.c renamed from drivers/clk/hisilicon/crg-hi3798cv200.c +91 -90
288 lines not on this page · raw message
Signature · 1 line
2.39.2
PATCH v7 2/9 clk: hisilicon: Extract common functions
In reply to David YangTo be reused with other Hi3798 series SoCs.
Signed-off-by David Yang <[email protected]>
--- drivers/clk/hisilicon/crg-hi3798.c | 243 ++++++++++++++++------------- 1 file changed, 137 insertions(+), 106 deletions(-)
drivers/clk/hisilicon/crg-hi3798.c +137 -106
@@ -59,6 +59,121 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = { { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, }, }; +struct hi3798_clks { +const struct hisi_gate_clock *gate_clks; +int gate_clks_nums; +const struct hisi_mux_clock *mux_clks; +int mux_clks_nums; +const struct hisi_phase_clock *phase_clks; +int phase_clks_nums; +}; + +static struct hisi_clock_data * +hi3798_clk_register (struct platform_device *pdev, +const struct hi3798_clks *clks) +{ +struct hisi_clock_data *clk_data; +int ret; + + clk_data =hisi_clk_alloc (pdev,HI3798_CRG_NR_CLKS ); +if (!clk_data) +return ERR_PTR (-ENOMEM ); + +/* hisi_phase_clock is resource managed */ + ret =hisi_clk_register_phase (&pdev->dev, clks->phase_clks, + clks->phase_clks_nums, clk_data); +if (ret) +return ERR_PTR (ret); + + ret =hisi_clk_register_fixed_rate (hi3798_fixed_rate_clks, +ARRAY_SIZE (hi3798_fixed_rate_clks), + clk_data); +if (ret) +return ERR_PTR (ret); + + ret =hisi_clk_register_mux (clks->mux_clks, clks->mux_clks_nums, clk_data); +if (ret) + goto unregister_fixed_rate; + + ret =hisi_clk_register_gate (clks->gate_clks, clks->gate_clks_nums, clk_data); +if (ret) + goto unregister_mux; + + ret =of_clk_add_provider (pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); +if (ret) + goto unregister_gate; + +return clk_data; + +unregister_gate: +hisi_clk_unregister_gate (clks->gate_clks, clks->gate_clks_nums, clk_data); +unregister_mux: +hisi_clk_unregister_mux (clks->mux_clks, clks->mux_clks_nums, clk_data); +unregister_fixed_rate: +hisi_clk_unregister_fixed_rate (hi3798_fixed_rate_clks, +ARRAY_SIZE (hi3798_fixed_rate_clks), + clk_data); +return ERR_PTR (ret); +} + +static void hi3798_clk_unregister (struct platform_device *pdev, +const struct hi3798_clks *clks) +{ +struct hisi_crg_dev *crg =platform_get_drvdata (pdev); + +of_clk_del_provider (pdev->dev.of_node); + +hisi_clk_unregister_gate (clks->gate_clks, clks->gate_clks_nums, crg->clk_data); +hisi_clk_unregister_mux (clks->mux_clks, clks->mux_clks_nums, crg->clk_data); +hisi_clk_unregister_fixed_rate (hi3798_fixed_rate_clks, +ARRAY_SIZE (hi3798_fixed_rate_clks), + crg->clk_data); +} + +/* hi3798 sysctrl CRG */ + +#define HI3798_SYSCTRL_NR_CLKS 16 + +static struct hisi_clock_data * +hi3798_sysctrl_clk_register (struct platform_device *pdev, +const struct hi3798_clks *clks) +{ +struct hisi_clock_data *clk_data; +int ret; + + clk_data =hisi_clk_alloc (pdev,HI3798_SYSCTRL_NR_CLKS ); +if (!clk_data) +return ERR_PTR (-ENOMEM ); + + ret =hisi_clk_register_gate (clks->gate_clks, clks->gate_clks_nums, clk_data); +if (ret) +return ERR_PTR (ret); + + ret =of_clk_add_provider (pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); +if (ret) + goto unregister_gate; + +return clk_data; + +unregister_gate: +hisi_clk_unregister_gate (clks->gate_clks, clks->gate_clks_nums, clk_data); +return ERR_PTR (ret); +} + +static void hi3798_sysctrl_clk_unregister (struct platform_device *pdev, +const struct hi3798_clks *clks) +{ +struct hisi_crg_dev *crg =platform_get_drvdata (pdev); + +of_clk_del_provider (pdev->dev.of_node); + +hisi_clk_unregister_gate (clks->gate_clks, clks->gate_clks_nums, crg->clk_data); +} + +/* hi3798CV200 */ +static const char *const hi3798cv200_mmc_mux_p[] = {"100m" ,"50m" ,"25m" ,"200m" ,"150m" };static u32 hi3798cv200_mmc_mux_table[] = {0 ,1 ,2 ,3 ,6 };
@@ -194,79 +309,24 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { CLK_SET_RATE_PARENT, 0xb0, 18, 0 }, }; -static struct hisi_clock_data *hi3798cv200_clk_register ( -struct platform_device *pdev) -{ -struct hisi_clock_data *clk_data; -int ret; - - clk_data =hisi_clk_alloc (pdev,HI3798_CRG_NR_CLKS ); -if (!clk_data) -return ERR_PTR (-ENOMEM ); - -/* hisi_phase_clock is resource managed */ - ret =hisi_clk_register_phase (&pdev->dev, - hi3798cv200_phase_clks, -ARRAY_SIZE (hi3798cv200_phase_clks), - clk_data); -if (ret) -return ERR_PTR (ret); - - ret =hisi_clk_register_fixed_rate (hi3798_fixed_rate_clks, -ARRAY_SIZE (hi3798_fixed_rate_clks), - clk_data); -if (ret) -return ERR_PTR (ret); - - ret =hisi_clk_register_mux (hi3798cv200_mux_clks, -ARRAY_SIZE (hi3798cv200_mux_clks), - clk_data); -if (ret) - goto unregister_fixed_rate; - - ret =hisi_clk_register_gate (hi3798cv200_gate_clks, -ARRAY_SIZE (hi3798cv200_gate_clks), - clk_data); -if (ret) - goto unregister_mux; - - ret =of_clk_add_provider (pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); -if (ret) - goto unregister_gate; - -return clk_data; +static const struct hi3798_clks hi3798cv200_crg_clks = { + .gate_clks = hi3798cv200_gate_clks, + .gate_clks_nums =ARRAY_SIZE (hi3798cv200_gate_clks), + .mux_clks = hi3798cv200_mux_clks, + .mux_clks_nums =ARRAY_SIZE (hi3798cv200_mux_clks), + .phase_clks = hi3798cv200_phase_clks, + .phase_clks_nums =ARRAY_SIZE (hi3798cv200_phase_clks), +}; -unregister_gate: -hisi_clk_unregister_gate (hi3798cv200_gate_clks, -ARRAY_SIZE (hi3798cv200_gate_clks), - clk_data); -unregister_mux: -hisi_clk_unregister_mux (hi3798cv200_mux_clks, -ARRAY_SIZE (hi3798cv200_mux_clks), - clk_data); -unregister_fixed_rate: -hisi_clk_unregister_fixed_rate (hi3798_fixed_rate_clks, -ARRAY_SIZE (hi3798_fixed_rate_clks), - clk_data); -return ERR_PTR (ret); +static struct hisi_clock_data * +hi3798cv200_clk_register (struct platform_device *pdev) +{ +return hi3798_clk_register (pdev, &hi3798cv200_crg_clks); }static void hi3798cv200_clk_unregister (struct platform_device *pdev) { -struct hisi_crg_dev *crg =platform_get_drvdata (pdev); - -of_clk_del_provider (pdev->dev.of_node); - -hisi_clk_unregister_gate (hi3798cv200_gate_clks, -ARRAY_SIZE (hi3798cv200_gate_clks), - crg->clk_data); -hisi_clk_unregister_mux (hi3798cv200_mux_clks, -ARRAY_SIZE (hi3798cv200_mux_clks), - crg->clk_data); -hisi_clk_unregister_fixed_rate (hi3798_fixed_rate_clks, -ARRAY_SIZE (hi3798_fixed_rate_clks), - crg->clk_data); +hi3798_clk_unregister (pdev, &hi3798cv200_crg_clks); }static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
@@ -274,10 +334,6 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { .unregister_clks = hi3798cv200_clk_unregister, }; -/* hi3798 sysctrl CRG */ - -#define HI3798_SYSCTRL_NR_CLKS 16 -static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { {HISTB_IR_CLK ,"clk_ir" ,"24m" ,CLK_SET_RATE_PARENT ,0x48 ,4 ,0 , },
@@ -287,45 +343,20 @@ static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { CLK_SET_RATE_PARENT, 0x48, 10, 0, }, }; -static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register ( -struct platform_device *pdev) -{ -struct hisi_clock_data *clk_data; -int ret; - - clk_data =hisi_clk_alloc (pdev,HI3798_SYSCTRL_NR_CLKS ); -if (!clk_data) -return ERR_PTR (-ENOMEM ); - - ret =hisi_clk_register_gate (hi3798cv200_sysctrl_gate_clks, -ARRAY_SIZE (hi3798cv200_sysctrl_gate_clks), - clk_data); -if (ret) -return ERR_PTR (ret); - - ret =of_clk_add_provider (pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); -if (ret) - goto unregister_gate; - -return clk_data; +static const struct hi3798_clks hi3798cv200_sysctrl_clks = { + .gate_clks = hi3798cv200_sysctrl_gate_clks, + .gate_clks_nums =ARRAY_SIZE (hi3798cv200_sysctrl_gate_clks), +}; -unregister_gate: -hisi_clk_unregister_gate (hi3798cv200_sysctrl_gate_clks, -ARRAY_SIZE (hi3798cv200_sysctrl_gate_clks), - clk_data); -return ERR_PTR (ret); +static struct hisi_clock_data * +hi3798cv200_sysctrl_clk_register (struct platform_device *pdev) +{ +return hi3798_sysctrl_clk_register (pdev, &hi3798cv200_sysctrl_clks); }static void hi3798cv200_sysctrl_clk_unregister (struct platform_device *pdev) { -struct hisi_crg_dev *crg =platform_get_drvdata (pdev); - -of_clk_del_provider (pdev->dev.of_node); - -hisi_clk_unregister_gate (hi3798cv200_sysctrl_gate_clks, -ARRAY_SIZE (hi3798cv200_sysctrl_gate_clks), - crg->clk_data); +hi3798_sysctrl_clk_unregister (pdev, &hi3798cv200_sysctrl_clks); }static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
Signature · 1 line
2.39.2
PATCH v7 3/9 clk: hisilicon: Remove hisi_clk_alloc
In reply to David YangDuring migration to devm APIs, (virtual) fixed-rate clocks were found hard on devm APIs, since they often depended by crucial peripherals, thus require early initialization before device probing, and cannot use devm APIs.
One solution to this problem is to add a "fixed-clock" node to device tree, independent to clock device, and make those peripherals depend on that. However, there is also some devices that do use fixed-rate clocks provided by drivers, for example clk-hi3660.c .
To simplify codes, we migrate clocks of other types to devm APIs, while keep fixed-rate clocks self-managed, alongside with struct hisi_clock_data, and remove devm-managed hisi_clock_data.
Patches for devm APIs migration are to follow.
Signed-off-by David Yang <[email protected]>
--- drivers/clk/hisilicon/clk-hi3519.c | 14 ++++----- drivers/clk/hisilicon/clk-hi3559a.c | 25 ++++++---------- drivers/clk/hisilicon/clk.c | 40 +++++-------------------- drivers/clk/hisilicon/clk.h | 3 +- drivers/clk/hisilicon/crg-hi3516cv300.c | 26 ++++++---------- drivers/clk/hisilicon/crg-hi3798.c | 25 ++++++---------- 6 files changed, 43 insertions(+), 90 deletions(-)
drivers/clk/hisilicon/clk-hi3519.c +6 -8
@@ -75,10 +75,12 @@ static const struct hisi_gate_clock hi3519_gate_clks[] = {static struct hisi_clock_data *hi3519_clk_register (struct platform_device *pdev) { +struct device *dev = &pdev->dev; +struct device_node *np = dev->of_node;struct hisi_clock_data *clk_data;int ret; - clk_data =hisi_clk_alloc (pdev,HI3519_NR_CLKS ); + clk_data =hisi_clk_init (np,HI3519_NR_CLKS );if (!clk_data)return ERR_PTR (-ENOMEM );
@@ -100,11 +102,6 @@ static struct hisi_clock_data *hi3519_clk_register(struct platform_device *pdev)if (ret) goto unregister_mux; - ret =of_clk_add_provider (pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); -if (ret) - goto unregister_gate; -return clk_data; unregister_fixed_rate:
@@ -127,8 +124,6 @@ static void hi3519_clk_unregister(struct platform_device *pdev) {struct hi3519_crg_data *crg =platform_get_drvdata (pdev); -of_clk_del_provider (pdev->dev.of_node); -hisi_clk_unregister_gate (hi3519_gate_clks,ARRAY_SIZE (hi3519_mux_clks), crg->clk_data);
@@ -164,10 +159,13 @@ static int hi3519_clk_probe(struct platform_device *pdev)static int hi3519_clk_remove (struct platform_device *pdev) { +struct device *dev = &pdev->dev; +struct device_node *np = dev->of_node;struct hi3519_crg_data *crg =platform_get_drvdata (pdev);hisi_reset_exit (crg->rstc);hi3519_clk_unregister (pdev); +hisi_clk_free (np, crg->clk_data);return 0 ; }
drivers/clk/hisilicon/clk-hi3559a.c +9 -16
@@ -505,10 +505,12 @@ static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,static struct hisi_clock_data *hi3559av100_clk_register (struct platform_device *pdev) { +struct device *dev = &pdev->dev; +struct device_node *np = dev->of_node;struct hisi_clock_data *clk_data;int ret; - clk_data =hisi_clk_alloc (pdev,HI3559AV100_CRG_NR_CLKS ); + clk_data =hisi_clk_init (np,HI3559AV100_CRG_NR_CLKS );if (!clk_data)return ERR_PTR (-ENOMEM );
@@ -530,11 +532,6 @@ static struct hisi_clock_data *hi3559av100_clk_register(if (ret) goto unregister_mux; - ret =of_clk_add_provider (pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); -if (ret) - goto unregister_gate; -return clk_data; unregister_gate:
@@ -553,8 +550,6 @@ static void hi3559av100_clk_unregister(struct platform_device *pdev) {struct hisi_crg_dev *crg =platform_get_drvdata (pdev); -of_clk_del_provider (pdev->dev.of_node); -hisi_clk_unregister_gate (hi3559av100_gate_clks,ARRAY_SIZE (hi3559av100_gate_clks), crg->clk_data); hisi_clk_unregister_mux(hi3559av100_mux_clks_crg,
@@ -699,12 +694,14 @@ static int hi3559av100_shub_default_clk_set(void)static struct hisi_clock_data *hi3559av100_shub_clk_register (struct platform_device *pdev) { +struct device *dev = &pdev->dev; +struct device_node *np = dev->of_node;struct hisi_clock_data *clk_data =NULL ;int ret;hi3559av100_shub_default_clk_set (); - clk_data =hisi_clk_alloc (pdev,HI3559AV100_SHUB_NR_CLKS ); + clk_data =hisi_clk_init (np,HI3559AV100_SHUB_NR_CLKS );if (!clk_data)return ERR_PTR (-ENOMEM );
@@ -728,11 +725,6 @@ static struct hisi_clock_data *hi3559av100_shub_clk_register(if (ret) goto unregister_factor; - ret =of_clk_add_provider (pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); -if (ret) - goto unregister_gate; -return clk_data; unregister_gate:
@@ -754,8 +746,6 @@ static void hi3559av100_shub_clk_unregister(struct platform_device *pdev) {struct hisi_crg_dev *crg =platform_get_drvdata (pdev); -of_clk_del_provider (pdev->dev.of_node); -hisi_clk_unregister_gate (hi3559av100_shub_gate_clks,ARRAY_SIZE (hi3559av100_shub_gate_clks), crg->clk_data); hisi_clk_unregister_divider(hi3559av100_shub_div_clks,
@@ -812,10 +802,13 @@ static int hi3559av100_crg_probe(struct platform_device *pdev)static int hi3559av100_crg_remove (struct platform_device *pdev) { +struct device *dev = &pdev->dev; +struct device_node *np = dev->of_node;struct hisi_crg_dev *crg =platform_get_drvdata (pdev);hisi_reset_exit (crg->rstc); crg->funcs->unregister_clks (pdev); +hisi_clk_free (np, crg->clk_data);return 0 ; }
drivers/clk/hisilicon/clk.c +8 -32
@@ -23,38 +23,6 @@static DEFINE_SPINLOCK (hisi_clk_lock); -struct hisi_clock_data *hisi_clk_alloc (struct platform_device *pdev, -int nr_clks) -{ -struct hisi_clock_data *clk_data; -struct resource *res; -struct clk **clk_table; - - clk_data =devm_kmalloc (&pdev->dev,sizeof (*clk_data),GFP_KERNEL ); -if (!clk_data) -return NULL ; - - res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); -if (!res) -return NULL ; - clk_data->base =devm_ioremap (&pdev->dev, - res->start,resource_size (res)); -if (!clk_data->base) -return NULL ; - - clk_table =devm_kmalloc_array (&pdev->dev, nr_clks, -sizeof (*clk_table), -GFP_KERNEL ); -if (!clk_table) -return NULL ; - - clk_data->clk_data.clks = clk_table; - clk_data->clk_data.clk_num = nr_clks; - -return clk_data; -} -EXPORT_SYMBOL_GPL (hisi_clk_alloc); -struct hisi_clock_data *hisi_clk_init (struct device_node *np,int nr_clks) {
@@ -88,6 +56,14 @@ struct hisi_clock_data *hisi_clk_init(struct device_node *np, }EXPORT_SYMBOL_GPL (hisi_clk_init); +void hisi_clk_free (struct device_node *np,struct hisi_clock_data *data) +{ +of_clk_del_provider (np); +kfree (data->clk_data.clks); +kfree (data); +} +EXPORT_SYMBOL_GPL (hisi_clk_free); +int hisi_clk_register_fixed_rate (const struct hisi_fixed_rate_clock *clks,int nums,struct hisi_clock_data *data) {
drivers/clk/hisilicon/clk.h +2 -1
@@ -111,8 +111,9 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u32 mask_bit, spinlock_t *lock); -struct hisi_clock_data *hisi_clk_alloc (struct platform_device *,int );struct hisi_clock_data *hisi_clk_init (struct device_node *,int ); +void hisi_clk_free (struct device_node *np,struct hisi_clock_data *data); +int hisi_clk_register_fixed_rate (const struct hisi_fixed_rate_clock *,int ,struct hisi_clock_data *); int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *,
drivers/clk/hisilicon/crg-hi3516cv300.c +9 -17
@@ -129,10 +129,12 @@ static const struct hisi_gate_clock hi3516cv300_gate_clks[] = {static struct hisi_clock_data *hi3516cv300_clk_register (struct platform_device *pdev) { +struct device *dev = &pdev->dev; +struct device_node *np = dev->of_node;struct hisi_clock_data *clk_data;int ret; - clk_data =hisi_clk_alloc (pdev,HI3516CV300_CRG_NR_CLKS ); + clk_data =hisi_clk_init (np,HI3516CV300_CRG_NR_CLKS );if (!clk_data)return ERR_PTR (-ENOMEM );
@@ -151,11 +153,6 @@ static struct hisi_clock_data *hi3516cv300_clk_register(if (ret) goto unregister_mux; - ret =of_clk_add_provider (pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); -if (ret) - goto unregister_gate; -return clk_data; unregister_gate:
@@ -174,8 +171,6 @@ static void hi3516cv300_clk_unregister(struct platform_device *pdev) {struct hisi_crg_dev *crg =platform_get_drvdata (pdev); -of_clk_del_provider (pdev->dev.of_node); -hisi_clk_unregister_gate (hi3516cv300_gate_clks,ARRAY_SIZE (hi3516cv300_gate_clks), crg->clk_data); hisi_clk_unregister_mux(hi3516cv300_mux_clks,
@@ -203,10 +198,12 @@ static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = {static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register (struct platform_device *pdev) { +struct device *dev = &pdev->dev; +struct device_node *np = dev->of_node;struct hisi_clock_data *clk_data;int ret; - clk_data =hisi_clk_alloc (pdev,HI3516CV300_SYSCTRL_NR_CLKS ); + clk_data =hisi_clk_init (np,HI3516CV300_SYSCTRL_NR_CLKS );if (!clk_data)return ERR_PTR (-ENOMEM );
@@ -215,12 +212,6 @@ static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register(if (ret)return ERR_PTR (ret); - - ret =of_clk_add_provider (pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); -if (ret) - goto unregister_mux; -return clk_data; unregister_mux:
@@ -233,8 +224,6 @@ static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev) {struct hisi_crg_dev *crg =platform_get_drvdata (pdev); -of_clk_del_provider (pdev->dev.of_node); -hisi_clk_unregister_mux (hi3516cv300_sysctrl_mux_clks,ARRAY_SIZE (hi3516cv300_sysctrl_mux_clks), crg->clk_data);
@@ -286,10 +275,13 @@ static int hi3516cv300_crg_probe(struct platform_device *pdev)static int hi3516cv300_crg_remove (struct platform_device *pdev) { +struct device *dev = &pdev->dev; +struct device_node *np = dev->of_node;struct hisi_crg_dev *crg =platform_get_drvdata (pdev);hisi_reset_exit (crg->rstc); crg->funcs->unregister_clks (pdev); +hisi_clk_free (np, crg->clk_data);return 0 ; }
drivers/clk/hisilicon/crg-hi3798.c +9 -16
@@ -72,10 +72,12 @@ static struct hisi_clock_data * hi3798_clk_register(struct platform_device *pdev, const struct hi3798_clks *clks) { + struct device *dev = &pdev->dev; +struct device_node *np = dev->of_node;struct hisi_clock_data *clk_data;int ret; - clk_data =hisi_clk_alloc (pdev,HI3798_CRG_NR_CLKS ); + clk_data =hisi_clk_init (np,HI3798_CRG_NR_CLKS );if (!clk_data)return ERR_PTR (-ENOMEM );
@@ -99,11 +101,6 @@ hi3798_clk_register(struct platform_device *pdev,if (ret) goto unregister_mux; - ret =of_clk_add_provider (pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); -if (ret) - goto unregister_gate; -return clk_data; unregister_gate:
@@ -122,8 +119,6 @@ static void hi3798_clk_unregister(struct platform_device *pdev, {struct hisi_crg_dev *crg =platform_get_drvdata (pdev); -of_clk_del_provider (pdev->dev.of_node); -hisi_clk_unregister_gate (clks->gate_clks, clks->gate_clks_nums, crg->clk_data);hisi_clk_unregister_mux (clks->mux_clks, clks->mux_clks_nums, crg->clk_data); hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks,
@@ -139,10 +134,12 @@ static struct hisi_clock_data * hi3798_sysctrl_clk_register(struct platform_device *pdev, const struct hi3798_clks *clks) { + struct device *dev = &pdev->dev; +struct device_node *np = dev->of_node;struct hisi_clock_data *clk_data;int ret; - clk_data =hisi_clk_alloc (pdev,HI3798_SYSCTRL_NR_CLKS ); + clk_data =hisi_clk_init (np,HI3798_SYSCTRL_NR_CLKS );if (!clk_data)return ERR_PTR (-ENOMEM );
@@ -150,11 +147,6 @@ hi3798_sysctrl_clk_register(struct platform_device *pdev,if (ret)return ERR_PTR (ret); - ret =of_clk_add_provider (pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); -if (ret) - goto unregister_gate; -return clk_data; unregister_gate:
@@ -167,8 +159,6 @@ static void hi3798_sysctrl_clk_unregister(struct platform_device *pdev, {struct hisi_crg_dev *crg =platform_get_drvdata (pdev); -of_clk_del_provider (pdev->dev.of_node); -hisi_clk_unregister_gate (clks->gate_clks, clks->gate_clks_nums, crg->clk_data); }
@@ -401,10 +391,13 @@ static int hi3798_crg_probe(struct platform_device *pdev)static int hi3798_crg_remove (struct platform_device *pdev) { +struct device *dev = &pdev->dev; +struct device_node *np = dev->of_node;struct hisi_crg_dev *crg =platform_get_drvdata (pdev);hisi_reset_exit (crg->rstc); crg->funcs->unregister_clks (pdev); +hisi_clk_free (np, crg->clk_data);return 0 ; }
Signature · 1 line
2.39.2
PATCH v7 4/9 clk: hisilicon: Add helper functions for platform driver
In reply to David YangHelper functions extract common operations on platform drivers.
This patch is part of devm APIs migration.
Signed-off-by David Yang <[email protected]>
--- drivers/clk/hisilicon/clk-hi6220.c | 6 +- drivers/clk/hisilicon/clk.c | 132 ++++++++++++++++++++++++++++- drivers/clk/hisilicon/clk.h | 75 +++++++++++++--- drivers/clk/hisilicon/crg.h | 5 ++ drivers/clk/hisilicon/reset.c | 65 +++++++++++++- 5 files changed, 264 insertions(+), 19 deletions(-)
drivers/clk/hisilicon/clk-hi6220.c +3 -3
@@ -191,7 +191,7 @@ static void __init hi6220_clk_sys_init(struct device_node *np)hisi_clk_register_mux (hi6220_mux_clks_sys,ARRAY_SIZE (hi6220_mux_clks_sys), clk_data); -hi6220_clk_register_divider (hi6220_div_clks_sys, +hi6220_clk_register_divider (NULL , hi6220_div_clks_sys,ARRAY_SIZE (hi6220_div_clks_sys), clk_data); }CLK_OF_DECLARE_DRIVER (hi6220_clk_sys,"hisilicon,hi6220-sysctrl" , hi6220_clk_sys_init);
@@ -248,7 +248,7 @@ static void __init hi6220_clk_media_init(struct device_node *np)hisi_clk_register_mux (hi6220_mux_clks_media,ARRAY_SIZE (hi6220_mux_clks_media), clk_data); -hi6220_clk_register_divider (hi6220_div_clks_media, +hi6220_clk_register_divider (NULL , hi6220_div_clks_media,ARRAY_SIZE (hi6220_div_clks_media), clk_data); }CLK_OF_DECLARE_DRIVER (hi6220_clk_media,"hisilicon,hi6220-mediactrl" , hi6220_clk_media_init);
@@ -279,7 +279,7 @@ static void __init hi6220_clk_power_init(struct device_node *np)hisi_clk_register_gate (hi6220_gate_clks_power,ARRAY_SIZE (hi6220_gate_clks_power), clk_data); -hi6220_clk_register_divider (hi6220_div_clks_power, +hi6220_clk_register_divider (NULL , hi6220_div_clks_power,ARRAY_SIZE (hi6220_div_clks_power), clk_data); }CLK_OF_DECLARE (hi6220_clk_power,"hisilicon,hi6220-pmctrl" , hi6220_clk_power_init);
drivers/clk/hisilicon/clk.c +128 -4
163 lines not on this page · raw message
drivers/clk/hisilicon/clk.h +65 -10
109 lines not on this page · raw message
drivers/clk/hisilicon/crg.h +5 -0
@@ -22,4 +22,9 @@ struct hisi_crg_dev { const struct hisi_crg_funcs *funcs; }; +/* helper functions for platform driver */ + +int hisi_crg_probe (struct platform_device *pdev); +int hisi_crg_remove (struct platform_device *pdev); +#endif /* __HISI_CRG_H */
drivers/clk/hisilicon/reset.c +63 -2
78 lines not on this page · raw message
Signature · 1 line
2.39.2
PATCH v7 5/9 clk: hisilicon: Use helper functions
In reply to David YangRemove redundant codes.
Signed-off-by David Yang <[email protected]>
--- drivers/clk/hisilicon/clk-hi3519.c | 132 ++---------- drivers/clk/hisilicon/clk-hi3559a.c | 221 ++++---------------- drivers/clk/hisilicon/clk-hi3660.c | 204 ++++++------------ drivers/clk/hisilicon/clk-hi3670.c | 267 ++++++++---------------- drivers/clk/hisilicon/crg-hi3516cv300.c | 169 ++------------- drivers/clk/hisilicon/crg-hi3798.c | 219 ++----------------- drivers/clk/hisilicon/crg.h | 6 - drivers/clk/hisilicon/reset.c | 1 - 8 files changed, 250 insertions(+), 969 deletions(-)
drivers/clk/hisilicon/clk-hi3519.c +19 -113
@@ -6,11 +6,13 @@*/ #include <dt-bindings/clock/hi3519-clock.h> -#include <linux/clk-provider.h> + +#include <linux/kernel.h> #include <linux/module.h> -#include <linux/platform_device.h> +#include <linux/of_device.h> +#include "clk.h" -#include "reset.h" +#include "crg.h" #define HI3519_INNER_CLK_OFFSET 64#define HI3519_FIXED_24M 65
@@ -73,129 +75,33 @@ static const struct hisi_gate_clock hi3519_gate_clks[] = { CLK_SET_RATE_PARENT, 0xe4, 18, 0, }, }; -static struct hisi_clock_data *hi3519_clk_register (struct platform_device *pdev) -{ -struct device *dev = &pdev->dev; -struct device_node *np = dev->of_node; -struct hisi_clock_data *clk_data; -int ret; - - clk_data =hisi_clk_init (np,HI3519_NR_CLKS ); -if (!clk_data) -return ERR_PTR (-ENOMEM ); - - ret =hisi_clk_register_fixed_rate (hi3519_fixed_rate_clks, -ARRAY_SIZE (hi3519_fixed_rate_clks), - clk_data); -if (ret) -return ERR_PTR (ret); - - ret =hisi_clk_register_mux (hi3519_mux_clks, -ARRAY_SIZE (hi3519_mux_clks), - clk_data); -if (ret) - goto unregister_fixed_rate; - - ret =hisi_clk_register_gate (hi3519_gate_clks, -ARRAY_SIZE (hi3519_gate_clks), - clk_data); -if (ret) - goto unregister_mux; - -return clk_data; - -unregister_fixed_rate: -hisi_clk_unregister_fixed_rate (hi3519_fixed_rate_clks, -ARRAY_SIZE (hi3519_fixed_rate_clks), - clk_data); - -unregister_mux: -hisi_clk_unregister_mux (hi3519_mux_clks, -ARRAY_SIZE (hi3519_mux_clks), - clk_data); -unregister_gate: -hisi_clk_unregister_gate (hi3519_gate_clks, -ARRAY_SIZE (hi3519_gate_clks), - clk_data); -return ERR_PTR (ret); -} - -static void hi3519_clk_unregister (struct platform_device *pdev) -{ -struct hi3519_crg_data *crg =platform_get_drvdata (pdev); - -hisi_clk_unregister_gate (hi3519_gate_clks, -ARRAY_SIZE (hi3519_mux_clks), - crg->clk_data); -hisi_clk_unregister_mux (hi3519_mux_clks, -ARRAY_SIZE (hi3519_mux_clks), - crg->clk_data); -hisi_clk_unregister_fixed_rate (hi3519_fixed_rate_clks, -ARRAY_SIZE (hi3519_fixed_rate_clks), - crg->clk_data); -} - -static int hi3519_clk_probe (struct platform_device *pdev) -{ -struct hi3519_crg_data *crg; - - crg =devm_kmalloc (&pdev->dev,sizeof (*crg),GFP_KERNEL ); -if (!crg) -return -ENOMEM ; - - crg->rstc =hisi_reset_init (pdev); -if (!crg->rstc) -return -ENOMEM ; - - crg->clk_data =hi3519_clk_register (pdev); -if (IS_ERR (crg->clk_data)) { -hisi_reset_exit (crg->rstc); -return PTR_ERR (crg->clk_data); - } - -platform_set_drvdata (pdev, crg); -return 0 ; -} - -static int hi3519_clk_remove (struct platform_device *pdev) -{ -struct device *dev = &pdev->dev; -struct device_node *np = dev->of_node; -struct hi3519_crg_data *crg =platform_get_drvdata (pdev); - -hisi_reset_exit (crg->rstc); -hi3519_clk_unregister (pdev); -hisi_clk_free (np, crg->clk_data); -return 0 ; -} - +static const struct hisi_clocks hi3519_crg_clks = { + .nr =HI3519_NR_CLKS , + .fixed_rate_clks = hi3519_fixed_rate_clks, + .fixed_rate_clks_num =ARRAY_SIZE (hi3519_fixed_rate_clks), + .mux_clks = hi3519_mux_clks, + .mux_clks_num =ARRAY_SIZE (hi3519_mux_clks), + .gate_clks = hi3519_gate_clks, + .gate_clks_num =ARRAY_SIZE (hi3519_gate_clks), +};static const struct of_device_id hi3519_clk_match_table[] = { - { .compatible ="hisilicon,hi3519-crg" }, + { .compatible ="hisilicon,hi3519-crg" , + .data = &hi3519_crg_clks }, { } };MODULE_DEVICE_TABLE (of, hi3519_clk_match_table);static struct platform_driver hi3519_clk_driver = { - .probe = hi3519_clk_probe, - .remove = hi3519_clk_remove, + .probe = hisi_crg_probe, + .remove = hisi_crg_remove, .driver = { .name ="hi3519-clk" , .of_match_table = hi3519_clk_match_table, }, }; -static int __init hi3519_clk_init (void ) -{ -return platform_driver_register (&hi3519_clk_driver); -} -core_initcall (hi3519_clk_init); - -static void __exit hi3519_clk_exit(void) -{ -platform_driver_unregister (&hi3519_clk_driver); -} -module_exit (hi3519_clk_exit); +module_platform_driver (hi3519_clk_driver);MODULE_LICENSE ("GPL v2" );MODULE_DESCRIPTION ("HiSilicon Hi3519 Clock Driver" );
drivers/clk/hisilicon/clk-hi3559a.c +35 -186
285 lines not on this page · raw message
drivers/clk/hisilicon/clk-hi3660.c +63 -141
241 lines not on this page · raw message
drivers/clk/hisilicon/clk-hi3670.c +92 -175
296 lines not on this page · raw message
drivers/clk/hisilicon/crg-hi3516cv300.c +20 -149
211 lines not on this page · raw message
drivers/clk/hisilicon/crg-hi3798.c +21 -198
272 lines not on this page · raw message
drivers/clk/hisilicon/crg.h +0 -6
@@ -11,15 +11,9 @@struct hisi_clock_data ;struct hisi_reset_controller ; -struct hisi_crg_funcs { -struct hisi_clock_data * (*register_clks)(struct platform_device *pdev); -void (*unregister_clks)(struct platform_device *pdev); -}; -struct hisi_crg_dev {struct hisi_clock_data *clk_data;struct hisi_reset_controller *rstc; -const struct hisi_crg_funcs *funcs; };/* helper functions for platform driver */
drivers/clk/hisilicon/reset.c +0 -1
@@ -172,7 +172,6 @@ int hisi_crg_remove(struct platform_device *pdev)struct hisi_crg_dev *crg =platform_get_drvdata (pdev);hisi_reset_exit (crg->rstc); - crg->funcs->unregister_clks (pdev);hisi_clk_free (np, crg->clk_data);return 0 ; }
Signature · 1 line
2.39.2
PATCH v7 6/9 clk: hisilicon: Convert to platform_driver
In reply to David YangAnd use common helper functions.
This patch is part of devm APIs migration.
Signed-off-by David Yang <[email protected]>
--- drivers/clk/hisilicon/clk-hi3620.c | 194 ++++++++++++------------ drivers/clk/hisilicon/clk-hi6220.c | 224 +++++++++++++--------------- drivers/clk/hisilicon/clk-hip04.c | 38 +++-- drivers/clk/hisilicon/clk-hix5hd2.c | 80 ++++++---- 4 files changed, 271 insertions(+), 265 deletions(-)
drivers/clk/hisilicon/clk-hi3620.c +98 -96
@@ -12,6 +12,7 @@#include <linux/kernel.h> #include <linux/clk-provider.h> #include <linux/io.h> +#include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_device.h>
@@ -22,48 +23,48 @@#include "clk.h" /* clock parent list */ -static const char *const timer0_mux_p[]__initconst = {"osc32k" ,"timerclk01" , }; -static const char *const timer1_mux_p[]__initconst = {"osc32k" ,"timerclk01" , }; -static const char *const timer2_mux_p[]__initconst = {"osc32k" ,"timerclk23" , }; -static const char *const timer3_mux_p[]__initconst = {"osc32k" ,"timerclk23" , }; -static const char *const timer4_mux_p[]__initconst = {"osc32k" ,"timerclk45" , }; -static const char *const timer5_mux_p[]__initconst = {"osc32k" ,"timerclk45" , }; -static const char *const timer6_mux_p[]__initconst = {"osc32k" ,"timerclk67" , }; -static const char *const timer7_mux_p[]__initconst = {"osc32k" ,"timerclk67" , }; -static const char *const timer8_mux_p[]__initconst = {"osc32k" ,"timerclk89" , }; -static const char *const timer9_mux_p[]__initconst = {"osc32k" ,"timerclk89" , }; -static const char *const uart0_mux_p[]__initconst = {"osc26m" ,"pclk" , }; -static const char *const uart1_mux_p[]__initconst = {"osc26m" ,"pclk" , }; -static const char *const uart2_mux_p[]__initconst = {"osc26m" ,"pclk" , }; -static const char *const uart3_mux_p[]__initconst = {"osc26m" ,"pclk" , }; -static const char *const uart4_mux_p[]__initconst = {"osc26m" ,"pclk" , }; -static const char *const spi0_mux_p[]__initconst = {"osc26m" ,"rclk_cfgaxi" , }; -static const char *const spi1_mux_p[]__initconst = {"osc26m" ,"rclk_cfgaxi" , }; -static const char *const spi2_mux_p[]__initconst = {"osc26m" ,"rclk_cfgaxi" , }; +static const char *const timer0_mux_p[] = {"osc32k" ,"timerclk01" , }; +static const char *const timer1_mux_p[] = {"osc32k" ,"timerclk01" , }; +static const char *const timer2_mux_p[] = {"osc32k" ,"timerclk23" , }; +static const char *const timer3_mux_p[] = {"osc32k" ,"timerclk23" , }; +static const char *const timer4_mux_p[] = {"osc32k" ,"timerclk45" , }; +static const char *const timer5_mux_p[] = {"osc32k" ,"timerclk45" , }; +static const char *const timer6_mux_p[] = {"osc32k" ,"timerclk67" , }; +static const char *const timer7_mux_p[] = {"osc32k" ,"timerclk67" , }; +static const char *const timer8_mux_p[] = {"osc32k" ,"timerclk89" , }; +static const char *const timer9_mux_p[] = {"osc32k" ,"timerclk89" , }; +static const char *const uart0_mux_p[] = {"osc26m" ,"pclk" , }; +static const char *const uart1_mux_p[] = {"osc26m" ,"pclk" , }; +static const char *const uart2_mux_p[] = {"osc26m" ,"pclk" , }; +static const char *const uart3_mux_p[] = {"osc26m" ,"pclk" , }; +static const char *const uart4_mux_p[] = {"osc26m" ,"pclk" , }; +static const char *const spi0_mux_p[] = {"osc26m" ,"rclk_cfgaxi" , }; +static const char *const spi1_mux_p[] = {"osc26m" ,"rclk_cfgaxi" , }; +static const char *const spi2_mux_p[] = {"osc26m" ,"rclk_cfgaxi" , };/* share axi parent */ -static const char *const saxi_mux_p[]__initconst = {"armpll3" ,"armpll2" , }; -static const char *const pwm0_mux_p[]__initconst = {"osc32k" ,"osc26m" , }; -static const char *const pwm1_mux_p[]__initconst = {"osc32k" ,"osc26m" , }; -static const char *const sd_mux_p[]__initconst = {"armpll2" ,"armpll3" , }; -static const char *const mmc1_mux_p[]__initconst = {"armpll2" ,"armpll3" , }; -static const char *const mmc1_mux2_p[]__initconst = {"osc26m" ,"mmc1_div" , }; -static const char *const g2d_mux_p[]__initconst = {"armpll2" ,"armpll3" , }; -static const char *const venc_mux_p[]__initconst = {"armpll2" ,"armpll3" , }; -static const char *const vdec_mux_p[]__initconst = {"armpll2" ,"armpll3" , }; -static const char *const vpp_mux_p[]__initconst = {"armpll2" ,"armpll3" , }; -static const char *const edc0_mux_p[]__initconst = {"armpll2" ,"armpll3" , }; -static const char *const ldi0_mux_p[]__initconst = {"armpll2" ,"armpll4" , +static const char *const saxi_mux_p[] = {"armpll3" ,"armpll2" , }; +static const char *const pwm0_mux_p[] = {"osc32k" ,"osc26m" , }; +static const char *const pwm1_mux_p[] = {"osc32k" ,"osc26m" , }; +static const char *const sd_mux_p[] = {"armpll2" ,"armpll3" , }; +static const char *const mmc1_mux_p[] = {"armpll2" ,"armpll3" , }; +static const char *const mmc1_mux2_p[] = {"osc26m" ,"mmc1_div" , }; +static const char *const g2d_mux_p[] = {"armpll2" ,"armpll3" , }; +static const char *const venc_mux_p[] = {"armpll2" ,"armpll3" , }; +static const char *const vdec_mux_p[] = {"armpll2" ,"armpll3" , }; +static const char *const vpp_mux_p[] = {"armpll2" ,"armpll3" , }; +static const char *const edc0_mux_p[] = {"armpll2" ,"armpll3" , }; +static const char *const ldi0_mux_p[] = {"armpll2" ,"armpll4" ,"armpll3" ,"armpll5" , }; -static const char *const edc1_mux_p[]__initconst = {"armpll2" ,"armpll3" , }; -static const char *const ldi1_mux_p[]__initconst = {"armpll2" ,"armpll4" , +static const char *const edc1_mux_p[] = {"armpll2" ,"armpll3" , }; +static const char *const ldi1_mux_p[] = {"armpll2" ,"armpll4" ,"armpll3" ,"armpll5" , }; -static const char *const rclk_hsic_p[]__initconst = {"armpll3" ,"armpll2" , }; -static const char *const mmc2_mux_p[]__initconst = {"armpll2" ,"armpll3" , }; -static const char *const mmc3_mux_p[]__initconst = {"armpll2" ,"armpll3" , }; +static const char *const rclk_hsic_p[] = {"armpll3" ,"armpll2" , }; +static const char *const mmc2_mux_p[] = {"armpll2" ,"armpll3" , }; +static const char *const mmc3_mux_p[] = {"armpll2" ,"armpll3" , };/* fixed rate clocks */ -static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[]__initdata = { +static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] = { {HI3620_OSC32K ,"osc32k" ,NULL ,0 ,32768 , }, {HI3620_OSC26M ,"osc26m" ,NULL ,0 ,26000000 , }, {HI3620_PCLK ,"pclk" ,NULL ,0 ,26000000 , },
@@ -76,13 +77,13 @@ static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = { };/* fixed factor clocks */ -static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[]__initdata = { +static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] = { {HI3620_RCLK_TCXO ,"rclk_tcxo" ,"osc26m" ,1 ,4 ,0 , }, {HI3620_RCLK_CFGAXI ,"rclk_cfgaxi" ,"armpll2" ,1 ,30 ,0 , }, {HI3620_RCLK_PICO ,"rclk_pico" ,"hsic_div" ,1 ,40 ,0 , }, }; -static struct hisi_mux_clock hi3620_mux_clks[]__initdata = { +static struct hisi_mux_clock hi3620_mux_clks[] = { {HI3620_TIMER0_MUX ,"timer0_mux" , timer0_mux_p,ARRAY_SIZE (timer0_mux_p),CLK_SET_RATE_PARENT ,0 ,15 ,2 ,0 , }, {HI3620_TIMER1_MUX ,"timer1_mux" , timer1_mux_p,ARRAY_SIZE (timer1_mux_p),CLK_SET_RATE_PARENT ,0 ,17 ,2 ,0 , }, {HI3620_TIMER2_MUX ,"timer2_mux" , timer2_mux_p,ARRAY_SIZE (timer2_mux_p),CLK_SET_RATE_PARENT ,0 ,19 ,2 ,0 , },
@@ -120,7 +121,7 @@ static struct hisi_mux_clock hi3620_mux_clks[] __initdata = { { HI3620_MMC3_MUX, "mmc3_mux", mmc3_mux_p, ARRAY_SIZE(mmc3_mux_p), CLK_SET_RATE_PARENT, 0x140, 9, 1, CLK_MUX_HIWORD_MASK, }, }; -static struct hisi_divider_clock hi3620_div_clks[]__initdata = { +static struct hisi_divider_clock hi3620_div_clks[] = { {HI3620_SHAREAXI_DIV ,"saxi_div" ,"saxi_mux" ,0 ,0x100 ,0 ,5 ,CLK_DIVIDER_HIWORD_MASK ,NULL , }, {HI3620_CFGAXI_DIV ,"cfgaxi_div" ,"saxi_div" ,0 ,0x100 ,5 ,2 ,CLK_DIVIDER_HIWORD_MASK ,NULL , }, { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
@@ -130,7 +131,7 @@ static struct hisi_divider_clock hi3620_div_clks[] __initdata = { { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, }; -static struct hisi_gate_clock hi3620_separated_gate_clks[]__initdata = { +static struct hisi_gate_clock hi3620_separated_gate_clks[] = { {HI3620_TIMERCLK01 ,"timerclk01" ,"timer_rclk01" ,CLK_SET_RATE_PARENT ,0x20 ,0 ,0 , }, {HI3620_TIMER_RCLK01 ,"timer_rclk01" ,"rclk_tcxo" ,CLK_SET_RATE_PARENT ,0x20 ,1 ,0 , }, { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PARENT, 0x20, 2, 0, },
@@ -192,29 +193,19 @@ static struct hisi_gate_clock hi3620_separated_gate_clks[] __initdata = { { HI3620_MCU_CLK, "mcu_clk", "acp_clk", CLK_SET_RATE_PARENT, 0x50, 24, 0, }, }; -static void __init hi3620_clk_init (struct device_node *np) -{ -struct hisi_clock_data *clk_data; - - clk_data =hisi_clk_init (np,HI3620_NR_CLKS ); -if (!clk_data) -return ; - -hisi_clk_register_fixed_rate (hi3620_fixed_rate_clks, -ARRAY_SIZE (hi3620_fixed_rate_clks), - clk_data); -hisi_clk_register_fixed_factor (hi3620_fixed_factor_clks, -ARRAY_SIZE (hi3620_fixed_factor_clks), - clk_data); -hisi_clk_register_mux (hi3620_mux_clks,ARRAY_SIZE (hi3620_mux_clks), - clk_data); -hisi_clk_register_divider (hi3620_div_clks,ARRAY_SIZE (hi3620_div_clks), - clk_data); -hisi_clk_register_gate_sep (hi3620_separated_gate_clks, -ARRAY_SIZE (hi3620_separated_gate_clks), - clk_data); -} -CLK_OF_DECLARE (hi3620_clk,"hisilicon,hi3620-clock" , hi3620_clk_init); +static const struct hisi_clocks hi3620_clks = { + .nr =HI3620_NR_CLKS , + .fixed_rate_clks = hi3620_fixed_rate_clks, + .fixed_rate_clks_num =ARRAY_SIZE (hi3620_fixed_rate_clks), + .fixed_factor_clks = hi3620_fixed_factor_clks, + .fixed_factor_clks_num =ARRAY_SIZE (hi3620_fixed_factor_clks), + .mux_clks = hi3620_mux_clks, + .mux_clks_num =ARRAY_SIZE (hi3620_mux_clks), + .divider_clks = hi3620_div_clks, + .divider_clks_num =ARRAY_SIZE (hi3620_div_clks), + .gate_sep_clks = hi3620_separated_gate_clks, + .gate_sep_clks_num =ARRAY_SIZE (hi3620_separated_gate_clks), +}; struct hisi_mmc_clock { unsigned int id;
@@ -252,7 +243,7 @@ struct clk_mmc {#define to_mmc (_hw) container_of(_hw, struct clk_mmc, hw) -static struct hisi_mmc_clock hi3620_mmc_clks[]__initdata = { +static struct hisi_mmc_clock hi3620_mmc_clks[] = { {HI3620_SD_CIUCLK ,"sd_bclk1" ,"sd_clk" ,CLK_SET_RATE_PARENT ,0x1f8 ,0 ,0x1f8 ,1 ,3 ,0x1f8 ,4 ,4 ,0x1f8 ,8 ,4 }, {HI3620_MMC_CIUCLK1 ,"mmc_bclk1" ,"mmc_clk1" ,CLK_SET_RATE_PARENT ,0x1f8 ,12 ,0x1f8 ,13 ,3 ,0x1f8 ,16 ,4 ,0x1f8 ,20 ,4 }, {HI3620_MMC_CIUCLK2 ,"mmc_bclk2" ,"mmc_clk2" ,CLK_SET_RATE_PARENT ,0x1f8 ,24 ,0x1f8 ,25 ,3 ,0x1f8 ,28 ,4 ,0x1fc ,0 ,4 },
@@ -408,8 +399,9 @@ static const struct clk_ops clk_mmc_ops = { .recalc_rate = mmc_clk_recalc_rate, }; -static struct clk *hisi_register_clk_mmc (struct hisi_mmc_clock *mmc_clk, -void __iomem *base,struct device_node *np) +static struct clk * +clk_register_hisi_mmc (struct device *dev,const struct hisi_mmc_clock *mmc_clk, +void __iomem *base) {struct clk_mmc *mclk;struct clk *clk;
@@ -445,39 +437,49 @@ static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk,return clk; } -static void __init hi3620_mmc_clk_init (struct device_node *node) +static int hisi_register_clk_mmc (struct device *dev,const void *clocks, +int nums,struct hisi_clock_data *data) { -void __iomem *base; -int i, num =ARRAY_SIZE (hi3620_mmc_clks); -struct clk_onecell_data *clk_data; - -if (!node) { -pr_err ("failed to find pctrl node in DTS\n" ); -return ; - } - - base =of_iomap (node,0 ); -if (!base) { -pr_err ("failed to map pctrl\n" ); -return ; +const struct hisi_mmc_clock *clks = clocks; +struct clk *clk; +int i; + +for (i =0 ; i < nums; i++) { + clk =clk_register_hisi_mmc (dev, &clks[i], data->base); +if (IS_ERR (clk)) { +pr_err ("%s: failed to register clock %s\n" , + __func__, clks[i].name); +return PTR_ERR (clk); + } + data->clk_data.clks[clks[i].id] = clk; } - clk_data =kzalloc (sizeof (*clk_data),GFP_KERNEL ); -if (WARN_ON (!clk_data)) -return ; - - clk_data->clks =kcalloc (num,sizeof (*clk_data->clks),GFP_KERNEL ); -if (!clk_data->clks) -return ; +return 0 ; +} -for (i =0 ; i < num; i++) { -struct hisi_mmc_clock *mmc_clk = &hi3620_mmc_clks[i]; - clk_data->clks[mmc_clk->id] = -hisi_register_clk_mmc (mmc_clk, base, node); - } +static const struct hisi_clocks hi3620_clks_mmc = { + .nr =ARRAY_SIZE (hi3620_mmc_clks), + .customized_clks = hi3620_mmc_clks, + .customized_clks_num =ARRAY_SIZE (hi3620_mmc_clks), + .clk_register_customized = hisi_register_clk_mmc, +}; - clk_data->clk_num = num; -of_clk_add_provider (node, of_clk_src_onecell_get, clk_data); -} +static const struct of_device_id hi3620_clk_match_table[] = { + { .compatible ="hisilicon,hi3620-clock" , + .data = &hi3620_clks }, + { .compatible ="hisilicon,hi3620-mmc-clock" , + .data = &hi3620_clks_mmc }, + { } +}; +MODULE_DEVICE_TABLE (of, hi3620_clk_match_table); + +static struct platform_driver hi3620_clk_driver = { + .probe = hisi_clk_probe, + .remove = hisi_clk_remove, + .driver = { + .name ="hi3620-clock" , + .of_match_table = hi3620_clk_match_table, + }, +}; -CLK_OF_DECLARE (hi3620_mmc_clk,"hisilicon,hi3620-mmc-clock" , hi3620_mmc_clk_init); +module_platform_driver (hi3620_clk_driver);
drivers/clk/hisilicon/clk-hi6220.c +103 -121
315 lines not on this page · raw message
drivers/clk/hisilicon/clk-hip04.c +22 -16
@@ -9,12 +9,8 @@*/ #include <linux/kernel.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> +#include <linux/module.h> #include <linux/of_device.h> -#include <linux/slab.h> #include <dt-bindings/clock/hip04-clock.h>
@@ -27,16 +23,26 @@ static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = { { HIP04_CLK_168M, "clk168m", NULL, 0, 168750000, }, }; -static void __init hip04_clk_init (struct device_node *np) -{ -struct hisi_clock_data *clk_data; +static const struct hisi_clocks hip04_clks = { + .nr =ARRAY_SIZE (hip04_fixed_rate_clks), + .fixed_rate_clks = hip04_fixed_rate_clks, + .fixed_factor_clks_num =ARRAY_SIZE (hip04_fixed_rate_clks), +}; + +static const struct of_device_id hip04_clk_match_table[] = { + { .compatible ="hisilicon,hip04-clock" , + .data = &hip04_clks }, + { } +}; +MODULE_DEVICE_TABLE (of, hip04_clk_match_table); - clk_data =hisi_clk_init (np,HIP04_NR_CLKS ); -if (!clk_data) -return ; +static struct platform_driver hip04_clk_driver = { + .probe = hisi_clk_probe, + .remove = hisi_clk_remove, + .driver = { + .name ="hip04-clock" , + .of_match_table = hip04_clk_match_table, + }, +}; -hisi_clk_register_fixed_rate (hip04_fixed_rate_clks, -ARRAY_SIZE (hip04_fixed_rate_clks), - clk_data); -} -CLK_OF_DECLARE (hip04_clk,"hisilicon,hip04-clock" , hip04_clk_init); +module_platform_driver (hip04_clk_driver);
drivers/clk/hisilicon/clk-hix5hd2.c +48 -32
142 lines not on this page · raw message
Signature · 1 line
2.39.2
kernel test robot
build botRe: [PATCH v7 6/9] clk: hisilicon: Convert to platform_driver
Thank you for the patch! Perhaps something to improve:
Hi David,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on 6015b1aca1a233379625385feb01dd014aca60b5]
url: https://github.com/intel-lab-lkp/linux/commits/David-Yang/clk-hisilicon-Rename-Hi3798CV200-to-Hi3798/20230323-004453 base: 6015b1aca1a233379625385feb01dd014aca60b5 patch link: https://lore.kernel.org/r/20230322164201.2454771-7-mmyangfl%40gmail.com patch subject: [PATCH v7 6/9] clk: hisilicon: Convert to platform_driver config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20230323/[email protected]/config) compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/f551034776d2c5eb0495634bd2f8bde5c4743f92
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review David-Yang/clk-hisilicon-Rename-Hi3798CV200-to-Hi3798/20230323-004453 git checkout f551034776d2c5eb0495634bd2f8bde5c4743f92
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm olddefconfig COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/clk/hisilicon/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
| Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
drivers/clk/hisilicon/clk-hix5hd2.c: In function 'hix5hd2_clk_register_complex':
>> drivers/clk/hisilicon/clk-hix5hd2.c:260:46: warning: initialization discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
260 | struct hix5hd2_complex_clock *clks = clocks;
| ^~~~~~vim +/const +260 drivers/clk/hisilicon/clk-hix5hd2.c
255
256 static int
257 hix5hd2_clk_register_complex(struct device *dev, const void *clocks, int nums,
258 struct hisi_clock_data *data)
259 {
> 260 struct hix5hd2_complex_clock *clks = clocks;
261 void __iomem *base = data->base;
262 int i;
263
264 for (i = 0; i < nums; i++) {
265 struct hix5hd2_clk_complex *p_clk;
266 struct clk *clk;
267 struct clk_init_data init;
268
269 p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL);
270 if (!p_clk)
271 return -ENOMEM;
272
273 init.name = clks[i].name;
274 if (clks[i].type == TYPE_ETHER)
275 init.ops = &clk_ether_ops;
276 else
277 init.ops = &clk_complex_ops;
278
279 init.flags = 0;
280 init.parent_names =
281 (clks[i].parent_name ? &clks[i].parent_name : NULL);
282 init.num_parents = (clks[i].parent_name ? 1 : 0);
283
284 p_clk->ctrl_reg = base + clks[i].ctrl_reg;
285 p_clk->ctrl_clk_mask = clks[i].ctrl_clk_mask;
286 p_clk->ctrl_rst_mask = clks[i].ctrl_rst_mask;
287 p_clk->phy_reg = base + clks[i].phy_reg;
288 p_clk->phy_clk_mask = clks[i].phy_clk_mask;
289 p_clk->phy_rst_mask = clks[i].phy_rst_mask;
290 p_clk->hw.init = &init;
291
292 clk = clk_register(NULL, &p_clk->hw);
293 if (IS_ERR(clk)) {
294 kfree(p_clk);
295 pr_err("%s: failed to register clock %s\n",
296 __func__, clks[i].name);
297 return PTR_ERR(p_clk);
298 }
299
300 data->clk_data.clks[clks[i].id] = clk;
301 }
302
303 return 0;
304 }
305
Signature · 2 lines
0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests
PATCH v7 7/9 clk: hisilicon: Migrate devm APIs
In reply to David YangMigrates devm APIs for HiSilicon clock drivers.
Signed-off-by David Yang <[email protected]>
--- drivers/clk/hisilicon/clk-hi3559a.c | 29 +- drivers/clk/hisilicon/clk-hi3620.c | 28 +- drivers/clk/hisilicon/clk-hi6220-stub.c | 9 +- drivers/clk/hisilicon/clk-hi6220.c | 13 +- drivers/clk/hisilicon/clk-hisi-phase.c | 13 +- drivers/clk/hisilicon/clk-hix5hd2.c | 12 +- drivers/clk/hisilicon/clk.c | 330 +++++++--------------- drivers/clk/hisilicon/clk.h | 80 +++--- drivers/clk/hisilicon/clkdivider-hi6220.c | 24 +- drivers/clk/hisilicon/clkgate-separated.c | 26 +- 10 files changed, 230 insertions(+), 334 deletions(-)
drivers/clk/hisilicon/clk-hi3559a.c +13 -16
@@ -457,17 +457,16 @@ hisi_clk_register_pll(struct device *dev, const void *clocks, {const struct hi3559av100_pll_clock *clks = clocks;void __iomem *base = data->base; -struct hi3559av100_clk_pll *p_clk =NULL ; -struct clk *clk =NULL ; +struct hi3559av100_clk_pll *p_clk;struct clk_init_data init;int i; - - p_clk =devm_kzalloc (dev,sizeof (*p_clk) * nums,GFP_KERNEL ); - -if (!p_clk) -return -ENOMEM ; +int ret;for (i =0 ; i < nums; i++) { + p_clk =devm_kzalloc (dev,sizeof (*p_clk),GFP_KERNEL ); +if (!p_clk) +return -ENOMEM ; + init.name = clks[i].name; init.flags =0 ; init.parent_names =
@@ -490,16 +489,14 @@ hisi_clk_register_pll(struct device *dev, const void *clocks, p_clk->refdiv_width = clks[i].refdiv_width; p_clk->hw.init = &init; - clk =clk_register (NULL , &p_clk->hw); -if (IS_ERR (clk)) { -devm_kfree (dev, p_clk); + ret =devm_clk_hw_register (dev, &p_clk->hw); +if (ret) {dev_err (dev,"%s: failed to register clock %s\n" , - __func__, clks[i].name); -return PTR_ERR (clk); + __func__, clks[i].name); +return ret; } - data->clk_data.clks[clks[i].id] = clk; - p_clk++; + data->clk_data->hws[clks[i].id] = &p_clk->hw; }return 0 ;
@@ -628,7 +625,7 @@ static int hi3559av100_shub_default_clk_set(struct device *dev, struct hisi_clocvoid __iomem *crg_base;unsigned int val; - crg_base =ioremap (CRG_BASE_ADDR ,SZ_4K ); + crg_base =devm_ioremap (dev,CRG_BASE_ADDR ,SZ_4K );/* SSP: 192M/2 */ val =readl_relaxed (crg_base +0x20 );
@@ -640,7 +637,7 @@ static int hi3559av100_shub_default_clk_set(struct device *dev, struct hisi_cloc val |= (0x1 <<28 );writel_relaxed (val, crg_base +0x1C ); -iounmap (crg_base); +devm_iounmap (dev, crg_base); crg_base =NULL ;return 0 ;
drivers/clk/hisilicon/clk-hi3620.c +15 -13
@@ -11,12 +11,10 @@#include <linux/kernel.h> #include <linux/clk-provider.h> +#include <linux/device.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/of.h> -#include <linux/of_address.h> #include <linux/of_device.h> -#include <linux/slab.h> #include <dt-bindings/clock/hi3620-clock.h>
@@ -399,15 +397,15 @@ static const struct clk_ops clk_mmc_ops = { .recalc_rate = mmc_clk_recalc_rate, }; -static struct clk * +static struct clk_hw *clk_register_hisi_mmc (struct device *dev,const struct hisi_mmc_clock *mmc_clk,void __iomem *base) {struct clk_mmc *mclk; -struct clk *clk;struct clk_init_data init; +int ret; - mclk =kzalloc (sizeof (*mclk),GFP_KERNEL ); + mclk =devm_kzalloc (dev,sizeof (*mclk),GFP_KERNEL );if (!mclk)return ERR_PTR (-ENOMEM );
@@ -431,27 +429,31 @@ clk_register_hisi_mmc(struct device *dev, const struct hisi_mmc_clock *mmc_clk, mclk->sam_off = mmc_clk->sam_off; mclk->sam_bits = mmc_clk->sam_bits; - clk =clk_register (NULL , &mclk->hw); -if (WARN_ON (IS_ERR (clk))) -kfree (mclk); -return clk; + ret =devm_clk_hw_register (dev, &mclk->hw); +if (ret) { +dev_err (dev,"%s: failed to register clock %s\n" , + __func__, clks[i].name); +return ret; + } + +return &mclk->hw; }static int hisi_register_clk_mmc (struct device *dev,const void *clocks,int nums,struct hisi_clock_data *data) {const struct hisi_mmc_clock *clks = clocks; -struct clk *clk;int i;for (i =0 ; i < nums; i++) { - clk =clk_register_hisi_mmc (dev, &clks[i], data->base); +struct clk_hw *clk =clk_register_hisi_mmc (dev, &clks[i], data->base); +if (IS_ERR (clk)) {pr_err ("%s: failed to register clock %s\n" , __func__, clks[i].name);return PTR_ERR (clk); } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = clk; }return 0 ;
drivers/clk/hisilicon/clk-hi6220-stub.c +4 -5
@@ -195,7 +195,6 @@ static int hi6220_stub_clk_probe(struct platform_device *pdev)struct device *dev = &pdev->dev;struct clk_init_data init;struct hi6220_stub_clk *stub_clk; -struct clk *clk;struct device_node *np = pdev->dev.of_node;int ret;
@@ -233,11 +232,11 @@ static int hi6220_stub_clk_probe(struct platform_device *pdev) init.num_parents =0 ; init.flags =0 ; - clk =devm_clk_register (dev, &stub_clk->hw); -if (IS_ERR (clk)) -return PTR_ERR (clk); + ret =devm_clk_hw_register (dev, &stub_clk->hw); +if (ret) +return ret; - ret =of_clk_add_provider (np, of_clk_src_simple_get, clk); + ret =devm_of_clk_add_hw_provider (dev, of_clk_hw_simple_get, &stub_clk->hw);if (ret) {dev_err (dev,"failed to register OF clock provider\n" );return ret;
drivers/clk/hisilicon/clk-hi6220.c +10 -3
@@ -16,6 +16,13 @@#include "clk.h" +static int +hi6220_clk_register_divider_stub (struct device *dev,const void *clks, +int num,struct hisi_clock_data *data) +{ +return hi6220_clk_register_divider (dev, clks, num, data); +} +/* clocks in AO (always on) controller */ static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] = { {HI6220_REF32K ,"ref32k" ,NULL ,0 ,32764 , },
@@ -176,7 +183,7 @@ static const struct hisi_clocks hi6220_sys_clks = { .gate_sep_clks_num = ARRAY_SIZE(hi6220_separated_gate_clks_sys), .customized_clks = hi6220_div_clks_sys, .customized_clks_num = ARRAY_SIZE(hi6220_div_clks_sys), - .clk_register_customized = hi6220_clk_register_divider, + .clk_register_customized = hi6220_clk_register_divider_stub, };/* clocks in media controller */
@@ -224,7 +231,7 @@ static const struct hisi_clocks hi6220_media_clks = { .gate_sep_clks_num = ARRAY_SIZE(hi6220_separated_gate_clks_media), .customized_clks = hi6220_div_clks_media, .customized_clks_num = ARRAY_SIZE(hi6220_div_clks_media), - .clk_register_customized = hi6220_clk_register_divider, + .clk_register_customized = hi6220_clk_register_divider_stub, };/* clocks in pmctrl */
@@ -247,7 +254,7 @@ static const struct hisi_clocks hi6220_power_clks = { .gate_clks_num = ARRAY_SIZE(hi6220_gate_clks_power), .customized_clks = hi6220_div_clks_power, .customized_clks_num = ARRAY_SIZE(hi6220_div_clks_power), - .clk_register_customized = hi6220_clk_register_divider, + .clk_register_customized = hi6220_clk_register_divider_stub, };/* clocks in acpu */
drivers/clk/hisilicon/clk-hisi-phase.c +9 -4
@@ -5,11 +5,11 @@* Simple HiSilicon phase clock implementation. */ +#include <linux/device.h> #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> -#include <linux/slab.h> #include "clk.h"
@@ -90,12 +90,13 @@ static const struct clk_ops clk_phase_ops = { .set_phase = hisi_clk_set_phase, }; -struct clk *clk_register_hisi_phase (struct device *dev, +struct clk_hw *devm_clk_hw_register_hisi_phase (struct device *dev,const struct hisi_phase_clock *clks,void __iomem *base,spinlock_t *lock) {struct clk_hisi_phase *phase;struct clk_init_data init; +int ret; phase =devm_kzalloc (dev,sizeof (struct clk_hisi_phase ),GFP_KERNEL );if (!phase)
@@ -116,6 +117,10 @@ struct clk *clk_register_hisi_phase(struct device *dev, phase->phase_num = clks->phase_num; phase->hw.init = &init; -return devm_clk_register (dev, &phase->hw); + ret =devm_clk_hw_register (dev, &phase->hw); +if (ret) +return ERR_PTR (ret); + +return &phase->hw; } -EXPORT_SYMBOL_GPL (clk_register_hisi_phase); +EXPORT_SYMBOL_GPL (devm_clk_hw_register_hisi_phase);
drivers/clk/hisilicon/clk-hix5hd2.c +6 -6
@@ -6,7 +6,7 @@#include <dt-bindings/clock/hix5hd2-clock.h> -#include <linux/slab.h> +#include <linux/device.h> #include <linux/delay.h> #include <linux/kernel.h> #include <linux/module.h>
@@ -260,13 +260,14 @@ hix5hd2_clk_register_complex(struct device *dev, const void *clocks, int nums,struct hix5hd2_complex_clock *clks = clocks;void __iomem *base = data->base;int i; +int ret;for (i =0 ; i < nums; i++) {struct hix5hd2_clk_complex *p_clk;struct clk *clk;struct clk_init_data init; - p_clk =kzalloc (sizeof (*p_clk),GFP_KERNEL ); + p_clk =devm_kzalloc (dev,sizeof (*p_clk),GFP_KERNEL );if (!p_clk)return -ENOMEM ;
@@ -289,12 +290,11 @@ hix5hd2_clk_register_complex(struct device *dev, const void *clocks, int nums, p_clk->phy_rst_mask = clks[i].phy_rst_mask; p_clk->hw.init = &init; - clk =clk_register (NULL , &p_clk->hw); -if (IS_ERR (clk)) { -kfree (p_clk); + ret =devm_clk_hw_register (dev, &p_clk->hw); +if (ret) {pr_err ("%s: failed to register clock %s\n" , __func__, clks[i].name); -return PTR_ERR (p_clk); +return ret; } data->clk_data.clks[clks[i].id] = clk;
drivers/clk/hisilicon/clk.c +108 -222
419 lines not on this page · raw message
drivers/clk/hisilicon/clk.h +41 -39
110 lines not on this page · raw message
drivers/clk/hisilicon/clkdivider-hi6220.c +10 -14
@@ -9,7 +9,7 @@#include <linux/kernel.h> #include <linux/clk-provider.h> -#include <linux/slab.h> +#include <linux/device.h> #include <linux/io.h> #include <linux/err.h> #include <linux/spinlock.h>
@@ -97,19 +97,19 @@ static const struct clk_ops hi6220_clkdiv_ops = { .set_rate = hi6220_clkdiv_set_rate, }; -struct clk *hi6220_register_clkdiv (struct device *dev,const char *name, +struct clk_hw *devm_clk_hw_register_hi6220_divider (struct device *dev,const char *name,const char *parent_name,unsigned long flags,void __iomem *reg,u8 shift,u8 width,u32 mask_bit,spinlock_t *lock) {struct hi6220_clk_divider *div; -struct clk *clk;struct clk_init_data init;struct clk_div_table *table;u32 max_div, min_div;int i; +int ret;/* allocate the divider */ - div =kzalloc (sizeof (*div),GFP_KERNEL ); + div =devm_kzalloc (dev,sizeof (*div),GFP_KERNEL );if (!div)return ERR_PTR (-ENOMEM );
@@ -117,11 +117,9 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, max_div =div_mask (width) +1 ; min_div =1 ; - table =kcalloc (max_div +1 ,sizeof (*table),GFP_KERNEL ); -if (!table) { -kfree (div); + table =devm_kcalloc (dev, max_div +1 ,sizeof (*table),GFP_KERNEL ); +if (!table)return ERR_PTR (-ENOMEM ); - }for (i =0 ; i < max_div; i++) { table[i].div = min_div + i;
@@ -144,11 +142,9 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, div->table = table;/* register the clock */ - clk =clk_register (dev, &div->hw); -if (IS_ERR (clk)) { -kfree (table); -kfree (div); - } + ret =devm_clk_hw_register (dev, &div->hw); +if (ret) +return ERR_PTR (ret); -return clk; +return &div->hw; }
drivers/clk/hisilicon/clkgate-separated.c +14 -12
@@ -11,8 +11,8 @@#include <linux/kernel.h> #include <linux/clk-provider.h> +#include <linux/device.h> #include <linux/io.h> -#include <linux/slab.h> #include "clk.h"
@@ -80,17 +80,18 @@ static const struct clk_ops clkgate_separated_ops = { .is_enabled = clkgate_separated_is_enabled, }; -struct clk *hisi_register_clkgate_sep (struct device *dev,const char *name, -const char *parent_name, -unsigned long flags, -void __iomem *reg,u8 bit_idx, -u8 clk_gate_flags,spinlock_t *lock) +struct clk_hw * +devm_clk_hw_register_hisi_gate_sep (struct device *dev,const char *name, +const char *parent_name, +unsigned long flags, +void __iomem *reg,u8 bit_idx, +u8 clk_gate_flags,spinlock_t *lock) {struct clkgate_separated *sclk; -struct clk *clk;struct clk_init_data init; +int ret; - sclk =kzalloc (sizeof (*sclk),GFP_KERNEL ); + sclk =devm_kzalloc (dev,sizeof (*sclk),GFP_KERNEL );if (!sclk)return ERR_PTR (-ENOMEM );
@@ -106,8 +107,9 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, sclk->hw.init = &init; sclk->lock = lock; - clk =clk_register (dev, &sclk->hw); -if (IS_ERR (clk)) -kfree (sclk); -return clk; + ret =devm_clk_hw_register (dev, &sclk->hw); +if (ret) +return ERR_PTR (ret); + +return &sclk->hw; }
Signature · 1 line
2.39.2
kernel test robot
build botRe: [PATCH v7 7/9] clk: hisilicon: Migrate devm APIs
Thank you for the patch! Yet something to improve:
Hi David,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on 6015b1aca1a233379625385feb01dd014aca60b5]
url: https://github.com/intel-lab-lkp/linux/commits/David-Yang/clk-hisilicon-Rename-Hi3798CV200-to-Hi3798/20230323-004453 base: 6015b1aca1a233379625385feb01dd014aca60b5 patch link: https://lore.kernel.org/r/20230322164201.2454771-8-mmyangfl%40gmail.com patch subject: [PATCH v7 7/9] clk: hisilicon: Migrate devm APIs config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20230323/[email protected]/config) compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/8d88e46ef325130e4dd516ce36e3e0484bc52230
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review David-Yang/clk-hisilicon-Rename-Hi3798CV200-to-Hi3798/20230323-004453 git checkout 8d88e46ef325130e4dd516ce36e3e0484bc52230
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm olddefconfig COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/clk/hisilicon/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
| Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All error/warnings (new ones prefixed by >>):
In file included from include/linux/device.h:15,
from drivers/clk/hisilicon/clk-hi3620.c:14:
drivers/clk/hisilicon/clk-hi3620.c: In function 'clk_register_hisi_mmc':
>> drivers/clk/hisilicon/clk-hi3620.c:435:35: error: 'clks' undeclared (first use in this function); did you mean 'clk'?
435 | __func__, clks[i].name);
| ^~~~
include/linux/dev_printk.h:110:37: note: in definition of macro 'dev_printk_index_wrap'
110 | _p_func(dev, fmt, ##__VA_ARGS__); \
| ^~~~~~~~~~~
drivers/clk/hisilicon/clk-hi3620.c:434:17: note: in expansion of macro 'dev_err'
434 | dev_err(dev, "%s: failed to register clock %s\n",
| ^~~~~~~
drivers/clk/hisilicon/clk-hi3620.c:435:35: note: each undeclared identifier is reported only once for each function it appears in
435 | __func__, clks[i].name);
| ^~~~
include/linux/dev_printk.h:110:37: note: in definition of macro 'dev_printk_index_wrap'
110 | _p_func(dev, fmt, ##__VA_ARGS__); \
| ^~~~~~~~~~~
drivers/clk/hisilicon/clk-hi3620.c:434:17: note: in expansion of macro 'dev_err'
434 | dev_err(dev, "%s: failed to register clock %s\n",
| ^~~~~~~
>> drivers/clk/hisilicon/clk-hi3620.c:435:40: error: 'i' undeclared (first use in this function)
435 | __func__, clks[i].name);
| ^
include/linux/dev_printk.h:110:37: note: in definition of macro 'dev_printk_index_wrap'
110 | _p_func(dev, fmt, ##__VA_ARGS__); \
| ^~~~~~~~~~~
drivers/clk/hisilicon/clk-hi3620.c:434:17: note: in expansion of macro 'dev_err'
434 | dev_err(dev, "%s: failed to register clock %s\n",
| ^~~~~~~
>> drivers/clk/hisilicon/clk-hi3620.c:436:24: warning: returning 'int' from a function with return type 'struct clk_hw *' makes pointer from integer without a cast [-Wint-conversion]
436 | return ret;
| ^~~
--
drivers/clk/hisilicon/clk-hix5hd2.c: In function 'hix5hd2_clk_register_complex':
drivers/clk/hisilicon/clk-hix5hd2.c:260:46: warning: initialization discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
260 | struct hix5hd2_complex_clock *clks = clocks;
| ^~~~~~
>> drivers/clk/hisilicon/clk-hix5hd2.c:300:31: error: 'data->clk_data' is a pointer; did you mean to use '->'?
300 | data->clk_data.clks[clks[i].id] = clk;
| ^
| ->vim +435 drivers/clk/hisilicon/clk-hi3620.c
399
400 static struct clk_hw *
401 clk_register_hisi_mmc(struct device *dev, const struct hisi_mmc_clock *mmc_clk,
402 void __iomem *base)
403 {
404 struct clk_mmc *mclk;
405 struct clk_init_data init;
406 int ret;
407
408 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
409 if (!mclk)
410 return ERR_PTR(-ENOMEM);
411
412 init.name = mmc_clk->name;
413 init.ops = &clk_mmc_ops;
414 init.flags = mmc_clk->flags;
415 init.parent_names = (mmc_clk->parent_name ? &mmc_clk->parent_name : NULL);
416 init.num_parents = (mmc_clk->parent_name ? 1 : 0);
417 mclk->hw.init = &init;
418
419 mclk->id = mmc_clk->id;
420 mclk->clken_reg = base + mmc_clk->clken_reg;
421 mclk->clken_bit = mmc_clk->clken_bit;
422 mclk->div_reg = base + mmc_clk->div_reg;
423 mclk->div_off = mmc_clk->div_off;
424 mclk->div_bits = mmc_clk->div_bits;
425 mclk->drv_reg = base + mmc_clk->drv_reg;
426 mclk->drv_off = mmc_clk->drv_off;
427 mclk->drv_bits = mmc_clk->drv_bits;
428 mclk->sam_reg = base + mmc_clk->sam_reg;
429 mclk->sam_off = mmc_clk->sam_off;
430 mclk->sam_bits = mmc_clk->sam_bits;
431
432 ret = devm_clk_hw_register(dev, &mclk->hw);
433 if (ret) {
434 dev_err(dev, "%s: failed to register clock %s\n",
> 435 __func__, clks[i].name); > 436 return ret;
437 }
438
439 return &mclk->hw;
440 }
441
Signature · 2 lines
0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests
PATCH v7 8/9 dt-bindings: clock: Add Hi3798MV100 CRG
In reply to David YangAdd CRG bindings for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC.
Signed-off-by David Yang <[email protected]>
--- .../devicetree/bindings/clock/hisi-crg.txt | 2 ++ include/dt-bindings/clock/histb-clock.h | 13 +++++++++++++ 2 files changed, 15 insertions(+)
Documentation/devicetree/bindings/clock/hisi-crg.txt +2 -0
@@ -13,6 +13,8 @@ Required Properties: - "hisilicon,hi3516cv300-crg" - "hisilicon,hi3516cv300-sysctrl" - "hisilicon,hi3519-crg" + - "hisilicon,hi3798mv100-crg" + - "hisilicon,hi3798mv100-sysctrl" - "hisilicon,hi3798cv200-crg" - "hisilicon,hi3798cv200-sysctrl"
include/dt-bindings/clock/histb-clock.h +13 -0
@@ -58,6 +58,19 @@#define HISTB_USB3_UTMI_CLK1 48#define HISTB_USB3_PIPE_CLK1 49#define HISTB_USB3_SUSPEND_CLK1 50 +#define HISTB_USB2_UTMI_CLK1 51 +#define HISTB_USB2_2_BUS_CLK 52 +#define HISTB_USB2_2_PHY_CLK 53 +#define HISTB_USB2_2_UTMI_CLK 54 +#define HISTB_USB2_2_UTMI_CLK1 55 +#define HISTB_USB2_2_12M_CLK 56 +#define HISTB_USB2_2_48M_CLK 57 +#define HISTB_USB2_2_OTG_UTMI_CLK 58 +#define HISTB_USB2_2_PHY1_REF_CLK 59 +#define HISTB_USB2_2_PHY2_REF_CLK 60 +#define HISTB_FEPHY_CLK 61 +#define HISTB_GPU_BUS_CLK 62 +#define HISTB_GPU_CORE_CLK 63/* clocks provided by mcu CRG */ #define HISTB_MCE_CLK 1
Signature · 1 line
2.39.2
PATCH v7 9/9 clk: hisilicon: Add CRG driver for Hi3798MV100 SoC
In reply to David YangAdd CRG driver for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC.
Signed-off-by David Yang <[email protected]>
--- drivers/clk/hisilicon/crg-hi3798.c | 249 +++++++++++++++++++++++++++++ 1 file changed, 249 insertions(+)
drivers/clk/hisilicon/crg-hi3798.c +249 -0
@@ -7,6 +7,7 @@#include <dt-bindings/clock/histb-clock.h> +#include <linux/clk-provider.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of_device.h>
@@ -38,6 +39,9 @@#define HI3798_FIXED_166P5M 84#define HI3798_SDIO0_MUX 85#define HI3798_COMBPHY0_MUX 86 +#define HI3798_FIXED_3M 87 +#define HI3798_FIXED_15M 88 +#define HI3798_FIXED_83P3M 89#define HI3798_CRG_NR_CLKS 128
@@ -47,13 +51,16 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = { { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, + { HI3798_FIXED_3M, "3m", NULL, 0, 3000000, }, { HI3798_FIXED_12M, "12m", NULL, 0, 12000000, }, + { HI3798_FIXED_15M, "15m", NULL, 0, 15000000, }, { HI3798_FIXED_24M, "24m", NULL, 0, 24000000, }, { HI3798_FIXED_25M, "25m", NULL, 0, 25000000, }, { HI3798_FIXED_48M, "48m", NULL, 0, 48000000, }, { HI3798_FIXED_50M, "50m", NULL, 0, 50000000, }, { HI3798_FIXED_60M, "60m", NULL, 0, 60000000, }, { HI3798_FIXED_75M, "75m", NULL, 0, 75000000, }, + { HI3798_FIXED_83P3M, "83p3m", NULL, 0, 83333333, }, { HI3798_FIXED_100M, "100m", NULL, 0, 100000000, }, { HI3798_FIXED_150M, "150m", NULL, 0, 150000000, }, { HI3798_FIXED_166P5M, "166p5m", NULL, 0, 165000000, },
@@ -61,6 +68,106 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = { { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, }, }; +struct hi3798_complex_clock { +unsigned int id; +const char *name; +const char *parent_name; +unsigned long flags; +unsigned long offset; +u32 mask; +u32 value; +}; + +struct hi3798_clk_complex { +struct clk_hw hw; +void __iomem *reg; +u32 mask; +u32 value; +}; + +#define to_complex_clk (_hw) container_of(_hw, struct hi3798_clk_complex, hw) + +static int hi3798_clk_complex_prepare (struct clk_hw *hw) +{ +struct hi3798_clk_complex *clk =to_complex_clk (hw); +u32 val; + + val =readl_relaxed (clk->reg); + val &= ~(clk->mask); + val |= clk->value; +writel_relaxed (val, clk->reg); + +return 0 ; +} + +static void hi3798_clk_complex_unprepare (struct clk_hw *hw) +{ +struct hi3798_clk_complex *clk =to_complex_clk (hw); +u32 val; + + val =readl_relaxed (clk->reg); + val &= ~(clk->mask); +writel_relaxed (val, clk->reg); +} + +static int hi3798_clk_complex_is_prepared (struct clk_hw *hw) +{ +struct hi3798_clk_complex *clk =to_complex_clk (hw); +u32 val; + + val =readl_relaxed (clk->reg); +return (val & clk->mask) == clk->value; +} + +static const struct clk_ops hi3798_clk_complex_ops = { + .prepare = hi3798_clk_complex_prepare, + .unprepare = hi3798_clk_complex_unprepare, + .is_prepared = hi3798_clk_complex_is_prepared, +}; + +static int hi3798_clk_register_complex (struct device *dev, +const void *clocks,int nums, +struct hisi_clock_data *data) +{ +const struct hi3798_complex_clock *clks = clocks; +void __iomem *base = data->base; +int i; + +for (i =0 ; i < nums; i++) { +struct hi3798_clk_complex *p_clk; +struct clk_init_data init; +int ret; + + p_clk =devm_kzalloc (dev,sizeof (*p_clk),GFP_KERNEL ); +if (!p_clk) +return -ENOMEM ; + + init.name = clks[i].name; + init.ops = &hi3798_clk_complex_ops; + + init.flags =0 ; + init.parent_names = + (clks[i].parent_name ? &clks[i].parent_name :NULL ); + init.num_parents = (clks[i].parent_name ?1 :0 ); + + p_clk->reg = base + clks[i].offset; + p_clk->mask = clks[i].mask; + p_clk->value = clks[i].value; + p_clk->hw.init = &init; + + ret =devm_clk_hw_register (dev, &p_clk->hw); +if (ret) { +pr_err ("%s: failed to register clock %s\n" , + __func__, clks[i].name); +return ret; + } + + data->clk_data->hws[clks[i].id] = &p_clk->hw; + } + +return 0 ; +} +/* hi3798CV200 */ static const char *const hi3798cv200_mmc_mux_p[] = {
@@ -225,11 +332,153 @@ static const struct hisi_clocks hi3798cv200_sysctrl_clks = { .gate_clks_num = ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), }; +/* hi3798MV100 */ + +static const char *const hi3798mv100_mmc_mux_p[] = { +"75m" ,"100m" ,"50m" ,"15m" }; +static u32 hi3798mv100_mmc_mux_table[] = {0 ,1 ,2 ,3 }; + +static struct hisi_mux_clock hi3798mv100_mux_clks[] = { + {HI3798_MMC_MUX ,"mmc_mux" , hi3798mv100_mmc_mux_p, +ARRAY_SIZE (hi3798mv100_mmc_mux_p),CLK_SET_RATE_PARENT , +0xa0 ,8 ,2 ,0 , hi3798mv100_mmc_mux_table, }, + {HI3798_SDIO0_MUX ,"sdio0_mux" , hi3798mv100_mmc_mux_p, +ARRAY_SIZE (hi3798mv100_mmc_mux_p),CLK_SET_RATE_PARENT , +0x9c ,8 ,2 ,0 , hi3798mv100_mmc_mux_table, }, +}; + +static const struct hisi_gate_clock hi3798mv100_gate_clks[] = { +/* NAND */ +/* hi3798MV100 NAND driver does not get into mainline yet, +* expose these clocks when it gets ready */ +/* { HISTB_NAND_CLK, "clk_nand", "clk_apb", +CLK_SET_RATE_PARENT, 0x60, 0, 0, }, */ +/* UART */ + {HISTB_UART1_CLK ,"clk_uart1" ,"3m" , +CLK_SET_RATE_PARENT |CLK_IS_CRITICAL ,0x68 ,0 ,0 , }, + {HISTB_UART2_CLK ,"clk_uart2" ,"83p3m" , +CLK_SET_RATE_PARENT ,0x68 ,4 ,0 , }, +/* I2C */ + {HISTB_I2C0_CLK ,"clk_i2c0" ,"clk_apb" , +CLK_SET_RATE_PARENT ,0x6C ,4 ,0 , }, + {HISTB_I2C1_CLK ,"clk_i2c1" ,"clk_apb" , +CLK_SET_RATE_PARENT ,0x6C ,8 ,0 , }, + {HISTB_I2C2_CLK ,"clk_i2c2" ,"clk_apb" , +CLK_SET_RATE_PARENT ,0x6C ,12 ,0 , }, +/* SPI */ + {HISTB_SPI0_CLK ,"clk_spi0" ,"clk_apb" , +CLK_SET_RATE_PARENT ,0x70 ,0 ,0 , }, +/* SDIO */ + {HISTB_SDIO0_BIU_CLK ,"clk_sdio0_biu" ,"200m" , +CLK_SET_RATE_PARENT ,0x9c ,0 ,0 , }, + {HISTB_SDIO0_CIU_CLK ,"clk_sdio0_ciu" ,"sdio0_mux" , +CLK_SET_RATE_PARENT ,0x9c ,1 ,0 , }, +/* EMMC */ + {HISTB_MMC_BIU_CLK ,"clk_mmc_biu" ,"200m" , +CLK_SET_RATE_PARENT ,0xa0 ,0 ,0 , }, + {HISTB_MMC_CIU_CLK ,"clk_mmc_ciu" ,"mmc_mux" , +CLK_SET_RATE_PARENT ,0xa0 ,1 ,0 , }, +/* USB2 */ + {HISTB_USB2_BUS_CLK ,"clk_u2_bus" ,"clk_ahb" , +CLK_SET_RATE_PARENT ,0xb8 ,0 ,0 , }, + {HISTB_USB2_PHY_CLK ,"clk_u2_phy" ,"60m" , +CLK_SET_RATE_PARENT ,0xb8 ,4 ,0 , }, + {HISTB_USB2_12M_CLK ,"clk_u2_12m" ,"12m" , +CLK_SET_RATE_PARENT ,0xb8 ,2 ,0 }, + {HISTB_USB2_48M_CLK ,"clk_u2_48m" ,"48m" , +CLK_SET_RATE_PARENT ,0xb8 ,1 ,0 }, + {HISTB_USB2_UTMI_CLK ,"clk_u2_utmi" ,"60m" , +CLK_SET_RATE_PARENT ,0xb8 ,5 ,0 }, + {HISTB_USB2_UTMI_CLK1 ,"clk_u2_utmi1" ,"60m" , +CLK_SET_RATE_PARENT ,0xb8 ,6 ,0 }, + {HISTB_USB2_OTG_UTMI_CLK ,"clk_u2_otg_utmi" ,"60m" , +CLK_SET_RATE_PARENT ,0xb8 ,3 ,0 }, + {HISTB_USB2_PHY1_REF_CLK ,"clk_u2_phy1_ref" ,"24m" , +CLK_SET_RATE_PARENT ,0xbc ,0 ,0 }, + {HISTB_USB2_PHY2_REF_CLK ,"clk_u2_phy2_ref" ,"24m" , +CLK_SET_RATE_PARENT ,0xbc ,2 ,0 }, +/* USB2 2 */ + {HISTB_USB2_2_BUS_CLK ,"clk_u2_2_bus" ,"clk_ahb" , +CLK_SET_RATE_PARENT ,0x198 ,0 ,0 , }, + {HISTB_USB2_2_PHY_CLK ,"clk_u2_2_phy" ,"60m" , +CLK_SET_RATE_PARENT ,0x198 ,4 ,0 , }, + {HISTB_USB2_2_12M_CLK ,"clk_u2_2_12m" ,"12m" , +CLK_SET_RATE_PARENT ,0x198 ,2 ,0 }, + {HISTB_USB2_2_48M_CLK ,"clk_u2_2_48m" ,"48m" , +CLK_SET_RATE_PARENT ,0x198 ,1 ,0 }, + {HISTB_USB2_2_UTMI_CLK ,"clk_u2_2_utmi" ,"60m" , +CLK_SET_RATE_PARENT ,0x198 ,5 ,0 }, + {HISTB_USB2_2_UTMI_CLK1 ,"clk_u2_2_utmi1" ,"60m" , +CLK_SET_RATE_PARENT ,0x198 ,6 ,0 }, + {HISTB_USB2_2_OTG_UTMI_CLK ,"clk_u2_2_otg_utmi" ,"60m" , +CLK_SET_RATE_PARENT ,0x198 ,3 ,0 }, + {HISTB_USB2_2_PHY1_REF_CLK ,"clk_u2_2_phy1_ref" ,"24m" , +CLK_SET_RATE_PARENT ,0x190 ,0 ,0 }, + {HISTB_USB2_2_PHY2_REF_CLK ,"clk_u2_2_phy2_ref" ,"24m" , +CLK_SET_RATE_PARENT ,0x190 ,2 ,0 }, +/* USB3 */ + {HISTB_USB3_BUS_CLK ,"clk_u3_bus" ,NULL , +CLK_SET_RATE_PARENT ,0xb0 ,0 ,0 }, + {HISTB_USB3_UTMI_CLK ,"clk_u3_utmi" ,NULL , +CLK_SET_RATE_PARENT ,0xb0 ,4 ,0 }, + {HISTB_USB3_PIPE_CLK ,"clk_u3_pipe" ,NULL , +CLK_SET_RATE_PARENT ,0xb0 ,3 ,0 }, + {HISTB_USB3_SUSPEND_CLK ,"clk_u3_suspend" ,NULL , +CLK_SET_RATE_PARENT ,0xb0 ,2 ,0 }, +/* GPU */ + {HISTB_GPU_BUS_CLK ,"clk_gpu" ,"200m" , +CLK_SET_RATE_PARENT ,0xd4 ,0 ,0 }, +/* FEPHY */ + {HISTB_FEPHY_CLK ,"clk_fephy" ,"25m" , +CLK_SET_RATE_PARENT ,0x120 ,0 ,0 , }, +}; + +static const struct hi3798_complex_clock hi3798mv100_complex_clks[] = { + {HISTB_ETH0_MAC_CLK ,"clk_mac0" ,NULL , +CLK_SET_RATE_PARENT ,0xcc ,0xf ,0xb , }, + {HISTB_GPU_CORE_CLK ,"clk_gpu_gp" ,"200m" , +CLK_SET_RATE_PARENT ,0xd4 ,0x700 ,0x700 , }, +}; + +static const struct hisi_clocks hi3798mv100_crg_clks = { + .nr =HI3798_CRG_NR_CLKS , + .fixed_rate_clks = hi3798_fixed_rate_clks, + .fixed_rate_clks_num =ARRAY_SIZE (hi3798_fixed_rate_clks), + .gate_clks = hi3798mv100_gate_clks, + .gate_clks_num =ARRAY_SIZE (hi3798mv100_gate_clks), + .mux_clks = hi3798mv100_mux_clks, + .mux_clks_num =ARRAY_SIZE (hi3798mv100_mux_clks), + .phase_clks = hi3798cv200_phase_clks, + .phase_clks_num =ARRAY_SIZE (hi3798cv200_phase_clks), + .customized_clks = hi3798mv100_complex_clks, + .customized_clks_num =ARRAY_SIZE (hi3798mv100_complex_clks), + .clk_register_customized = hi3798_clk_register_complex, +}; + +static const struct hisi_gate_clock hi3798mv100_sysctrl_gate_clks[] = { + {HISTB_IR_CLK ,"clk_ir" ,"24m" , +CLK_SET_RATE_PARENT ,0x48 ,4 ,0 , }, + {HISTB_TIMER01_CLK ,"clk_timer01" ,"24m" , +CLK_SET_RATE_PARENT ,0x48 ,6 ,0 , }, + {HISTB_UART0_CLK ,"clk_uart0" ,"83p3m" , +CLK_SET_RATE_PARENT ,0x48 ,12 ,0 , }, +}; + +static const struct hisi_clocks hi3798mv100_sysctrl_clks = { + .nr =HI3798_SYSCTRL_NR_CLKS , + .gate_clks = hi3798mv100_sysctrl_gate_clks, + .gate_clks_num =ARRAY_SIZE (hi3798mv100_sysctrl_gate_clks), +}; +static const struct of_device_id hi3798_crg_match_table[] = { { .compatible ="hisilicon,hi3798cv200-crg" , .data = &hi3798cv200_crg_clks }, { .compatible ="hisilicon,hi3798cv200-sysctrl" , .data = &hi3798cv200_sysctrl_clks }, + { .compatible ="hisilicon,hi3798mv100-crg" , + .data = &hi3798mv100_crg_clks }, + { .compatible ="hisilicon,hi3798mv100-sysctrl" , + .data = &hi3798mv100_sysctrl_clks }, { } };MODULE_DEVICE_TABLE (of, hi3798_crg_match_table);
Signature · 1 line
2.39.2