arm64: dts: qcom: sa8775p: add basic PMIC support
Subsystems (10)
v3 cover arm64: dts: qcom: sa8775p: add basic PMIC support
From: Bartosz Golaszewski <[email protected]>
This adds support for a number of PMIC functionalities on sa8775p. The PMIC used on the reference board is pm8654au which is another variant of the SPMI PMIC from Qualcomm with an automotive twist.
v2 -> v3:
- add GPIO line names for the PMIC GPIOs on sa8775p-ride
- add missing GPIO chips to the PMIC .dtsi
- add missing thermal zones and alerts
- add regulators (driver support and regulator settings for sa8775p-ride)
- add missing PDC mappings
- squash patches 7 and 8 to avoid adding code without users
- dropped Krzysztof's Ack from patch 3 as it now extends the max number of mappings so most likely needs a second look
v1 -> v2:
- improve DT coding style where needed
- don't disable the power button in PMIC's .dtsi
- add debounce time for pwrkey and resin inputs
- use the official PMIC's name in DT labels
- add reg-names property for the PON node
- add patches that tidy up the dtsi before the PMIC stuff
Bartosz Golaszewski (18):
arm64: dts: qcom: sa8775p: pad reg properties to 8 digits
arm64: dts: qcom: sa8775p: sort soc nodes by reg property
dt-bindings: interrupt-controller: qcom-pdc: add compatible for
sa8775p
arm64: dts: qcom: sa8775p: add the pdc node
arm64: dts: qcom: sa8775p: add the spmi node
dt-bindings: mfd: qcom,spmi-pmic: add compatible for pmm8654au
arm64: dts: qcom: sa8775p: add support for the on-board PMICs
arm64: dts: qcom: sa8775p: add the Power On device node
arm64: dts: qcom: sa8775p: pmic: add the power key
arm64: dts: qcom: sa8775p: pmic: add support for the pmm8654 RESIN
input
arm64: dts: qcom: sa8775p: pmic: add thermal zones
dt-bindings: pinctrl: qcom,pmic-gpio: add compatible for
pmm8654au-gpio pinctrl: qcom: spmi-gpio: add support for pmm8654au-gpio
arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes
arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs
dt-bindings: regulator: qcom,rpmh: add compatible for pmm8654au RPMH
regulator: qcom-rpmh: add support for pmm8654au regulators
arm64: dts: qcom: sa8775p-ride: add PMIC regulators
.../interrupt-controller/qcom,pdc.yaml | 3 +- .../bindings/mfd/qcom,spmi-pmic.yaml | 1 + .../bindings/pinctrl/qcom,pmic-gpio.yaml | 2 + .../regulator/qcom,rpmh-regulator.yaml | 14 + arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 211 ++++++++ arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 285 +++++++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 465 ++++++++++-------- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + drivers/regulator/qcom-rpmh-regulator.c | 55 +++ 9 files changed, 838 insertions(+), 199 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
Signature · 1 line
2.37.2
PATCH v3 1/18 arm64: dts: qcom: sa8775p: pad reg properties to 8 digits
From: Bartosz Golaszewski <[email protected]>
The file has inconsistent padding of the address part of soc node children's reg properties. Fix it.
Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +6 -6
@@ -440,7 +440,7 @@ soc: soc@0 { gcc: clock-controller@100000 { compatible = "qcom,sa8775p-gcc"; - reg = <0x0 0x100000 0x0 0xc7018>; + reg = <0x0 0x00100000 0x0 0xc7018>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;
@@ -464,7 +464,7 @@ gcc: clock-controller@100000 { ipcc: mailbox@408000 { compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; - reg = <0x0 0x408000 0x0 0x1000>; + reg = <0x0 0x00408000 0x0 0x1000>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>;
@@ -473,7 +473,7 @@ ipcc: mailbox@408000 { qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; - reg = <0x0 0xac0000 0x0 0x6000>; + reg = <0x0 0x00ac0000 0x0 0x6000>; #address-cells = <2>; #size-cells = <2>; ranges;
@@ -485,7 +485,7 @@ qupv3_id_1: geniqup@ac0000 { uart10: serial@a8c000 { compatible = "qcom,geni-uart"; - reg = <0x0 0xa8c000 0x0 0x4000>; + reg = <0x0 0x00a8c000 0x0 0x4000>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
@@ -735,7 +735,7 @@ rpmhpd_opp_turbo_l1: opp-9 { tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x1f40000 0x0 0x20000>; + reg = <0x0 0x01f40000 0x0 0x20000>; #hwlock-cells = <1>; };
@@ -754,7 +754,7 @@ cpufreq_hw: cpufreq@18591000 { tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; - reg = <0x0 0xf000000 0x0 0x1000000>; + reg = <0x0 0x0f000000 0x0 0x1000000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>;
Signature · 1 line
2.37.2
PATCH v3 2/18 arm64: dts: qcom: sa8775p: sort soc nodes by reg property
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Sort all children of the soc node by the first address in their reg property. This was mostly already the case but there were some nodes that didn't follow it so fix it now for consistency.
Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 394 +++++++++++++------------- 1 file changed, 197 insertions(+), 197 deletions(-)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +197 -197
@@ -471,50 +471,6 @@ ipcc: mailbox@408000 { #mbox-cells = <2>; }; - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - iommus = <&apps_smmu 0x443 0x0>; - status = "disabled"; - - uart10: serial@a8c000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x00a8c000 0x0 0x4000>; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - interconnect-names = "qup-core", "qup-config"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 - &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_QUP_1 0>; - power-domains = <&rpmhpd SA8775P_CX>; - operating-points-v2 = <&qup_opp_table_100mhz>; - status = "disabled"; - }; - - uart12: serial@a94000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x00a94000 0x0 0x4000>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - power-domains = <&rpmhpd SA8775P_CX>; - status = "disabled"; - }; - }; - qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -585,173 +541,56 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, }; }; - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x20000>; - }; - - memtimer: timer@17c20000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - ranges = <0x0 0x0 0x0 0x20000000>; - #address-cells = <1>; - #size-cells = <1>; - - frame@17c21000 { - reg = <0x17c21000 0x1000>, - <0x17c22000 0x1000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - frame-number = <0>; - }; - - frame@17c23000 { - reg = <0x17c23000 0x1000>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - frame-number = <1>; - status = "disabled"; - }; - - frame@17c25000 { - reg = <0x17c25000 0x1000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - frame-number = <2>; - status = "disabled"; - }; - - frame@17c27000 { - reg = <0x17c27000 0x1000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - frame-number = <3>; - status = "disabled"; - }; - - frame@17c29000 { - reg = <0x17c29000 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - frame-number = <4>; - status = "disabled"; - }; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x443 0x0>; + status = "disabled"; - frame@17c2b000 { - reg = <0x17c2b000 0x1000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - frame-number = <5>; + uart10: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; - frame@17c2d000 { - reg = <0x17c2d000 0x1000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - frame-number = <6>; + uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; }; - apps_rsc: rsc@18200000 { - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = <ACTIVE_TCS 2>, - <SLEEP_TCS 3>, - <WAKE_TCS 3>, - <CONTROL_TCS 0>; - label = "apps_rsc"; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sa8775p-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board_clk>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sa8775p-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp-0 { - opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; - }; - - rpmhpd_opp_min_svs: opp-1 { - opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; - }; - - rpmhpd_opp_low_svs: opp2 { - opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; - }; - - rpmhpd_opp_svs: opp3 { - opp-level = <RPMH_REGULATOR_LEVEL_SVS>; - }; - - rpmhpd_opp_svs_l1: opp-4 { - opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; - }; - - rpmhpd_opp_nom: opp-5 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM>; - }; - - rpmhpd_opp_nom_l1: opp-6 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; - }; - - rpmhpd_opp_nom_l2: opp-7 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; - }; - - rpmhpd_opp_turbo: opp-8 { - opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; - }; - - rpmhpd_opp_turbo_l1: opp-9 { - opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; - }; - }; - }; - }; - tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; #hwlock-cells = <1>; }; - cpufreq_hw: cpufreq@18591000 { - compatible = "qcom,sa8775p-cpufreq-epss", - "qcom,cpufreq-epss"; - reg = <0x0 0x18591000 0x0 0x1000>, - <0x0 0x18593000 0x0 0x1000>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0x0f000000 0x0 0x1000000>;
@@ -900,6 +739,167 @@ apps_smmu: iommu@15000000 { <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + memtimer: timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17c21000 { + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <0>; + }; + + frame@17c23000 { + reg = <0x17c23000 0x1000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <1>; + status = "disabled"; + }; + + frame@17c25000 { + reg = <0x17c25000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <2>; + status = "disabled"; + }; + + frame@17c27000 { + reg = <0x17c27000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <3>; + status = "disabled"; + }; + + frame@17c29000 { + reg = <0x17c29000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <4>; + status = "disabled"; + }; + + frame@17c2b000 { + reg = <0x17c2b000 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <5>; + status = "disabled"; + }; + + frame@17c2d000 { + reg = <0x17c2d000 0x1000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <6>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, + <SLEEP_TCS 3>, + <WAKE_TCS 3>, + <CONTROL_TCS 0>; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sa8775p-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sa8775p-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sa8775p-cpufreq-epss", + "qcom,cpufreq-epss"; + reg = <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; arch_timer: timer {
Signature · 1 line
2.37.2
PATCH v3 3/18 dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add a compatible for the Power Domain Controller on SA8775p platforms. Increase the number of PDC pin mappings.
Signed-off-by Bartosz Golaszewski <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Marc Zyngier <[email protected]>
--- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +2 -1
@@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,sa8775p-pdc - qcom,sc7180-pdc - qcom,sc7280-pdc - qcom,sc8280xp-pdc
@@ -53,7 +54,7 @@ properties: qcom,pdc-ranges: $ref: /schemas/types.yaml#/definitions/uint32-matrix minItems: 1 - maxItems: 32 # no hard limit + maxItems: 38 # no hard limit items: items: - description: starting PDC port
Signature · 1 line
2.37.2
Re: [PATCH v3 03/18] dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
Quoted 6 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add a compatible for the Power Domain Controller on SA8775p platforms. Increase the number of PDC pin mappings.
Signed-off-by Bartosz Golaszewski <[email protected]>
Best regards,
Krzysztof
Re: [PATCH v3 03/18] dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
In reply to Bartosz GolaszewskiQuoted 35 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add a compatible for the Power Domain Controller on SA8775p platforms. Increase the number of PDC pin mappings.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Marc Zyngier <[email protected]>--- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +2
-2@@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,sa8775p-pdc - qcom,sc7180-pdc - qcom,sc7280-pdc - qcom,sc8280xp-pdc@@ -53,7 +54,7 @@ properties: qcom,pdc-ranges: $ref: /schemas/types.yaml#/definitions/uint32-matrix minItems: 1 - maxItems: 32 # no hard limit + maxItems: 38 # no hard limit items: items: - description: starting PDC port --
Quoted 2 lines
2.37.2
Bjorn,
Will you pick up the dt-bindings patches from this series as well or should they go through Rob's tree?
Bart
Re: [PATCH v3 03/18] dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
Quoted 42 lines · Bartosz Golaszewski
Quoted 35 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add a compatible for the Power Domain Controller on SA8775p platforms. Increase the number of PDC pin mappings.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Marc Zyngier <[email protected]>--- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +2
-2@@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,sa8775p-pdc - qcom,sc7180-pdc - qcom,sc7280-pdc - qcom,sc8280xp-pdc@@ -53,7 +54,7 @@ properties: qcom,pdc-ranges: $ref: /schemas/types.yaml#/definitions/uint32-matrix minItems: 1 - maxItems: 32 # no hard limit + maxItems: 38 # no hard limit items: items: - description: starting PDC port --Quoted 2 lines
2.37.2
Bjorn,
Quoted 4 lines
Will you pick up the dt-bindings patches from this series as well or should they go through Rob's tree?
Bart
Gentle ping as this one's still not in next.
Bart
Re: [PATCH v3 03/18] dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
Quoted 26 lines · Bartosz Golaszewski
Quoted 25 lines · Bartosz Golaszewski
Quoted 23 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add a compatible for the Power Domain Controller on SA8775p platforms. Increase the number of PDC pin mappings.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Marc Zyngier <[email protected]>--- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +1
-0@@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,sa8775p-pdc - qcom,sc7180-pdc
Quoted 8 lines
Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml properties: · line 57
Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +1
-1- qcom,sc7280-pdc - qcom,sc8280xp-pdc@@ -53,7 +54,7 @@ properties: qcom,pdc-ranges: $ref: /schemas/types.yaml#/definitions/uint32-matrix minItems: 1 - maxItems: 32 # no hard limit + maxItems: 38 # no hard limit
I don't think the limit is correct. I still see warnings with this patch. We already have 57 elements, so limit should be I guess 128 or something.
Best regards,
Krzysztof
Re: [PATCH v3 03/18] dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
Quoted 32 lines · Krzysztof Kozlowski
Quoted 30 lines · Bartosz Golaszewski
Quoted 29 lines · Bartosz Golaszewski
Quoted 27 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add a compatible for the Power Domain Controller on SA8775p platforms. Increase the number of PDC pin mappings.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Marc Zyngier <[email protected]>--- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +1
-0@@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,sa8775p-pdc - qcom,sc7180-pdc - qcom,sc7280-pdc - qcom,sc8280xp-pdc@@ -53,7 +54,7 @@ properties: qcom,pdc-ranges:
Quoted 9 lines
Quoted 4 lines
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml properties: · line 57
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +1
-1$ref: /schemas/types.yaml#/definitions/uint32-matrix minItems: 1 - maxItems: 32 # no hard limit + maxItems: 38 # no hard limitI don't think the limit is correct. I still see warnings with this patch. We already have 57 elements, so limit should be I guess 128 or something.
You mean for other platforms? This limit applies to sa8775p as the goal of the patch is to add its own PDC compatible. If other platforms have more interrupts then we need to fix it first with a separate commit IMO. I'll send out two patches for that.
Brt
Re: [PATCH v3 03/18] dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
Quoted 44 lines · Bartosz Golaszewski
Quoted 32 lines · Krzysztof Kozlowski
Quoted 30 lines · Bartosz Golaszewski
Quoted 29 lines · Bartosz Golaszewski
Quoted 27 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add a compatible for the Power Domain Controller on SA8775p platforms. Increase the number of PDC pin mappings.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Marc Zyngier <[email protected]>--- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +1
-0@@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,sa8775p-pdc - qcom,sc7180-pdc - qcom,sc7280-pdc - qcom,sc8280xp-pdc@@ -53,7 +54,7 @@ properties: qcom,pdc-ranges:Quoted 9 lines
Quoted 4 lines
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml properties: · line 57
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +1
-1$ref: /schemas/types.yaml#/definitions/uint32-matrix minItems: 1 - maxItems: 32 # no hard limit + maxItems: 38 # no hard limitI don't think the limit is correct. I still see warnings with this patch. We already have 57 elements, so limit should be I guess 128 or something.
Quoted 1 line
You mean for other platforms? This limit applies to sa8775p as the
I see errors on sa8775p.
Quoted 3 lines
goal of the patch is to add its own PDC compatible. If other platforms have more interrupts then we need to fix it first with a separate commit IMO. I'll send out two patches for that.
Best regards,
Krzysztof
Re: [PATCH v3 03/18] dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
Quoted 45 lines · Krzysztof Kozlowski
Quoted 44 lines · Bartosz Golaszewski
Quoted 41 lines · Krzysztof Kozlowski
Quoted 26 lines · Bartosz Golaszewski
Quoted 25 lines · Bartosz Golaszewski
Quoted 23 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add a compatible for the Power Domain Controller on SA8775p platforms. Increase the number of PDC pin mappings.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Marc Zyngier <[email protected]>--- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +1
-0@@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,sa8775p-pdc - qcom,sc7180-pdcQuoted 8 lines
Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml properties: · line 57
Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +1
-1- qcom,sc7280-pdc - qcom,sc8280xp-pdc@@ -53,7 +54,7 @@ properties: qcom,pdc-ranges: $ref: /schemas/types.yaml#/definitions/uint32-matrix minItems: 1 - maxItems: 32 # no hard limit + maxItems: 38 # no hard limitI don't think the limit is correct. I still see warnings with this patch. We already have 57 elements, so limit should be I guess 128 or something.
Quoted 3 lines
Quoted 1 line
You mean for other platforms? This limit applies to sa8775p as the
I see errors on sa8775p.
OK, so as you pointed out it's about other platform - sa8540p-ride. Anyway you update now this line to bump the limit, so bump it to something high instead of changing it in two patches.
Best regards,
Krzysztof
PATCH v3 4/18 arm64: dts: qcom: sa8775p: add the pdc node
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add the Power Domain Controller node for SA8775p.
Signed-off-by Bartosz Golaszewski <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 47 +++++++++++++++++++++++++++ 1 file changed, 47 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +47 -0
@@ -591,6 +591,53 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sa8775p-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x17c000f0 0x0 0x64>; + qcom,pdc-ranges = <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 2>, + <70 520 1>, + <73 523 1>, + <118 568 6>, + <124 609 3>, + <159 638 1>, + <160 720 3>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 2>, + <216 646 5>, + <221 390 5>, + <226 700 2>, + <228 440 1>, + <229 663 1>, + <230 524 2>, + <232 612 3>, + <235 723 5>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0x0f000000 0x0 0x1000000>;
Signature · 1 line
2.37.2
Re: [PATCH v3 04/18] arm64: dts: qcom: sa8775p: add the pdc node
Quoted 6 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add the Power Domain Controller node for SA8775p.
Signed-off-by Bartosz Golaszewski <[email protected]>---
Reviewed-by Konrad Dybcio <[email protected]>
Konrad
Quoted 61 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 47 +++++++++++++++++++++++++++ 1 file changed, 47 insertions(+)arch/arm64/boot/dts/qcom/sa8775p.dtsi +47
-0@@ -591,6 +591,53 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sa8775p-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x17c000f0 0x0 0x64>; + qcom,pdc-ranges = <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 2>, + <70 520 1>, + <73 523 1>, + <118 568 6>, + <124 609 3>, + <159 638 1>, + <160 720 3>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 2>, + <216 646 5>, + <221 390 5>, + <226 700 2>, + <228 440 1>, + <229 663 1>, + <230 524 2>, + <232 612 3>, + <235 723 5>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0x0f000000 0x0 0x1000000>;
PATCH v3 5/18 arm64: dts: qcom: sa8775p: add the spmi node
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add the SPMI PMIC Arbiter node for SA8775p platforms.
Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +22 -0
@@ -638,6 +638,28 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + qcom,channel = <0>; + qcom,ee = <0>; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0x0f000000 0x0 0x1000000>;
Signature · 1 line
2.37.2
PATCH v3 6/18 dt-bindings: mfd: qcom,spmi-pmic: add compatible for pmm8654au
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
PMM8654au is the SPMI PMIC variant used on sa8775p-ride. Add a compatible for it.
Signed-off-by Bartosz Golaszewski <[email protected]>
Cc Lee Jones <[email protected]>
Acked-by Rob Herring <[email protected]>
--- Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +1 -0
@@ -79,6 +79,7 @@ properties: - qcom,pmk8350 - qcom,pmk8550 - qcom,pmm8155au + - qcom,pmm8654au - qcom,pmp8074 - qcom,pmr735a - qcom,pmr735b
Signature · 1 line
2.37.2
Lee Jones
maintainerRe: [PATCH v3 06/18] dt-bindings: mfd: qcom,spmi-pmic: add compatible for pmm8654au
Quoted 9 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
PMM8654au is the SPMI PMIC variant used on sa8775p-ride. Add a compatible for it.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Lee Jones <[email protected]>Acked-by Rob Herring <[email protected]>---
Change-log?
Quoted 8 lines
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +0
-0
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml properties: · line 85
Quoted 7 lines
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +1
-0@@ -79,6 +79,7 @@ properties: - qcom,pmk8350 - qcom,pmk8550 - qcom,pmm8155au + - qcom,pmm8654au - qcom,pmp8074 - qcom,pmr735a - qcom,pmr735b
I believe this is already applied, right?
Not sure why I have 3 copies of seemingly the same patch in my inbox.
--
Lee Jones [李琼斯]
Re: [PATCH v3 06/18] dt-bindings: mfd: qcom,spmi-pmic: add compatible for pmm8654au
Quoted 33 lines · Lee Jones
Quoted 9 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
PMM8654au is the SPMI PMIC variant used on sa8775p-ride. Add a compatible for it.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Lee Jones <[email protected]>Acked-by Rob Herring <[email protected]>---
Change-log?
Quoted 8 lines
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +0
-0Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml properties: · line 85
Quoted 7 lines
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +1
-0@@ -79,6 +79,7 @@ properties: - qcom,pmk8350 - qcom,pmk8550 - qcom,pmm8155au + - qcom,pmm8654au - qcom,pmp8074 - qcom,pmr735a - qcom,pmr735bI believe this is already applied, right?
Quoted 2 lines
Not sure why I have 3 copies of seemingly the same patch in my inbox.
I've sent out three iterations of the series containing it. This one didn't change. As the rest of 18 patches don't concern your subsystem, I decided to only Cc you on this one. Let me know if you prefer to receive the entire series even if only a single patch needs your attention. The reaction to such dumps varies from maintainer to maintainer so I chose the safe approach. :)
Bart
Quoted 2 lines
--
Lee Jones [李琼斯]
Lee Jones
maintainerRe: [PATCH v3 06/18] dt-bindings: mfd: qcom,spmi-pmic: add compatible for pmm8654au
Quoted 37 lines · Bartosz Golaszewski
Quoted 33 lines · Lee Jones
Quoted 9 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
PMM8654au is the SPMI PMIC variant used on sa8775p-ride. Add a compatible for it.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Lee Jones <[email protected]>Acked-by Rob Herring <[email protected]>---
Change-log?
Quoted 8 lines
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +0
-0Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml properties: · line 85
Quoted 7 lines
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +1
-0@@ -79,6 +79,7 @@ properties: - qcom,pmk8350 - qcom,pmk8550 - qcom,pmm8155au + - qcom,pmm8654au - qcom,pmp8074 - qcom,pmr735a - qcom,pmr735bI believe this is already applied, right?
Quoted 2 lines
Not sure why I have 3 copies of seemingly the same patch in my inbox.
Quoted 6 lines
I've sent out three iterations of the series containing it. This one didn't change. As the rest of 18 patches don't concern your subsystem, I decided to only Cc you on this one. Let me know if you prefer to receive the entire series even if only a single patch needs your attention. The reaction to such dumps varies from maintainer to maintainer so I chose the safe approach. :)
There is no simple answer to that question.
Not Cc:ing me on this whole set appears to be the correct decision.
--
Lee Jones [李琼斯]
PATCH v3 7/18 arm64: dts: qcom: sa8775p: add support for the on-board PMICs
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced to the SoC via SPMI. Enable the PMICs for sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 37 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 1 + 2 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi new file +37 -0
@@ -0,0 +1,37 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + pmm8654au_0: pmic@0 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmm8654au_1: pmic@2 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmm8654au_2: pmic@4 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmm8654au_3: pmic@6 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +};
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +1 -0
@@ -6,6 +6,7 @@ /dts-v1/; #include "sa8775p.dtsi" +#include "sa8775p-pmics.dtsi" / { model = "Qualcomm SA8775P Ride";
Signature · 1 line
2.37.2
PATCH v3 8/18 arm64: dts: qcom: sa8775p: add the Power On device node
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add the PON node to PMIC #0 for sa8775p platforms.
Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +8 -0
@@ -12,6 +12,14 @@ pmm8654au_0: pmic@0 { reg = <0x0 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_0_pon: pon@1200 { + compatible = "qcom,pmk8350-pon"; + reg = <0x1200>, <0x800>; + reg-names = "hlos", "pbs"; + mode-recovery = <0x1>; + mode-bootloader = <0x2>; + }; }; pmm8654au_1: pmic@2 {
Signature · 1 line
2.37.2
PATCH v3 9/18 arm64: dts: qcom: sa8775p: pmic: add the power key
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add the power key node under the PON node for PMIC #0 on sa8775p.
Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +7 -0
@@ -19,6 +19,13 @@ pmm8654au_0_pon: pon@1200 { reg-names = "hlos", "pbs"; mode-recovery = <0x1>; mode-bootloader = <0x2>; + + pmm8654au_0_pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts-extended = <&spmi_bus 0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_POWER>; + debounce = <15625>; + }; }; };
Signature · 1 line
2.37.2
PATCH v3 10/18 arm64: dts: qcom: sa8775p: pmic: add support for the pmm8654 RESIN input
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add the RESIN input for sa8775p platforms' PMIC.
Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +7 -0
@@ -26,6 +26,13 @@ pmm8654au_0_pon_pwrkey: pwrkey { linux,code = <KEY_POWER>; debounce = <15625>; }; + + pmm8654au_0_pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts-extended = <&spmi_bus 0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + status = "disabled"; + }; }; };
Signature · 1 line
2.37.2
PATCH v3 11/18 arm64: dts: qcom: sa8775p: pmic: add thermal zones
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add the thermal zones and associated alarm nodes for the PMICs that have them hooked up on sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 112 ++++++++++++++++++++ 1 file changed, 112 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +112 -0
@@ -6,6 +6,90 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/spmi/spmi.h> +/ { + thermal-zones { + pmm8654au_0_thermal: pm8775-0-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_0_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_1_thermal: pm8775-1-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_1_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_2_thermal: pm8775-2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_2_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_3_thermal: pm8775-3-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_3_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmm8654au_0: pmic@0 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
@@ -13,6 +97,13 @@ pmm8654au_0: pmic@0 { #address-cells = <1>; #size-cells = <0>; + pmm8654au_0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pmm8654au_0_pon: pon@1200 { compatible = "qcom,pmk8350-pon"; reg = <0x1200>, <0x800>;
@@ -41,6 +132,13 @@ pmm8654au_1: pmic@2 { reg = <0x2 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; pmm8654au_2: pmic@4 {
@@ -48,6 +146,13 @@ pmm8654au_2: pmic@4 { reg = <0x4 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_2_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; pmm8654au_3: pmic@6 {
@@ -55,5 +160,12 @@ pmm8654au_3: pmic@6 { reg = <0x6 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_3_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; };
Signature · 1 line
2.37.2
Re: [PATCH v3 11/18] arm64: dts: qcom: sa8775p: pmic: add thermal zones
Quoted 7 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add the thermal zones and associated alarm nodes for the PMICs that have them hooked up on sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>---
Reviewed-by Konrad Dybcio <[email protected]>
Konrad
Quoted 153 lines
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 112 ++++++++++++++++++++ 1 file changed, 112 insertions(+)arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +112
-0@@ -6,6 +6,90 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/spmi/spmi.h> +/ { + thermal-zones { + pmm8654au_0_thermal: pm8775-0-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_0_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_1_thermal: pm8775-1-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_1_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_2_thermal: pm8775-2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_2_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_3_thermal: pm8775-3-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_3_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmm8654au_0: pmic@0 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic";@@ -13,6 +97,13 @@ pmm8654au_0: pmic@0 { #address-cells = <1>; #size-cells = <0>; + pmm8654au_0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pmm8654au_0_pon: pon@1200 { compatible = "qcom,pmk8350-pon"; reg = <0x1200>, <0x800>;@@ -41,6 +132,13 @@ pmm8654au_1: pmic@2 { reg = <0x2 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; pmm8654au_2: pmic@4 {@@ -48,6 +146,13 @@ pmm8654au_2: pmic@4 { reg = <0x4 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_2_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; pmm8654au_3: pmic@6 {@@ -55,5 +160,12 @@ pmm8654au_3: pmic@6 { reg = <0x6 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_3_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; };
PATCH v3 12/18 dt-bindings: pinctrl: qcom,pmic-gpio: add compatible for pmm8654au-gpio
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add a new compatible for the GPIO controller on the pm8654au PMIC. It has 12 pins with no holes.
Signed-off-by Bartosz Golaszewski <[email protected]>
Cc Linus Walleij <[email protected]>
Acked-by Rob Herring <[email protected]>
--- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +2 -0
@@ -58,6 +58,7 @@ properties: - qcom,pmk8350-gpio - qcom,pmk8550-gpio - qcom,pmm8155au-gpio + - qcom,pmm8654au-gpio - qcom,pmp8074-gpio - qcom,pmr735a-gpio - qcom,pmr735b-gpio
@@ -439,6 +440,7 @@ $defs: - gpio1-gpio4 for pmk8350 - gpio1-gpio6 for pmk8550 - gpio1-gpio10 for pmm8155au + - gpio1-gpio12 for pmm8654au - gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12) - gpio1-gpio4 for pmr735a - gpio1-gpio4 for pmr735b
Signature · 1 line
2.37.2
Re: [PATCH v3 12/18] dt-bindings: pinctrl: qcom,pmic-gpio: add compatible for pmm8654au-gpio
Quoted 8 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add a new compatible for the GPIO controller on the pm8654au PMIC. It has 12 pins with no holes.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Linus Walleij <[email protected]>Acked-by Rob Herring <[email protected]>
Acked-by Linus Walleij <[email protected]>
Counting on Bjorn to pick this up.
Yours,
Linus Walleij
Re: [PATCH v3 12/18] dt-bindings: pinctrl: qcom,pmic-gpio: add compatible for pmm8654au-gpio
Quoted 12 lines · Linus Walleij
Quoted 8 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add a new compatible for the GPIO controller on the pm8654au PMIC. It has 12 pins with no holes.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Linus Walleij <[email protected]>Acked-by Rob Herring <[email protected]>
Quoted 6 lines
Acked-by Linus Walleij <[email protected]>Counting on Bjorn to pick this up.
Yours,
Linus Walleij
Linus,
Bjorn picked up the arm64 patches but these two were skipped. Can you take it through the pinctrl tree?
Bart
Re: [PATCH v3 12/18] dt-bindings: pinctrl: qcom,pmic-gpio: add compatible for pmm8654au-gpio
Quoted 16 lines · Bartosz Golaszewski
Quoted 15 lines · Linus Walleij
Quoted 8 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add a new compatible for the GPIO controller on the pm8654au PMIC. It has 12 pins with no holes.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Linus Walleij <[email protected]>Acked-by Rob Herring <[email protected]>Acked-by Linus Walleij <[email protected]>Counting on Bjorn to pick this up.
Quoted 7 lines
Quoted 2 lines
Yours,
Linus WalleijLinus,
Bjorn picked up the arm64 patches but these two were skipped. Can you take it through the pinctrl tree?
OK patches 12 and 13 applied to the pinctrl tree!
Yours,
Linus Walleij
PATCH v3 13/18 pinctrl: qcom: spmi-gpio: add support for pmm8654au-gpio
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add support for the GPIO controller present on the pmm8654au PMIC.
Signed-off-by Bartosz Golaszewski <[email protected]>
Cc Linus Walleij <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
--- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 1 file changed, 1 insertion(+)
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +1 -0
@@ -1238,6 +1238,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 }, { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pmm8654au-gpio", .data = (void *) 12 }, /* pmp8074 has 12 GPIOs with holes on 1 and 12 */ { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 }, { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
Signature · 1 line
2.37.2
Re: [PATCH v3 13/18] pinctrl: qcom: spmi-gpio: add support for pmm8654au-gpio
Quoted 7 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add support for the GPIO controller present on the pmm8654au PMIC.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Linus Walleij <[email protected]>Reviewed-by Konrad Dybcio <[email protected]>
Acked-by Linus Walleij <[email protected]>
Yours,
Linus Walleij
PATCH v3 14/18 arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add GPIO controller nodes to PMICs that have the GPIO hooked up on sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +40 -0
@@ -125,6 +125,16 @@ pmm8654au_0_pon_resin: resin { status = "disabled"; }; }; + + pmm8654au_0_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_0_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_1: pmic@2 {
@@ -139,6 +149,16 @@ pmm8654au_1_temp_alarm: temp-alarm@a00 { interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_1_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_2_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_2: pmic@4 {
@@ -153,6 +173,16 @@ pmm8654au_2_temp_alarm: temp-alarm@a00 { interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_2_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_2_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_3: pmic@6 {
@@ -167,5 +197,15 @@ pmm8654au_3_temp_alarm: temp-alarm@a00 { interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_3_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_3_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; };
Signature · 1 line
2.37.2
Re: [PATCH v3 14/18] arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes
Quoted 7 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add GPIO controller nodes to PMICs that have the GPIO hooked up on sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>---
Reviewed-by Konrad Dybcio <[email protected]>
Konrad
Quoted 74 lines
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+)arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +40
-0@@ -125,6 +125,16 @@ pmm8654au_0_pon_resin: resin { status = "disabled"; }; }; + + pmm8654au_0_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_0_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_1: pmic@2 {@@ -139,6 +149,16 @@ pmm8654au_1_temp_alarm: temp-alarm@a00 { interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_1_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_2_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_2: pmic@4 {@@ -153,6 +173,16 @@ pmm8654au_2_temp_alarm: temp-alarm@a00 { interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_2_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_2_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_3: pmic@6 {@@ -167,5 +197,15 @@ pmm8654au_3_temp_alarm: temp-alarm@a00 { interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_3_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_3_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; };
PATCH v3 15/18 arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Set line names for GPIO lines exposed by PMICs on sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 51 +++++++++++++++++++++++ 1 file changed, 51 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +51 -0
@@ -32,6 +32,57 @@ &i2c18 { status = "okay"; }; +&pmm8654au_0_gpios { + gpio-line-names = "DS_EN", + "POFF_COMPLETE", + "UFS0_VER_ID", + "FAST_POFF", + "DBU1_PON_DONE", + "AOSS_SLEEP", + "CAM_DES0_EN", + "CAM_DES1_EN", + "CAM_DES2_EN", + "CAM_DES3_EN", + "UEFI", + "ANALOG_PON_OPT"; +}; + +&pmm8654au_1_gpios { + gpio-line-names = "PMIC_C_ID0", + "PMIC_C_ID1", + "UFS1_VER_ID", + "IPA_PWR", + "", + "WLAN_DBU4_EN", + "WLAN_EN", + "BT_EN", + "USB2_PWR_EN", + "USB2_FAULT"; +}; + +&pmm8654au_2_gpios { + gpio-line-names = "PMIC_E_ID0", + "PMIC_E_ID1", + "USB0_PWR_EN", + "USB0_FAULT", + "SENSOR_IRQ_1", + "SENSOR_IRQ_2", + "SENSOR_RST", + "SGMIIO0_RST", + "SGMIIO1_RST", + "USB1_PWR_ENABLE", + "USB1_FAULT", + "VMON_SPX8"; +}; + +&pmm8654au_3_gpios { + gpio-line-names = "PMIC_G_ID0", + "PMIC_G_ID1", + "GNSS_RST", + "GNSS_EN", + "GNSS_BOOT_MODE"; +}; + &qupv3_id_1 { status = "okay"; };
Signature · 1 line
2.37.2
Re: [PATCH v3 15/18] arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs
Quoted 6 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Set line names for GPIO lines exposed by PMICs on sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>---
Reviewed-by Konrad Dybcio <[email protected]>
Konrad
Quoted 65 lines
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 51 +++++++++++++++++++++++ 1 file changed, 51 insertions(+)arch/arm64/boot/dts/qcom/sa8775p-ride.dts +51
-0@@ -32,6 +32,57 @@ &i2c18 { status = "okay"; }; +&pmm8654au_0_gpios { + gpio-line-names = "DS_EN", + "POFF_COMPLETE", + "UFS0_VER_ID", + "FAST_POFF", + "DBU1_PON_DONE", + "AOSS_SLEEP", + "CAM_DES0_EN", + "CAM_DES1_EN", + "CAM_DES2_EN", + "CAM_DES3_EN", + "UEFI", + "ANALOG_PON_OPT"; +}; + +&pmm8654au_1_gpios { + gpio-line-names = "PMIC_C_ID0", + "PMIC_C_ID1", + "UFS1_VER_ID", + "IPA_PWR", + "", + "WLAN_DBU4_EN", + "WLAN_EN", + "BT_EN", + "USB2_PWR_EN", + "USB2_FAULT"; +}; + +&pmm8654au_2_gpios { + gpio-line-names = "PMIC_E_ID0", + "PMIC_E_ID1", + "USB0_PWR_EN", + "USB0_FAULT", + "SENSOR_IRQ_1", + "SENSOR_IRQ_2", + "SENSOR_RST", + "SGMIIO0_RST", + "SGMIIO1_RST", + "USB1_PWR_ENABLE", + "USB1_FAULT", + "VMON_SPX8"; +}; + +&pmm8654au_3_gpios { + gpio-line-names = "PMIC_G_ID0", + "PMIC_G_ID1", + "GNSS_RST", + "GNSS_EN", + "GNSS_BOOT_MODE"; +}; + &qupv3_id_1 { status = "okay"; };
PATCH v3 16/18 dt-bindings: regulator: qcom,rpmh: add compatible for pmm8654au RPMH
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add the compatible for the pmm8654au RPMH regulators present on the sa8775p-ride development board.
Signed-off-by Bartosz Golaszewski <[email protected]>
Cc Mark Brown <[email protected]>
--- .../bindings/regulator/qcom,rpmh-regulator.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml +14 -0
@@ -78,6 +78,7 @@ properties: - qcom,pmg1110-rpmh-regulators - qcom,pmi8998-rpmh-regulators - qcom,pmm8155au-rpmh-regulators + - qcom,pmm8654au-rpmh-regulators - qcom,pmr735a-rpmh-regulators - qcom,pmx55-rpmh-regulators - qcom,pmx65-rpmh-regulators
@@ -244,6 +245,19 @@ allOf: patternProperties: "^vdd-s([1-9]|10)-supply$": true + - if: + properties: + compatible: + enum: + - qcom,pmm8654au-rpmh-regulators + then: + properties: + vdd-l2-l3-supply: true + vdd-l6-l7-supply: true + vdd-l8-l9-supply: true + patternProperties: + "^vdd-s[1-9]-supply$": true + - if: properties: compatible:
Signature · 1 line
2.37.2
Re: [PATCH v3 16/18] dt-bindings: regulator: qcom,rpmh: add compatible for pmm8654au RPMH
Quoted 27 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add the compatible for the pmm8654au RPMH regulators present on the sa8775p-ride development board.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Mark Brown <[email protected]>--- .../bindings/regulator/qcom,rpmh-regulator.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+)Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml +1
-0@@ -78,6 +78,7 @@ properties: - qcom,pmg1110-rpmh-regulators - qcom,pmi8998-rpmh-regulators - qcom,pmm8155au-rpmh-regulators + - qcom,pmm8654au-rpmh-regulators - qcom,pmr735a-rpmh-regulators - qcom,pmx55-rpmh-regulators - qcom,pmx65-rpmh-regulators@@ -244,6 +245,19 @@ allOf: patternProperties: "^vdd-s([1-9]|10)-supply$": true
Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml allOf: · line 257
Quoted 10 lines
Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml +10
-0+ - if: + properties: + compatible: + enum: + - qcom,pmm8654au-rpmh-regulators + then: + properties: + vdd-l2-l3-supply: true + vdd-l6-l7-supply: true + vdd-l8-l9-supply: true
What about l1, l4 and l5 supplies?
Best regards,
Krzysztof
PATCH v3 17/18 regulator: qcom-rpmh: add support for pmm8654au regulators
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add the RPMH regulators exposed by the PMM8654au PMIC and its variants.
Signed-off-by Bartosz Golaszewski <[email protected]>
Cc Mark Brown <[email protected]>
--- drivers/regulator/qcom-rpmh-regulator.c | 55 +++++++++++++++++++++++++ 1 file changed, 55 insertions(+)
drivers/regulator/qcom-rpmh-regulator.c +55 -0
@@ -694,6 +694,16 @@ static const struct rpmh_vreg_hw_data pmic5_pldo_lv = { .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, }; +static const struct rpmh_vreg_hw_data pmic5_pldo515_mv = { + .regulator_type =VRM , + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range =REGULATOR_LINEAR_RANGE (1800000 ,0 ,187 ,8000 ), + .n_voltages =188 , + .hpm_min_load_uA =10000 , + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; +static const struct rpmh_vreg_hw_data pmic5_nldo = { .regulator_type =VRM , .ops = &rpmh_regulator_vrm_drms_ops,
@@ -704,6 +714,16 @@ static const struct rpmh_vreg_hw_data pmic5_nldo = { .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, }; +static const struct rpmh_vreg_hw_data pmic5_nldo515 = { + .regulator_type =VRM , + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range =REGULATOR_LINEAR_RANGE (320000 ,0 ,210 ,8000 ), + .n_voltages =211 , + .hpm_min_load_uA =30000 , + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; +static const struct rpmh_vreg_hw_data pmic5_hfsmps510 = { .regulator_type =VRM , .ops = &rpmh_regulator_vrm_ops,
@@ -749,6 +769,15 @@ static const struct rpmh_vreg_hw_data pmic5_ftsmps525_mv = { .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, }; +static const struct rpmh_vreg_hw_data pmic5_ftsmps527 = { + .regulator_type =VRM , + .ops = &rpmh_regulator_vrm_ops, + .voltage_range =REGULATOR_LINEAR_RANGE (320000 ,0 ,215 ,8000 ), + .n_voltages =215 , + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; +static const struct rpmh_vreg_hw_data pmic5_hfsmps515 = { .regulator_type =VRM , .ops = &rpmh_regulator_vrm_ops,
@@ -937,6 +966,28 @@ static const struct rpmh_vreg_init_data pmm8155au_vreg_data[] = { {} }; +static const struct rpmh_vreg_init_data pmm8654au_vreg_data[] = { +RPMH_VREG ("smps1" ,"smp%s1" , &pmic5_ftsmps527,"vdd-s1" ), +RPMH_VREG ("smps2" ,"smp%s2" , &pmic5_ftsmps527,"vdd-s2" ), +RPMH_VREG ("smps3" ,"smp%s3" , &pmic5_ftsmps527,"vdd-s3" ), +RPMH_VREG ("smps4" ,"smp%s4" , &pmic5_ftsmps527,"vdd-s4" ), +RPMH_VREG ("smps5" ,"smp%s5" , &pmic5_ftsmps527,"vdd-s5" ), +RPMH_VREG ("smps6" ,"smp%s6" , &pmic5_ftsmps527,"vdd-s6" ), +RPMH_VREG ("smps7" ,"smp%s7" , &pmic5_ftsmps527,"vdd-s7" ), +RPMH_VREG ("smps8" ,"smp%s8" , &pmic5_ftsmps527,"vdd-s8" ), +RPMH_VREG ("smps9" ,"smp%s9" , &pmic5_ftsmps527,"vdd-s9" ), +RPMH_VREG ("ldo1" ,"ldo%s1" , &pmic5_nldo515,"vdd-s9" ), +RPMH_VREG ("ldo2" ,"ldo%s2" , &pmic5_nldo515,"vdd-l2-l3" ), +RPMH_VREG ("ldo3" ,"ldo%s3" , &pmic5_nldo515,"vdd-l2-l3" ), +RPMH_VREG ("ldo4" ,"ldo%s4" , &pmic5_nldo515,"vdd-s9" ), +RPMH_VREG ("ldo5" ,"ldo%s5" , &pmic5_nldo515,"vdd-s9" ), +RPMH_VREG ("ldo6" ,"ldo%s6" , &pmic5_nldo515,"vdd-l6-l7" ), +RPMH_VREG ("ldo7" ,"ldo%s7" , &pmic5_nldo515,"vdd-l6-l7" ), +RPMH_VREG ("ldo8" ,"ldo%s8" , &pmic5_pldo515_mv,"vdd-l8-l9" ), +RPMH_VREG ("ldo9" ,"ldo%s9" , &pmic5_pldo,"vdd-l8-l9" ), + {} +}; +static const struct rpmh_vreg_init_data pm8350_vreg_data[] = {RPMH_VREG ("smps1" ,"smp%s1" , &pmic5_ftsmps510,"vdd-s1" ),RPMH_VREG ("smps2" ,"smp%s2" , &pmic5_ftsmps510,"vdd-s2" ),
@@ -1431,6 +1482,10 @@ static const struct of_device_id __maybe_unused rpmh_regulator_match_table[] = { .compatible = "qcom,pmm8155au-rpmh-regulators", .data = pmm8155au_vreg_data, }, + { + .compatible = "qcom,pmm8654au-rpmh-regulators", + .data = pmm8654au_vreg_data, + }, { .compatible = "qcom,pmx55-rpmh-regulators", .data = pmx55_vreg_data,
Signature · 1 line
2.37.2
Re: [PATCH v3 17/18] regulator: qcom-rpmh: add support for pmm8654au regulators
Quoted 7 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add the RPMH regulators exposed by the PMM8654au PMIC and its variants.
Signed-off-by Bartosz Golaszewski <[email protected]>Cc Mark Brown <[email protected]>---
I can't check the validity of the regulator types and ranges, but for the overall picture:
Reviewed-by Konrad Dybcio <[email protected]>
Konrad
Quoted 97 lines
drivers/regulator/qcom-rpmh-regulator.c | 55 +++++++++++++++++++++++++ 1 file changed, 55 insertions(+)drivers/regulator/qcom-rpmh-regulator.c +55
-0@@ -694,6 +694,16 @@ static const struct rpmh_vreg_hw_data pmic5_pldo_lv = { .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, }; +static const struct rpmh_vreg_hw_data pmic5_pldo515_mv = { + .regulator_type =VRM , + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range =REGULATOR_LINEAR_RANGE (1800000 ,0 ,187 ,8000 ), + .n_voltages =188 , + .hpm_min_load_uA =10000 , + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; +static const struct rpmh_vreg_hw_data pmic5_nldo = { .regulator_type =VRM , .ops = &rpmh_regulator_vrm_drms_ops,@@ -704,6 +714,16 @@ static const struct rpmh_vreg_hw_data pmic5_nldo = { .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, }; +static const struct rpmh_vreg_hw_data pmic5_nldo515 = { + .regulator_type =VRM , + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range =REGULATOR_LINEAR_RANGE (320000 ,0 ,210 ,8000 ), + .n_voltages =211 , + .hpm_min_load_uA =30000 , + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; +static const struct rpmh_vreg_hw_data pmic5_hfsmps510 = { .regulator_type =VRM , .ops = &rpmh_regulator_vrm_ops,@@ -749,6 +769,15 @@ static const struct rpmh_vreg_hw_data pmic5_ftsmps525_mv = { .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, }; +static const struct rpmh_vreg_hw_data pmic5_ftsmps527 = { + .regulator_type =VRM , + .ops = &rpmh_regulator_vrm_ops, + .voltage_range =REGULATOR_LINEAR_RANGE (320000 ,0 ,215 ,8000 ), + .n_voltages =215 , + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; +static const struct rpmh_vreg_hw_data pmic5_hfsmps515 = { .regulator_type =VRM , .ops = &rpmh_regulator_vrm_ops,@@ -937,6 +966,28 @@ static const struct rpmh_vreg_init_data pmm8155au_vreg_data[] = { {} }; +static const struct rpmh_vreg_init_data pmm8654au_vreg_data[] = { +RPMH_VREG ("smps1" ,"smp%s1" , &pmic5_ftsmps527,"vdd-s1" ), +RPMH_VREG ("smps2" ,"smp%s2" , &pmic5_ftsmps527,"vdd-s2" ), +RPMH_VREG ("smps3" ,"smp%s3" , &pmic5_ftsmps527,"vdd-s3" ), +RPMH_VREG ("smps4" ,"smp%s4" , &pmic5_ftsmps527,"vdd-s4" ), +RPMH_VREG ("smps5" ,"smp%s5" , &pmic5_ftsmps527,"vdd-s5" ), +RPMH_VREG ("smps6" ,"smp%s6" , &pmic5_ftsmps527,"vdd-s6" ), +RPMH_VREG ("smps7" ,"smp%s7" , &pmic5_ftsmps527,"vdd-s7" ), +RPMH_VREG ("smps8" ,"smp%s8" , &pmic5_ftsmps527,"vdd-s8" ), +RPMH_VREG ("smps9" ,"smp%s9" , &pmic5_ftsmps527,"vdd-s9" ), +RPMH_VREG ("ldo1" ,"ldo%s1" , &pmic5_nldo515,"vdd-s9" ), +RPMH_VREG ("ldo2" ,"ldo%s2" , &pmic5_nldo515,"vdd-l2-l3" ), +RPMH_VREG ("ldo3" ,"ldo%s3" , &pmic5_nldo515,"vdd-l2-l3" ), +RPMH_VREG ("ldo4" ,"ldo%s4" , &pmic5_nldo515,"vdd-s9" ), +RPMH_VREG ("ldo5" ,"ldo%s5" , &pmic5_nldo515,"vdd-s9" ), +RPMH_VREG ("ldo6" ,"ldo%s6" , &pmic5_nldo515,"vdd-l6-l7" ), +RPMH_VREG ("ldo7" ,"ldo%s7" , &pmic5_nldo515,"vdd-l6-l7" ), +RPMH_VREG ("ldo8" ,"ldo%s8" , &pmic5_pldo515_mv,"vdd-l8-l9" ), +RPMH_VREG ("ldo9" ,"ldo%s9" , &pmic5_pldo,"vdd-l8-l9" ), + {} +}; +static const struct rpmh_vreg_init_data pm8350_vreg_data[] = {RPMH_VREG ("smps1" ,"smp%s1" , &pmic5_ftsmps510,"vdd-s1" ),RPMH_VREG ("smps2" ,"smp%s2" , &pmic5_ftsmps510,"vdd-s2" ),@@ -1431,6 +1482,10 @@ static const struct of_device_id __maybe_unused rpmh_regulator_match_table[] = { .compatible = "qcom,pmm8155au-rpmh-regulators", .data = pmm8155au_vreg_data, }, + { + .compatible = "qcom,pmm8654au-rpmh-regulators", + .data = pmm8654au_vreg_data, + }, { .compatible = "qcom,pmx55-rpmh-regulators", .data = pmx55_vreg_data,
PATCH v3 18/18 arm64: dts: qcom: sa8775p-ride: add PMIC regulators
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add PMIC regulators for sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 233 ++++++++++++++++++++++ 1 file changed, 233 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +233 -0
@@ -5,6 +5,8 @@ /dts-v1/; +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + #include "sa8775p.dtsi" #include "sa8775p-pmics.dtsi"
@@ -25,6 +27,237 @@ chosen { }; }; +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1816000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1996000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9a: smps9 { + regulator-name = "vreg_s9a"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + /* + * FIXME: This should have regulator-allow-set-load but + * we're getting the over-current fault from the PMIC + * when switching to LPM. + */ + }; + + vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_s4e: smps4 { + regulator-name = "vreg_s4e"; + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1520000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s7e: smps7 { + regulator-name = "vreg_s7e"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9e: smps9 { + regulator-name = "vreg_s9e"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6e: ldo6 { + regulator-name = "vreg_l6e"; + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8e: ldo8 { + regulator-name = "vreg_l8e"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + &i2c18 { clock-frequency = <400000>; pinctrl-0 = <&qup_i2c18_default>;
Signature · 1 line
2.37.2
Re: [PATCH v3 18/18] arm64: dts: qcom: sa8775p-ride: add PMIC regulators
Quoted 85 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add PMIC regulators for sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>--- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 233 ++++++++++++++++++++++ 1 file changed, 233 insertions(+)arch/arm64/boot/dts/qcom/sa8775p-ride.dts +61
-0@@ -5,6 +5,8 @@ /dts-v1/; +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + #include "sa8775p.dtsi" #include "sa8775p-pmics.dtsi"@@ -25,6 +27,237 @@ chosen { }; }; +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1816000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1996000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9a: smps9 { + regulator-name = "vreg_s9a"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <720000>;
arch/arm64/boot/dts/qcom/sa8775p-ride.dts chosen { · line 98
Quoted 10 lines
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +10
-0+ regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2400000>;
Hi Bart,
Internally with PMIC2.0 i.e K2 upgraded board we were seeing target crash when kernel votes for 2.4V with fault monitors enabled in K2. So let's keep the recommended value <2504000> for ldo8.
-Shazad
Quoted 165 lines
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +162
-0+ regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + /* + * FIXME: This should have regulator-allow-set-load but + * we're getting the over-current fault from the PMIC + * when switching to LPM. + */ + }; + + vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_s4e: smps4 { + regulator-name = "vreg_s4e"; + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1520000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s7e: smps7 { + regulator-name = "vreg_s7e"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9e: smps9 { + regulator-name = "vreg_s9e"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6e: ldo6 { + regulator-name = "vreg_l6e"; + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8e: ldo8 { + regulator-name = "vreg_l8e"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + &i2c18 { clock-frequency = <400000>; pinctrl-0 = <&qup_i2c18_default>;
Re: (subset) [PATCH v3 00/18] arm64: dts: qcom: sa8775p: add basic PMIC support
In reply to Bartosz GolaszewskiQuoted 16 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
This adds support for a number of PMIC functionalities on sa8775p. The PMIC used on the reference board is pm8654au which is another variant of the SPMI PMIC from Qualcomm with an automotive twist.
v2 -> v3:
- add GPIO line names for the PMIC GPIOs on sa8775p-ride
- add missing GPIO chips to the PMIC .dtsi
- add missing thermal zones and alerts
- add regulators (driver support and regulator settings for sa8775p-ride)
- add missing PDC mappings
- squash patches 7 and 8 to avoid adding code without users
- dropped Krzysztof's Ack from patch 3 as it now extends the max number of mappings so most likely needs a second look
Quoted 1 line
[...]
Applied, thanks!
[01/18] arm64: dts: qcom: sa8775p: pad reg properties to 8 digits
commit: 3fd7e2eec8f4fedbe3b252cf436be8527f7a5f82
[02/18] arm64: dts: qcom: sa8775p: sort soc nodes by reg property
commit: f95f988cf7b609157630dd1f2f7e8d297aadbe2b
[04/18] arm64: dts: qcom: sa8775p: add the pdc node
commit: 8696cd072e955bd6f5df757774e47f0b9dd29920
[05/18] arm64: dts: qcom: sa8775p: add the spmi node
commit: fdd55b3babedce5abd1c1f90afc3ab2199a772ad
[07/18] arm64: dts: qcom: sa8775p: add support for the on-board PMICs
commit: 634a3de323fc5c67c144919e298259d8d9d44a4b
[08/18] arm64: dts: qcom: sa8775p: add the Power On device node
commit: d2d9a592746cd454bd5b8f72193f2d3db2e62a44
[09/18] arm64: dts: qcom: sa8775p: pmic: add the power key
commit: b3a755ba16e6f61d93c811b827edacc9946b0500
[10/18] arm64: dts: qcom: sa8775p: pmic: add support for the pmm8654 RESIN input
commit: cecff1f5429d975df9649376e2bd5a2fb004f988
[11/18] arm64: dts: qcom: sa8775p: pmic: add thermal zones
commit: fa40ca07e943333a14d247988ef5008a59949153
[14/18] arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes
commit: e5a893a7cec5776e10c25d7fa80b5ad1edf88c17
[15/18] arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs
commit: 81767c1591dcb711f1f78a80e510b667b1fb5718Best regards,
Signature · 1 line
Bjorn Andersson <[email protected]>