Enable IPQ9754 USB
Subsystems (7)
v4 cover Enable IPQ9754 USB
This patch series adds the relevant phy and controller configurations for enabling USB on IPQ9754
Depends on:
https://lore.kernel.org/all/[email protected]/
[v4]:
- Incorporated review comments
- Address all 'make dtbs_check' errors
[v3]:
- Incorporated review comments regarding coding style
[v2]:
- Incorporated review comments regarding coding style, maintaining sorted order of entries and unused phy register offsets
- Removed NOC clock entries from DT node (will be implemented later with interconnect support)
- Fixed 'make dtbs_check' errors/warnings
[v1]:
https://lore.kernel.org/linux-arm-msm/[email protected]/T/
Varadarajan Narayanan (8):
dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
dt-bindings: usb: dwc3: Add IPQ9574 compatible
clk: qcom: gcc-ipq9574: Add USB related clocks
phy: qcom-qusb2: add QUSB2 support for IPQ9574
phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
arm64: dts: qcom: ipq9574: Add USB related nodes
arm64: dts: qcom: ipq9574: Enable USB
.../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 +++- .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 6 +- .../devicetree/bindings/usb/qcom,dwc3.yaml | 22 +++- arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 12 ++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 83 +++++++++++++ drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 129 +++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 + include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 + 9 files changed, 310 insertions(+), 9 deletions(-)
Signature · 7 lines
2.7.4 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v4 1/8 dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
Document the compatible string used for the qusb2 phy in IPQ9574.
---
Changes in v4:
- Remove constraints not applicable to IPQ9574
Changes in v3:
- Maintain the proper sorted order
Changes in v2:
- Moved ipq6018 to the proper place and placed ipq9574 next to it as suggested by Dmitry
--- Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +2 -4
@@ -18,13 +18,14 @@ properties: oneOf: - items: - enum: + - qcom,ipq6018-qusb2-phy - qcom,ipq8074-qusb2-phy + - qcom,ipq9574-qusb2-phy - qcom,msm8953-qusb2-phy - qcom,msm8996-qusb2-phy - qcom,msm8998-qusb2-phy - qcom,qcm2290-qusb2-phy - qcom,sdm660-qusb2-phy - - qcom,ipq6018-qusb2-phy - qcom,sm4250-qusb2-phy - qcom,sm6115-qusb2-phy - items:
@@ -157,9 +158,6 @@ required: - "#phy-cells" - clocks - clock-names - - vdd-supply - - vdda-pll-supply - - vdda-phy-dpdm-supply - resets allOf:
Signature · 7 lines
2.7.4 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Re: [PATCH v4 1/8] dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
Quoted 8 lines · Varadarajan Narayanan
Document the compatible string used for the qusb2 phy in IPQ9574.
Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Remove constraints not applicable to IPQ9574
I don't think this is a correct way to go
Quoted 31 lines
Changes in v3:
- Maintain the proper sorted orderChanges in v2:
- Moved ipq6018 to the proper place and placed ipq9574 next to it as suggested by Dmitry--- Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +2
-1@@ -18,13 +18,14 @@ properties: oneOf: - items: - enum: + - qcom,ipq6018-qusb2-phy - qcom,ipq8074-qusb2-phy + - qcom,ipq9574-qusb2-phy - qcom,msm8953-qusb2-phy - qcom,msm8996-qusb2-phy - qcom,msm8998-qusb2-phy - qcom,qcm2290-qusb2-phy - qcom,sdm660-qusb2-phy - - qcom,ipq6018-qusb2-phy - qcom,sm4250-qusb2-phy - qcom,sm6115-qusb2-phy - items:
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml required: · line 162
Quoted 6 lines
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +0
-3@@ -157,9 +158,6 @@ required: - "#phy-cells" - clocks - clock-names - - vdd-supply - - vdda-pll-supply - - vdda-phy-dpdm-supply
So, how does ipq9574 power on the PHY?
Quoted 3 lines
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +0
-0- resets allOf:
Signature · 2 lines
With best wishes Dmitry
PATCH v4 2/8 dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
In reply to Varadarajan NarayananAdd dt-bindings for USB3 PHY found on Qualcomm IPQ9574
---
Changes in v4:
- Remove constraints not applicable to IPQ9574
Changes in v3:
- Update other mandatory fields to accomodate IPQ9574
Changes in v2:
- Updated sections missed in previous patch
--- .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +23 -2
@@ -21,6 +21,7 @@ properties: enum: - qcom,ipq6018-qmp-usb3-phy - qcom,ipq8074-qmp-usb3-phy + - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - qcom,msm8998-qmp-usb3-phy - qcom,qcm2290-qmp-usb3-phy
@@ -122,8 +123,6 @@ required: - clock-names - resets - reset-names - - vdda-phy-supply - - vdda-pll-supply additionalProperties: false
@@ -204,6 +203,28 @@ allOf: compatible: contains: enum: + - qcom,ipq9574-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: pipe + resets: + maxItems: 2 + reset-names: + items: + - const: phy + - const: common + + - if: + properties: + compatible: + contains: + enum: - qcom,sm8150-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy - qcom,sm8250-qmp-usb3-uni-phy
Signature · 7 lines
2.7.4 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Re: [PATCH v4 2/8] dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
Quoted 27 lines · Varadarajan Narayanan
Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Remove constraints not applicable to IPQ9574
Changes in v3:
- Update other mandatory fields to accomodate IPQ9574
Changes in v2:
- Updated sections missed in previous patch--- .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +1
-0@@ -21,6 +21,7 @@ properties: enum: - qcom,ipq6018-qmp-usb3-phy - qcom,ipq8074-qmp-usb3-phy + - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - qcom,msm8998-qmp-usb3-phy - qcom,qcm2290-qmp-usb3-phy
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml required: · line 126
Quoted 5 lines
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +0
-2@@ -122,8 +123,6 @@ required: - clock-names - resets - reset-names - - vdda-phy-supply - - vdda-pll-supply
Same questions as for the qusb2 PHY. How is the PHY powered?
Quoted 3 lines
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +0
-0additionalProperties: false
Signature · 2 lines
With best wishes Dmitry
Re: [PATCH v4 2/8] dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
Quoted 27 lines · Dmitry Baryshkov
Quoted 26 lines · Varadarajan Narayanan
Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Remove constraints not applicable to IPQ9574
Changes in v3:
- Update other mandatory fields to accomodate IPQ9574
Changes in v2:
- Updated sections missed in previous patch--- .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +1
-0@@ -21,6 +21,7 @@ properties: enum: - qcom,ipq6018-qmp-usb3-phy - qcom,ipq8074-qmp-usb3-phy + - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - qcom,msm8998-qmp-usb3-phy - qcom,qcm2290-qmp-usb3-phy
Quoted 8 lines
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml required: · line 126
Quoted 6 lines
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +0
-2@@ -122,8 +123,6 @@ required: - clock-names - resets - reset-names - - vdda-phy-supply - - vdda-pll-supplySame questions as for the qusb2 PHY. How is the PHY powered?
It is powered by always on regulators. Will create fixed regulators and assign them to these.
Thanks
Varada
Quoted 6 lines
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml required: · line 127
Quoted 1 line
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +0
-0additionalProperties: false--
With best wishes
Dmitry
Signature · 3 lines
linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Re: [PATCH v4 2/8] dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
Quoted 37 lines · Varadarajan Narayanan
Quoted 27 lines · Dmitry Baryshkov
Quoted 26 lines · Varadarajan Narayanan
Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Remove constraints not applicable to IPQ9574
Changes in v3:
- Update other mandatory fields to accomodate IPQ9574
Changes in v2:
- Updated sections missed in previous patch--- .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +1
-0@@ -21,6 +21,7 @@ properties: enum: - qcom,ipq6018-qmp-usb3-phy - qcom,ipq8074-qmp-usb3-phy + - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - qcom,msm8998-qmp-usb3-phy - qcom,qcm2290-qmp-usb3-phyQuoted 8 lines
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml required: · line 126
Quoted 6 lines
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +0
-2@@ -122,8 +123,6 @@ required: - clock-names - resets - reset-names - - vdda-phy-supply - - vdda-pll-supplySame questions as for the qusb2 PHY. How is the PHY powered?
Quoted 2 lines
It is powered by always on regulators. Will create fixed regulators and assign them to these.
always-on where? in DTS? Then it is not really related to this patch... or you meant always-on power domains? Yet still device has power supplies.
Best regards,
Krzysztof
Re: [PATCH v4 2/8] dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
In reply to Varadarajan NarayananQuoted 39 lines · Varadarajan Narayanan
Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Remove constraints not applicable to IPQ9574
Changes in v3:
- Update other mandatory fields to accomodate IPQ9574
Changes in v2:
- Updated sections missed in previous patch--- .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +1
-2@@ -21,6 +21,7 @@ properties: enum: - qcom,ipq6018-qmp-usb3-phy - qcom,ipq8074-qmp-usb3-phy + - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - qcom,msm8998-qmp-usb3-phy - qcom,qcm2290-qmp-usb3-phy@@ -122,8 +123,6 @@ required: - clock-names - resets - reset-names - - vdda-phy-supply - - vdda-pll-supply additionalProperties: false@@ -204,6 +203,28 @@ allOf: compatible: contains: enum:
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml allOf: · line 215
Quoted 10 lines
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +10
-0+ - qcom,ipq9574-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: pipe
Isn't pipe the clock for child node?
Best regards,
Krzysztof
Re: [PATCH v4 2/8] dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
Quoted 36 lines · Krzysztof Kozlowski
Quoted 35 lines · Varadarajan Narayanan
Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Remove constraints not applicable to IPQ9574
Changes in v3:
- Update other mandatory fields to accomodate IPQ9574
Changes in v2:
- Updated sections missed in previous patch--- .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +1
-2@@ -21,6 +21,7 @@ properties: enum: - qcom,ipq6018-qmp-usb3-phy - qcom,ipq8074-qmp-usb3-phy + - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - qcom,msm8998-qmp-usb3-phy - qcom,qcm2290-qmp-usb3-phy@@ -122,8 +123,6 @@ required: - clock-names - resets - reset-names - - vdda-phy-supply - - vdda-pll-supply additionalProperties: false
Quoted 16 lines
Quoted 4 lines
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +0
-0@@ -204,6 +203,28 @@ allOf: compatible: contains: enum:Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml allOf: · line 215
Quoted 10 lines
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +10
-0+ - qcom,ipq9574-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: pipeIsn't pipe the clock for child node?
Will be moving to a newer style binding (as specified in qcom,sc8280xp-qmp-usb3-uni-phy.yaml). Will update accordingly and post the patch.
Thanks
Varada
Quoted 3 lines
Best regards,
Krzysztof
Signature · 3 lines
linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v4 3/8 dt-bindings: usb: dwc3: Add IPQ9574 compatible
In reply to Varadarajan NarayananDocument the IPQ9574 dwc3 compatible.
---
Changes in v4:
- Update other relevant sections
- Remove constraints not applicable to IPQ9574
--- .../devicetree/bindings/usb/qcom,dwc3.yaml | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +19 -3
@@ -17,6 +17,7 @@ properties: - qcom,ipq6018-dwc3 - qcom,ipq8064-dwc3 - qcom,ipq8074-dwc3 + - qcom,ipq9574-dwc3 - qcom,msm8953-dwc3 - qcom,msm8994-dwc3 - qcom,msm8996-dwc3
@@ -132,11 +133,8 @@ required: - "#address-cells" - "#size-cells" - ranges - - power-domains - clocks - clock-names - - interrupts - - interrupt-names allOf: - if:
@@ -242,6 +240,24 @@ allOf: compatible: contains: enum: + - qcom,ipq9574-dwc3 + then: + properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: sys_noc_axi + - const: anoc_axi + - const: master + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: - qcom,msm8994-dwc3 - qcom,qcs404-dwc3 then:
Signature · 7 lines
2.7.4 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Re: [PATCH v4 3/8] dt-bindings: usb: dwc3: Add IPQ9574 compatible
Quoted 7 lines · Varadarajan Narayanan
Document the IPQ9574 dwc3 compatible.
Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Update other relevant sections
- Remove constraints not applicable to IPQ9574
No, that's not way to go. These are required.
Quoted 31 lines
--- .../devicetree/bindings/usb/qcom,dwc3.yaml | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +1
-3@@ -17,6 +17,7 @@ properties: - qcom,ipq6018-dwc3 - qcom,ipq8064-dwc3 - qcom,ipq8074-dwc3 + - qcom,ipq9574-dwc3 - qcom,msm8953-dwc3 - qcom,msm8994-dwc3 - qcom,msm8996-dwc3@@ -132,11 +133,8 @@ required: - "#address-cells" - "#size-cells" - ranges - - power-domains - clocks - clock-names - - interrupts - - interrupt-names allOf: - if:@@ -242,6 +240,24 @@ allOf: compatible: contains:
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml allOf: · line 251
Quoted 10 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +9
-0enum: + - qcom,ipq9574-dwc3 + then: + properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: sys_noc_axi + - const: anoc_axi
Heh, do we really need entirely different clock names for each new variant?
Best regards,
Krzysztof
Re: [PATCH v4 3/8] dt-bindings: usb: dwc3: Add IPQ9574 compatible
Quoted 10 lines · Krzysztof Kozlowski
Quoted 7 lines · Varadarajan Narayanan
Document the IPQ9574 dwc3 compatible.
Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Update other relevant sections
- Remove constraints not applicable to IPQ9574No, that's not way to go. These are required.
Yes. Misinterpreted an earlier comment.
Will fix this.
Quoted 35 lines
Quoted 35 lines
--- .../devicetree/bindings/usb/qcom,dwc3.yaml | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +4
-3@@ -17,6 +17,7 @@ properties: - qcom,ipq6018-dwc3 - qcom,ipq8064-dwc3 - qcom,ipq8074-dwc3 + - qcom,ipq9574-dwc3 - qcom,msm8953-dwc3 - qcom,msm8994-dwc3 - qcom,msm8996-dwc3@@ -132,11 +133,8 @@ required: - "#address-cells" - "#size-cells" - ranges - - power-domains - clocks - clock-names - - interrupts - - interrupt-names allOf: - if:@@ -242,6 +240,24 @@ allOf: compatible: contains: enum: + - qcom,ipq9574-dwc3 + then: + properties:
Quoted 8 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml allOf: · line 251
Quoted 6 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +6
-0+ clocks: + maxItems: 5 + clock-names: + items: + - const: sys_noc_axi + - const: anoc_axiHeh, do we really need entirely different clock names for each new variant?
Will fix and post a new patch.
Thanks
Varada
Quoted 3 lines
Best regards,
Krzysztof
Signature · 3 lines
linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v4 4/8 clk: qcom: gcc-ipq9574: Add USB related clocks
In reply to Varadarajan NarayananAdd the clocks needed for enabling USB in IPQ9574
---
Changes in v2:
- Fixed coding style issues
--- drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++ 2 files changed, 39 insertions(+)
drivers/clk/qcom/gcc-ipq9574.c +37 -0
@@ -2041,6 +2041,41 @@ static struct clk_regmap_mux usb0_pipe_clk_src = { }, }; +static struct clk_branch gcc_usb0_pipe_clk = { + .halt_reg =0x2c054 , + .halt_check =BRANCH_HALT_DELAY , + .clkr = { + .enable_reg =0x2c054 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_usb0_pipe_clk" , + .parent_hws = (const struct clk_hw *[]) { + &usb0_pipe_clk_src.clkr.hw + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_sleep_clk = { + .halt_reg =0x2c058 , + .clkr = { + .enable_reg =0x2c058 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_usb0_sleep_clk" , + .parent_hws = (const struct clk_hw *[]) { + &gcc_sleep_clk_src.clkr.hw + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; +static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {F (144000 ,P_XO ,16 ,12 ,125 ),F (400000 ,P_XO ,12 ,1 ,5 ),
@@ -4008,6 +4043,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr, [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, + [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, + [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
include/dt-bindings/clock/qcom,ipq9574-gcc.h +2 -0
@@ -214,4 +214,6 @@#define GCC_SNOC_PCIE1_1LANE_S_CLK 205#define GCC_SNOC_PCIE2_2LANE_S_CLK 206#define GCC_SNOC_PCIE3_2LANE_S_CLK 207 +#define GCC_USB0_PIPE_CLK 208 +#define GCC_USB0_SLEEP_CLK 209#endif
Signature · 7 lines
2.7.4 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Re: [PATCH v4 4/8] clk: qcom: gcc-ipq9574: Add USB related clocks
Quoted 11 lines · Varadarajan Narayanan
Add the clocks needed for enabling USB in IPQ9574
Acked-by Stephen Boyd <[email protected]>Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v2:
- Fixed coding style issues--- drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++ 2 files changed, 39 insertions(+)
Signature · 2 lines
With best wishes Dmitry
PATCH v4 5/8 phy: qcom-qusb2: add QUSB2 support for IPQ9574
In reply to Varadarajan NarayananAdd the phy init sequence for the Super Speed ports found on IPQ9574.
---
Changes in v2:
- Place the entry such that the list continues to be sorted
--- drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++ 1 file changed, 3 insertions(+)
drivers/phy/qualcomm/phy-qcom-qusb2.c +3 -0
@@ -912,6 +912,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = { .compatible = "qcom,ipq8074-qusb2-phy", .data = &msm8996_phy_cfg, }, { + .compatible = "qcom,ipq9574-qusb2-phy", + .data = &ipq6018_phy_cfg, + }, { .compatible = "qcom,msm8953-qusb2-phy", .data = &msm8996_phy_cfg, }, {
Signature · 7 lines
2.7.4 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Re: [PATCH v4 5/8] phy: qcom-qusb2: add QUSB2 support for IPQ9574
Quoted 10 lines · Varadarajan Narayanan
Add the phy init sequence for the Super Speed ports found on IPQ9574.
Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v2:
- Place the entry such that the list continues to be sorted--- drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++ 1 file changed, 3 insertions(+)
Signature · 8 lines
With best wishes Dmitry -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v4 6/8 phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
In reply to Varadarajan NarayananUpdated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets.
---
Changes in v4:
- Use qmp_usb_offsets for register space access
Changes in v3:
- Fix hex captitalization
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order
--- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 129 ++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+)
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +129 -0
@@ -94,6 +94,7 @@ enum qphy_reg_layout {QPHY_PCS_STATUS ,QPHY_PCS_AUTONOMOUS_MODE_CTRL ,QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR , +QPHY_PCS_LFPS_RXTERM_IRQ_STATUS ,QPHY_PCS_POWER_DOWN_CONTROL ,/* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE
@@ -139,6 +140,97 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, }; +static const unsigned int usb3phy_regs_layout[] = { + [QPHY_SW_RESET ] =0x00 , + [QPHY_START_CTRL ] =0x08 , + [QPHY_PCS_STATUS ] =0x17c , + [QPHY_PCS_AUTONOMOUS_MODE_CTRL ] =0x0d4 , + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR ] =0x0d8 , + [QPHY_PCS_POWER_DOWN_CONTROL ] =0x04 , +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_COM_SYSCLK_EN_SEL ,0x1a ), +QMP_PHY_INIT_CFG (QSERDES_COM_BIAS_EN_CLKBUFLR_EN ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CLK_SELECT ,0x30 ), +QMP_PHY_INIT_CFG (QSERDES_COM_BG_TRIM ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_RX_UCDR_FASTLOCK_FO_GAIN ,0x0b ), +QMP_PHY_INIT_CFG (QSERDES_COM_SVS_MODE_CLK_SEL ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_COM_HSCLK_SEL ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CMN_CONFIG ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_COM_PLL_IVCO ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_COM_SYS_CLK_CTRL ,0x06 ), +/* PLL and Loop filter settings */ +QMP_PHY_INIT_CFG (QSERDES_COM_DEC_START_MODE0 ,0x68 ), +QMP_PHY_INIT_CFG (QSERDES_COM_DIV_FRAC_START1_MODE0 ,0xab ), +QMP_PHY_INIT_CFG (QSERDES_COM_DIV_FRAC_START2_MODE0 ,0xaa ), +QMP_PHY_INIT_CFG (QSERDES_COM_DIV_FRAC_START3_MODE0 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CP_CTRL_MODE0 ,0x09 ), +QMP_PHY_INIT_CFG (QSERDES_COM_PLL_RCTRL_MODE0 ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_COM_PLL_CCTRL_MODE0 ,0x28 ), +QMP_PHY_INIT_CFG (QSERDES_COM_INTEGLOOP_GAIN0_MODE0 ,0xa0 ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP1_MODE0 ,0xaa ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP2_MODE0 ,0x29 ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP3_MODE0 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CORE_CLK_EN ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP_CFG ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_VCO_TUNE_MAP ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_BG_TIMER ,0x0a ), +/* SSC settings */ +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_EN_CENTER ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_PER1 ,0x7d ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_PER2 ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_ADJ_PER1 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_ADJ_PER2 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_STEP_SIZE1 ,0x0a ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_STEP_SIZE2 ,0x05 ), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN ,0x45 ), +QMP_PHY_INIT_CFG (QSERDES_TX_RCV_DETECT_LVL_2 ,0x12 ), +QMP_PHY_INIT_CFG (QSERDES_TX_LANE_MODE ,0x06 ), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_RX_UCDR_SO_GAIN ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 ,0x6c ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 ,0x4c ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 ,0xb8 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 ,0x77 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 ,0x80 ), +QMP_PHY_INIT_CFG (QSERDES_RX_SIGDET_CNTRL ,0x03 ), +QMP_PHY_INIT_CFG (QSERDES_RX_SIGDET_DEGLITCH_CNTRL ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_RX_SIGDET_ENABLES ,0x0c ), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = { +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_V0 ,0x15 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 ,0x0e ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNTRL2 ,0x83 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNTRL1 ,0x02 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNT_VAL_L ,0x09 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNT_VAL_H_TOL ,0xa2 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_MAN_CODE ,0x85 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG1 ,0xd1 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG2 ,0x1f ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG3 ,0x47 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_POWER_STATE_CONFIG2 ,0x1b ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME ,0x75 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RXEQTRAINING_RUN_TIME ,0x13 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK ,0x86 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK ,0x04 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TSYNC_RSYNC_TIME ,0x44 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L ,0xe7 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H ,0x03 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L ,0x40 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H ,0x00 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RX_SIGDET_LVL ,0x88 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_V0 ,0x17 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 ,0x0f ), +}; +static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {QMP_PHY_INIT_CFG (QSERDES_COM_SYSCLK_EN_SEL ,0x1a ),QMP_PHY_INIT_CFG (QSERDES_COM_BIAS_EN_CLKBUFLR_EN ,0x08 ),
@@ -1510,6 +1602,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) }/* list of clocks required by phy */ +static const char *const ipq9574_phy_clk_l[] = { +"aux" ,"cfg_ahb" , +}; +static const char *const msm8996_phy_clk_l[] = {"aux" ,"cfg_ahb" ,"ref" , };
@@ -1558,6 +1654,14 @@ static const char * const qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", }; +static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = { + .serdes =0 , + .pcs =0x800 , + .pcs_usb =0x600 , + .tx =0x200 , + .rx =0x400 , +}; +static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { .serdes =0 , .pcs =0x0200 ,
@@ -1586,6 +1690,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { .regs = qmp_v3_usb3phy_regs_layout, }; +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = { + .lanes =1 , + + .offsets = &qmp_usb_offsets_ipq9574, + + .serdes_tbl = ipq9574_usb3_serdes_tbl, + .serdes_tbl_num =ARRAY_SIZE (ipq9574_usb3_serdes_tbl), + .tx_tbl = ipq9574_usb3_tx_tbl, + .tx_tbl_num =ARRAY_SIZE (ipq9574_usb3_tx_tbl), + .rx_tbl = ipq9574_usb3_rx_tbl, + .rx_tbl_num =ARRAY_SIZE (ipq9574_usb3_rx_tbl), + .pcs_tbl = ipq9574_usb3_pcs_tbl, + .pcs_tbl_num =ARRAY_SIZE (ipq9574_usb3_pcs_tbl), + .clk_list = ipq9574_phy_clk_l, + .num_clks =ARRAY_SIZE (ipq9574_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets =ARRAY_SIZE (msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs =ARRAY_SIZE (qmp_phy_vreg_l), + .regs = usb3phy_regs_layout, +}; +static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { .lanes =1 ,
@@ -2589,6 +2715,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = { .compatible = "qcom,ipq8074-qmp-usb3-phy", .data = &ipq8074_usb3phy_cfg, }, { + .compatible = "qcom,ipq9574-qmp-usb3-phy", + .data = &ipq9574_usb3phy_cfg, + }, { .compatible = "qcom,msm8996-qmp-usb3-phy", .data = &msm8996_usb3phy_cfg, }, {
Signature · 7 lines
2.7.4 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Re: [PATCH v4 6/8] phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
Quoted 24 lines · Varadarajan Narayanan
Updated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets.
Signed-off-by Praveenkumar I <[email protected]>Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Useqmp_usb_offsetsfor register space access
Changes in v3:
- Fix hex captitalization
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order--- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 129 ++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+)drivers/phy/qualcomm/phy-qcom-qmp-usb.c +0
-0
drivers/phy/qualcomm/phy-qcom-qmp-usb.c enum qphy_reg_layout { · line 97
Quoted 4 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +1
-0@@ -94,6 +94,7 @@ enum qphy_reg_layout {QPHY_PCS_STATUS ,QPHY_PCS_AUTONOMOUS_MODE_CTRL ,QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR , + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
This is unused
Quoted 5 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +0
-0QPHY_PCS_POWER_DOWN_CONTROL ,/* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE @@ -139,6 +140,97 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
drivers/phy/qualcomm/phy-qcom-qmp-usb.c static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { · line 150
Quoted 10 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +8
-0}; +static const unsigned int usb3phy_regs_layout[] = { + [QPHY_SW_RESET ] =0x00 , + [QPHY_START_CTRL ] =0x08 , + [QPHY_PCS_STATUS ] =0x17c , + [QPHY_PCS_AUTONOMOUS_MODE_CTRL ] =0x0d4 , + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR ] =0x0d8 , + [QPHY_PCS_POWER_DOWN_CONTROL ] =0x04 , +};
This does not look correct. you are yousing QPHY_V3_PCS for the table, while your register layout corresponds to QPHY_V2_PCS registers. Please doublecheck this. Also, is there any reason to duplicate existing qmp_v2_usb3phy_regs_layout or qmp_v3_usb3phy_regs_layout?
Quoted 87 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +83
-0+ +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_COM_SYSCLK_EN_SEL ,0x1a ), +QMP_PHY_INIT_CFG (QSERDES_COM_BIAS_EN_CLKBUFLR_EN ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CLK_SELECT ,0x30 ), +QMP_PHY_INIT_CFG (QSERDES_COM_BG_TRIM ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_RX_UCDR_FASTLOCK_FO_GAIN ,0x0b ), +QMP_PHY_INIT_CFG (QSERDES_COM_SVS_MODE_CLK_SEL ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_COM_HSCLK_SEL ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CMN_CONFIG ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_COM_PLL_IVCO ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_COM_SYS_CLK_CTRL ,0x06 ), +/* PLL and Loop filter settings */ +QMP_PHY_INIT_CFG (QSERDES_COM_DEC_START_MODE0 ,0x68 ), +QMP_PHY_INIT_CFG (QSERDES_COM_DIV_FRAC_START1_MODE0 ,0xab ), +QMP_PHY_INIT_CFG (QSERDES_COM_DIV_FRAC_START2_MODE0 ,0xaa ), +QMP_PHY_INIT_CFG (QSERDES_COM_DIV_FRAC_START3_MODE0 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CP_CTRL_MODE0 ,0x09 ), +QMP_PHY_INIT_CFG (QSERDES_COM_PLL_RCTRL_MODE0 ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_COM_PLL_CCTRL_MODE0 ,0x28 ), +QMP_PHY_INIT_CFG (QSERDES_COM_INTEGLOOP_GAIN0_MODE0 ,0xa0 ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP1_MODE0 ,0xaa ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP2_MODE0 ,0x29 ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP3_MODE0 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CORE_CLK_EN ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP_CFG ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_VCO_TUNE_MAP ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_BG_TIMER ,0x0a ), +/* SSC settings */ +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_EN_CENTER ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_PER1 ,0x7d ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_PER2 ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_ADJ_PER1 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_ADJ_PER2 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_STEP_SIZE1 ,0x0a ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_STEP_SIZE2 ,0x05 ), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN ,0x45 ), +QMP_PHY_INIT_CFG (QSERDES_TX_RCV_DETECT_LVL_2 ,0x12 ), +QMP_PHY_INIT_CFG (QSERDES_TX_LANE_MODE ,0x06 ), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_RX_UCDR_SO_GAIN ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 ,0x6c ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 ,0x4c ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 ,0xb8 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 ,0x77 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 ,0x80 ), +QMP_PHY_INIT_CFG (QSERDES_RX_SIGDET_CNTRL ,0x03 ), +QMP_PHY_INIT_CFG (QSERDES_RX_SIGDET_DEGLITCH_CNTRL ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_RX_SIGDET_ENABLES ,0x0c ), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = { +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_V0 ,0x15 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 ,0x0e ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNTRL2 ,0x83 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNTRL1 ,0x02 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNT_VAL_L ,0x09 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNT_VAL_H_TOL ,0xa2 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_MAN_CODE ,0x85 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG1 ,0xd1 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG2 ,0x1f ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG3 ,0x47 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_POWER_STATE_CONFIG2 ,0x1b ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME ,0x75 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RXEQTRAINING_RUN_TIME ,0x13 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK ,0x86 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK ,0x04 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TSYNC_RSYNC_TIME ,0x44 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L ,0xe7 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H ,0x03 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L ,0x40 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H ,0x00 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RX_SIGDET_LVL ,0x88 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_V0 ,0x17 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 ,0x0f ), +}; +static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {QMP_PHY_INIT_CFG (QSERDES_COM_SYSCLK_EN_SEL ,0x1a ),QMP_PHY_INIT_CFG (QSERDES_COM_BIAS_EN_CLKBUFLR_EN ,0x08 ),
drivers/phy/qualcomm/phy-qcom-qmp-usb.c static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) · line 1606
Quoted 5 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +2
-0@@ -1510,6 +1602,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) }/* list of clocks required by phy */ +static const char *const ipq9574_phy_clk_l[] = { +"aux" ,"cfg_ahb" ,
No ref clock?
drivers/phy/qualcomm/phy-qcom-qmp-usb.c static const char * const qmp_phy_vreg_l[] = { · line 1660
Quoted 13 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +6
-0+}; +static const char *const msm8996_phy_clk_l[] = {"aux" ,"cfg_ahb" ,"ref" , };@@ -1558,6 +1654,14 @@ static const char * const qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", }; +static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = { + .serdes =0 , + .pcs =0x800 , + .pcs_usb =0x600 ,
Are you confusing pcs_usb vs pcs_misc? There was no separate pcs_usb on v3 PHYs
Quoted 49 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +29
-1+ .tx = 0x200, + .rx = 0x400, +}; +static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { .serdes =0 , .pcs =0x0200 ,@@ -1586,6 +1690,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { .regs = qmp_v3_usb3phy_regs_layout, }; +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = { + .lanes =1 , + + .offsets = &qmp_usb_offsets_ipq9574, + + .serdes_tbl = ipq9574_usb3_serdes_tbl, + .serdes_tbl_num =ARRAY_SIZE (ipq9574_usb3_serdes_tbl), + .tx_tbl = ipq9574_usb3_tx_tbl, + .tx_tbl_num =ARRAY_SIZE (ipq9574_usb3_tx_tbl), + .rx_tbl = ipq9574_usb3_rx_tbl, + .rx_tbl_num =ARRAY_SIZE (ipq9574_usb3_rx_tbl), + .pcs_tbl = ipq9574_usb3_pcs_tbl, + .pcs_tbl_num =ARRAY_SIZE (ipq9574_usb3_pcs_tbl), + .clk_list = ipq9574_phy_clk_l, + .num_clks =ARRAY_SIZE (ipq9574_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets =ARRAY_SIZE (msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs =ARRAY_SIZE (qmp_phy_vreg_l), + .regs = usb3phy_regs_layout, +}; +static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { .lanes =1 ,@@ -2589,6 +2715,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = { .compatible = "qcom,ipq8074-qmp-usb3-phy", .data = &ipq8074_usb3phy_cfg, }, { + .compatible = "qcom,ipq9574-qmp-usb3-phy", + .data = &ipq9574_usb3phy_cfg, + }, { .compatible = "qcom,msm8996-qmp-usb3-phy", .data = &msm8996_usb3phy_cfg, }, { --2.7.4
Signature · 2 lines
With best wishes Dmitry
Re: [PATCH v4 6/8] phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
Quoted 21 lines · Dmitry Baryshkov
Quoted 19 lines · Varadarajan Narayanan
Updated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets.
Signed-off-by Praveenkumar I <[email protected]>Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Useqmp_usb_offsetsfor register space access
Changes in v3:
- Fix hex captitalization
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order--- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 129 ++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+)
Quoted 11 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c enum qphy_reg_layout { · line 97
Quoted 9 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +1
-0@@ -94,6 +94,7 @@ enum qphy_reg_layout {QPHY_PCS_STATUS ,QPHY_PCS_AUTONOMOUS_MODE_CTRL ,QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR , + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,This is unused
Will remove.
Quoted 7 lines
Quoted 7 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +0
-0QPHY_PCS_POWER_DOWN_CONTROL ,/* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE @@ -139,6 +140,97 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, };
Quoted 13 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { · line 150
Quoted 8 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +8
-0+static const unsigned int usb3phy_regs_layout[] = { + [QPHY_SW_RESET ] =0x00 , + [QPHY_START_CTRL ] =0x08 , + [QPHY_PCS_STATUS ] =0x17c , + [QPHY_PCS_AUTONOMOUS_MODE_CTRL ] =0x0d4 , + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR ] =0x0d8 , + [QPHY_PCS_POWER_DOWN_CONTROL ] =0x04 , +};This does not look correct. you are yousing
QPHY_V3_PCSfor the table, while your register layout corresponds toQPHY_V2_PCSregisters. Please doublecheck this. Also, is there any reason to duplicate existingqmp_v2_usb3phy_regs_layoutorqmp_v3_usb3phy_regs_layout?
Will check on this and post a new patch.
Quoted 89 lines
Quoted 89 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +83
-0+ +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_COM_SYSCLK_EN_SEL ,0x1a ), +QMP_PHY_INIT_CFG (QSERDES_COM_BIAS_EN_CLKBUFLR_EN ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CLK_SELECT ,0x30 ), +QMP_PHY_INIT_CFG (QSERDES_COM_BG_TRIM ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_RX_UCDR_FASTLOCK_FO_GAIN ,0x0b ), +QMP_PHY_INIT_CFG (QSERDES_COM_SVS_MODE_CLK_SEL ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_COM_HSCLK_SEL ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CMN_CONFIG ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_COM_PLL_IVCO ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_COM_SYS_CLK_CTRL ,0x06 ), +/* PLL and Loop filter settings */ +QMP_PHY_INIT_CFG (QSERDES_COM_DEC_START_MODE0 ,0x68 ), +QMP_PHY_INIT_CFG (QSERDES_COM_DIV_FRAC_START1_MODE0 ,0xab ), +QMP_PHY_INIT_CFG (QSERDES_COM_DIV_FRAC_START2_MODE0 ,0xaa ), +QMP_PHY_INIT_CFG (QSERDES_COM_DIV_FRAC_START3_MODE0 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CP_CTRL_MODE0 ,0x09 ), +QMP_PHY_INIT_CFG (QSERDES_COM_PLL_RCTRL_MODE0 ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_COM_PLL_CCTRL_MODE0 ,0x28 ), +QMP_PHY_INIT_CFG (QSERDES_COM_INTEGLOOP_GAIN0_MODE0 ,0xa0 ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP1_MODE0 ,0xaa ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP2_MODE0 ,0x29 ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP3_MODE0 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_CORE_CLK_EN ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_LOCK_CMP_CFG ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_VCO_TUNE_MAP ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_BG_TIMER ,0x0a ), +/* SSC settings */ +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_EN_CENTER ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_PER1 ,0x7d ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_PER2 ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_ADJ_PER1 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_ADJ_PER2 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_STEP_SIZE1 ,0x0a ), +QMP_PHY_INIT_CFG (QSERDES_COM_SSC_STEP_SIZE2 ,0x05 ), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN ,0x45 ), +QMP_PHY_INIT_CFG (QSERDES_TX_RCV_DETECT_LVL_2 ,0x12 ), +QMP_PHY_INIT_CFG (QSERDES_TX_LANE_MODE ,0x06 ), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_RX_UCDR_SO_GAIN ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 ,0x6c ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 ,0x4c ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 ,0xb8 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 ,0x77 ), +QMP_PHY_INIT_CFG (QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 ,0x80 ), +QMP_PHY_INIT_CFG (QSERDES_RX_SIGDET_CNTRL ,0x03 ), +QMP_PHY_INIT_CFG (QSERDES_RX_SIGDET_DEGLITCH_CNTRL ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_RX_SIGDET_ENABLES ,0x0c ), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = { +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_V0 ,0x15 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 ,0x0e ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNTRL2 ,0x83 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNTRL1 ,0x02 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNT_VAL_L ,0x09 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNT_VAL_H_TOL ,0xa2 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_MAN_CODE ,0x85 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG1 ,0xd1 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG2 ,0x1f ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG3 ,0x47 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_POWER_STATE_CONFIG2 ,0x1b ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME ,0x75 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RXEQTRAINING_RUN_TIME ,0x13 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK ,0x86 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK ,0x04 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TSYNC_RSYNC_TIME ,0x44 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L ,0xe7 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H ,0x03 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L ,0x40 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H ,0x00 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_RX_SIGDET_LVL ,0x88 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_V0 ,0x17 ), +QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 ,0x0f ), +}; +static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {QMP_PHY_INIT_CFG (QSERDES_COM_SYSCLK_EN_SEL ,0x1a ),QMP_PHY_INIT_CFG (QSERDES_COM_BIAS_EN_CLKBUFLR_EN ,0x08 ),@@ -1510,6 +1602,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) }
Quoted 5 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) · line 1606
Quoted 3 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +2
-0/* list of clocks required by phy */ +static const char *const ipq9574_phy_clk_l[] = { +"aux" ,"cfg_ahb" ,No ref clock?
Will see if i can use msm8996_phy_clk_l itself.
Quoted 9 lines
Quoted 9 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +2
-0+}; +static const char *const msm8996_phy_clk_l[] = {"aux" ,"cfg_ahb" ,"ref" , };@@ -1558,6 +1654,14 @@ static const char * const qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", };
Quoted 6 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c static const char * const qmp_phy_vreg_l[] = { · line 1660
Quoted 4 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +4
-0+static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = { + .serdes =0 , + .pcs =0x800 , + .pcs_usb =0x600 ,Are you confusing
pcs_usbvspcs_misc? There was no separatepcs_usbon v3 PHYs
Yes, my mistake. Will fix this.
Thanks
Varada
Quoted 54 lines
Quoted 47 lines
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +29
-1+ .tx = 0x200, + .rx = 0x400, +}; +static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { .serdes =0 , .pcs =0x0200 ,@@ -1586,6 +1690,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { .regs = qmp_v3_usb3phy_regs_layout, }; +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = { + .lanes =1 , + + .offsets = &qmp_usb_offsets_ipq9574, + + .serdes_tbl = ipq9574_usb3_serdes_tbl, + .serdes_tbl_num =ARRAY_SIZE (ipq9574_usb3_serdes_tbl), + .tx_tbl = ipq9574_usb3_tx_tbl, + .tx_tbl_num =ARRAY_SIZE (ipq9574_usb3_tx_tbl), + .rx_tbl = ipq9574_usb3_rx_tbl, + .rx_tbl_num =ARRAY_SIZE (ipq9574_usb3_rx_tbl), + .pcs_tbl = ipq9574_usb3_pcs_tbl, + .pcs_tbl_num =ARRAY_SIZE (ipq9574_usb3_pcs_tbl), + .clk_list = ipq9574_phy_clk_l, + .num_clks =ARRAY_SIZE (ipq9574_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets =ARRAY_SIZE (msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs =ARRAY_SIZE (qmp_phy_vreg_l), + .regs = usb3phy_regs_layout, +}; +static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { .lanes =1 ,@@ -2589,6 +2715,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = { .compatible = "qcom,ipq8074-qmp-usb3-phy", .data = &ipq8074_usb3phy_cfg, }, { + .compatible = "qcom,ipq9574-qmp-usb3-phy", + .data = &ipq9574_usb3phy_cfg, + }, { .compatible = "qcom,msm8996-qmp-usb3-phy", .data = &msm8996_usb3phy_cfg, }, { --Quoted 2 lines
2.7.4
--
With best wishes
Dmitry
Signature · 3 lines
linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v4 7/8 arm64: dts: qcom: ipq9574: Add USB related nodes
In reply to Varadarajan NarayananAdd USB phy and controller related nodes
---
Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issues
Changes in v3:
- Insert the nodes at proper location
Changes in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by make dtbs_check
- Remove NOC related clocks (to be added with proper interconnect support)
--- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 83 +++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574.dtsi +83 -0
@@ -215,6 +215,45 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + qusb_phy_0: phy@7b000 { + compatible = "qcom,ipq9574-qusb2-phy"; + reg = <0x0007b000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board_clk>; + clock-names = "cfg_ahb", + "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + ssphy_0: phy@7d000 { + compatible = "qcom,ipq9574-qmp-usb3-phy"; + reg = <0x0007d000 0xa00>; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; + + #phy-cells = <0>; + clock-output-names = "usb0_pipe_clk"; + }; + pcie0_phy: phy@84000 { compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; reg = <0x00084000 0x1bc>; /* Serdes PLL */
@@ -436,6 +475,50 @@ status = "disabled"; }; + usb3: usb3@8a00000 { + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SNOC_USB_CLK>, + <&gcc GCC_ANOC_USB_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names = "sys_noc_axi", + "anoc_axi", + "master", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + resets = <&gcc GCC_USB_BCR>; + status = "disabled"; + + dwc_0: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xcd00>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_0>, <&ssphy_0>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */
Signature · 7 lines
2.7.4 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Re: [PATCH v4 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes
Quoted 39 lines · Varadarajan Narayanan
Add USB phy and controller related nodes
Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issuesChanges in v3:
- Insert the nodes at proper locationChanges in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by makedtbs_check
- Remove NOC related clocks (to be added with proper interconnect support)--- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 83 +++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+)arch/arm64/boot/dts/qcom/ipq9574.dtsi +11
-0@@ -215,6 +215,45 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + qusb_phy_0: phy@7b000 { + compatible = "qcom,ipq9574-qusb2-phy"; + reg = <0x0007b000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board_clk>; + clock-names = "cfg_ahb", + "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
arch/arm64/boot/dts/qcom/ipq9574.dtsi line 238
Quoted 10 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +10
-0+ status = "disabled"; + }; + + ssphy_0: phy@7d000 { + compatible = "qcom,ipq9574-qmp-usb3-phy"; + reg = <0x0007d000 0xa00>; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges;
Why do you need these three?
Quoted 6 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +6
-0+ + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb",
arch/arm64/boot/dts/qcom/ipq9574.dtsi line 254
Quoted 10 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +10
-0+ "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; + + #phy-cells = <0>; + clock-output-names = "usb0_pipe_clk";
Does not look like you tested the DTS against bindings. Please run make dtbs_check (see Documentation/devicetree/bindings/writing-schema.rst for instructions).
arch/arm64/boot/dts/qcom/ipq9574.dtsi line 478
Quoted 10 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +3
-0+ }; + pcie0_phy: phy@84000 { compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; reg = <0x00084000 0x1bc>; /* Serdes PLL */@@ -436,6 +475,50 @@ status = "disabled"; }; + usb3: usb3@8a00000 {
usb@
Quoted 33 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +30
-0+ compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SNOC_USB_CLK>, + <&gcc GCC_ANOC_USB_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names = "sys_noc_axi", + "anoc_axi", + "master", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + resets = <&gcc GCC_USB_BCR>; + status = "disabled"; + + dwc_0: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xcd00>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
arch/arm64/boot/dts/qcom/ipq9574.dtsi line 518
Quoted 10 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +10
-0+ clock-names = "ref"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_0>, <&ssphy_0>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host";
Are you saying that peripheral mode cannot work on this USB controller? Never?
Best regards,
Krzysztof
Re: [PATCH v4 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes
Quoted 44 lines · Krzysztof Kozlowski
Quoted 43 lines · Varadarajan Narayanan
Add USB phy and controller related nodes
Signed-off-by Varadarajan Narayanan <[email protected]>---
Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issuesChanges in v3:
- Insert the nodes at proper locationChanges in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by makedtbs_check
- Remove NOC related clocks (to be added with proper interconnect support)--- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 83 +++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+)arch/arm64/boot/dts/qcom/ipq9574.dtsi +15
-0@@ -215,6 +215,45 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + qusb_phy_0: phy@7b000 { + compatible = "qcom,ipq9574-qusb2-phy"; + reg = <0x0007b000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board_clk>; + clock-names = "cfg_ahb", + "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + ssphy_0: phy@7d000 {
Quoted 8 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi line 238
Quoted 6 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +6
-0+ compatible = "qcom,ipq9574-qmp-usb3-phy"; + reg = <0x0007d000 0xa00>; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges;Why do you need these three?
Don't need these. Have moved to qcom,sc8280xp-qmp-usb3-uni-phy.yaml specification instead of qcom,msm8996-qmp-usb3-phy.yaml. Will update accordingly and post.
Quoted 12 lines
Quoted 12 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +12
-0+ + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "common";
Quoted 8 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi line 254
Quoted 4 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +4
-0+ status = "disabled"; + + #phy-cells = <0>; + clock-output-names = "usb0_pipe_clk";Does not look like you tested the DTS against bindings. Please run
make dtbs_check(seeDocumentation/devicetree/bindings/writing-schema.rstfor instructions).
Have addressed these and have created a new patch. Will post it shortly. IPQ9574 doesn't have any power domains, hence don't have power-domains entry in the DT node. make dtbs_check is giving the following messages hope that is ok
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yamlQuoted 10 lines
Quoted 10 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +2
-0+ }; + pcie0_phy: phy@84000 { compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; reg = <0x00084000 0x1bc>; /* Serdes PLL */@@ -436,6 +475,50 @@ status = "disabled"; };
Quoted 3 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi line 478
Quoted 1 line
arch/arm64/boot/dts/qcom/ipq9574.dtsi +1
-0+ usb3: usb3@8a00000 {usb@
Will fix.
Quoted 38 lines
Quoted 38 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +35
-0+ compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SNOC_USB_CLK>, + <&gcc GCC_ANOC_USB_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names = "sys_noc_axi", + "anoc_axi", + "master", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + resets = <&gcc GCC_USB_BCR>; + status = "disabled"; + + dwc_0: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xcd00>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_0>, <&ssphy_0>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize;
Quoted 8 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi line 518
Quoted 5 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +5
-0+ snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host";Are you saying that peripheral mode cannot work on this USB controller? Never?
Will move to board DTS.
Thanks
Varada
Quoted 3 lines
Best regards,
Krzysztof
Signature · 3 lines
linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v4 8/8 arm64: dts: qcom: ipq9574: Enable USB
In reply to Varadarajan NarayananTurn on USB related nodes
---
Changes in v2:
- Fix node placement and coding style
- "ok" -> "okay"
--- arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts +12 -0
@@ -57,6 +57,10 @@ status = "okay"; }; +&qusb_phy_0 { + status = "okay"; +}; + &rpm_requests { regulators { compatible = "qcom,rpm-mp5496-regulators";
@@ -84,6 +88,10 @@ clock-frequency = <32000>; }; +&ssphy_0 { + status = "okay"; +}; + &tlmm { sdc_default_state: sdc-default-state { clk-pins {
@@ -118,6 +126,10 @@ }; }; +&usb3 { + status = "okay"; +}; + &xo_board_clk { clock-frequency = <24000000>; };
Signature · 7 lines
2.7.4 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy