Enable IPQ9754 USB

Document the IPQ9574 dwc3 compatible.

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v5:
- Restore removed constraints

Changes in v4:
- Update other relevant sections
- Remove constraints not applicable to IPQ9574

---
 Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +3 -0

index a2aabda..8def6a3 100644
@@ -17,6 +17,7 @@ properties:
           - qcom,ipq6018-dwc3
           - qcom,ipq8064-dwc3
           - qcom,ipq8074-dwc3
+          - qcom,ipq9574-dwc3
           - qcom,msm8953-dwc3
           - qcom,msm8994-dwc3
           - qcom,msm8996-dwc3

@@ -242,6 +243,24 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,ipq9574-dwc3
+    then:

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +6 -1

+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
               - qcom,msm8994-dwc3
               - qcom,qcs404-dwc3
     then:
--

2.7.4

Document the IPQ9574 dwc3 compatible.

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v5:
- Restore removed constraints

Changes in v4:
- Update other relevant sections
- Remove constraints not applicable to IPQ9574

---
 Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Updated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets.

Signed-off-by Praveenkumar I <[email protected]>

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v5:
- Fix additional review comments
- Use V3 register offsets
Changes in v4:
- Use qmp_usb_offsets for register space access
Changes in v3:
- Fix hex captitalization
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order

---
 drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)

drivers/phy/qualcomm/phy-qcom-qmp-usb.c +82 -0

index a49711c..77041dd 100644
@@ -139,6 +139,88 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 };
 
+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+       /* PLL and Loop filter settings */
+       QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+       QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+       /* SSC settings */
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+       QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+       QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+};
+
 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),

drivers/phy/qualcomm/phy-qcom-qmp-usb.c +29 -1

+       .tx             = 0x200,
+       .rx             = 0x400,
+};
+
 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
        .serdes         = 0,
        .pcs            = 0x0200,

@@ -1586,6 +1676,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
        .regs                   = qmp_v3_usb3phy_regs_layout,
 };
 
+static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
+       .lanes                  = 1,
+
+       .offsets                = &qmp_usb_offsets_ipq9574,
+
+       .serdes_tbl             = ipq9574_usb3_serdes_tbl,
+       .serdes_tbl_num         = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
+       .tx_tbl                 = ipq9574_usb3_tx_tbl,
+       .tx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
+       .rx_tbl                 = ipq9574_usb3_rx_tbl,
+       .rx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
+       .pcs_tbl                = ipq9574_usb3_pcs_tbl,
+       .pcs_tbl_num            = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
+       .clk_list               = qmp_v4_phy_clk_l,
+       .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
+       .reset_list             = qcm2290_usb3phy_reset_l,
+       .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
+       .vreg_list              = qmp_phy_vreg_l,
+       .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
+       .regs                   = qmp_v3_usb3phy_regs_layout,
+};
+
 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
        .lanes                  = 1,
 

@@ -2589,6 +2701,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
                .compatible = "qcom,ipq8074-qmp-usb3-phy",
                .data = &ipq8074_usb3phy_cfg,
        }, {
+               .compatible = "qcom,ipq9574-qmp-usb3-phy",
+               .data = &ipq9574_usb3phy_cfg,
+       }, {
                .compatible = "qcom,msm8996-qmp-usb3-phy",
                .data = &msm8996_usb3phy_cfg,
        }, {
--

2.7.4

Quoted 119 lines · Varadarajan Narayanan

Updated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets.

Signed-off-by Praveenkumar I <[email protected]>

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v5:
- Fix additional review comments
- Use V3 register offsets
Changes in v4:
- Use qmp_usb_offsets for register space access
Changes in v3:
- Fix hex captitalization
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order

---
 drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)

drivers/phy/qualcomm/phy-qcom-qmp-usb.c +82 -0

index a49711c..77041dd 100644
@@ -139,6 +139,88 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 };
 
+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+       /* PLL and Loop filter settings */
+       QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+       QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+       /* SSC settings */
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+       QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+       QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+};
+
 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),

@@ -1558,6 +1640,14 @@ static const char * const qmp_phy_vreg_l[] = {
        "vdda-phy", "vdda-pll",
 };
 

drivers/phy/qualcomm/phy-qcom-qmp-usb.c static const char * const qmp_phy_vreg_l[] = { · line 1646

Quoted 4 lines

drivers/phy/qualcomm/phy-qcom-qmp-usb.c +4 -0

+static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
+       .serdes         = 0,
+       .pcs            = 0x800,
+       .pcs_usb        = 0,

No, pcs_usb is not 0.

Quoted 48 lines

drivers/phy/qualcomm/phy-qcom-qmp-usb.c +29 -1

+       .tx             = 0x200,
+       .rx             = 0x400,
+};
+
 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
        .serdes         = 0,
        .pcs            = 0x0200,

@@ -1586,6 +1676,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
        .regs                   = qmp_v3_usb3phy_regs_layout,
 };
 
+static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
+       .lanes                  = 1,
+
+       .offsets                = &qmp_usb_offsets_ipq9574,
+
+       .serdes_tbl             = ipq9574_usb3_serdes_tbl,
+       .serdes_tbl_num         = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
+       .tx_tbl                 = ipq9574_usb3_tx_tbl,
+       .tx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
+       .rx_tbl                 = ipq9574_usb3_rx_tbl,
+       .rx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
+       .pcs_tbl                = ipq9574_usb3_pcs_tbl,
+       .pcs_tbl_num            = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
+       .clk_list               = qmp_v4_phy_clk_l,
+       .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
+       .reset_list             = qcm2290_usb3phy_reset_l,
+       .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
+       .vreg_list              = qmp_phy_vreg_l,
+       .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
+       .regs                   = qmp_v3_usb3phy_regs_layout,
+};
+
 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
        .lanes                  = 1,
 

@@ -2589,6 +2701,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
                .compatible = "qcom,ipq8074-qmp-usb3-phy",
                .data = &ipq8074_usb3phy_cfg,
        }, {
+               .compatible = "qcom,ipq9574-qmp-usb3-phy",
+               .data = &ipq9574_usb3phy_cfg,
+       }, {
                .compatible = "qcom,msm8996-qmp-usb3-phy",
                .data = &msm8996_usb3phy_cfg,
        }, {
--

Quoted 2 lines

2.7.4

--
With best wishes
Dmitry

Quoted 121 lines · Dmitry Baryshkov

Quoted 119 lines · Varadarajan Narayanan

Updated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets.

Signed-off-by Praveenkumar I <[email protected]>

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v5:
- Fix additional review comments
- Use V3 register offsets
Changes in v4:
- Use qmp_usb_offsets for register space access
Changes in v3:
- Fix hex captitalization
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order

---
 drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)

drivers/phy/qualcomm/phy-qcom-qmp-usb.c +82 -0

index a49711c..77041dd 100644
@@ -139,6 +139,88 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 };
 
+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+       /* PLL and Loop filter settings */
+       QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+       QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+       /* SSC settings */
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+       QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+       QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+};
+
 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),

@@ -1558,6 +1640,14 @@ static const char * const qmp_phy_vreg_l[] = {
        "vdda-phy", "vdda-pll",
 };
 

Quoted 6 lines

drivers/phy/qualcomm/phy-qcom-qmp-usb.c static const char * const qmp_phy_vreg_l[] = { · line 1646

Quoted 4 lines

drivers/phy/qualcomm/phy-qcom-qmp-usb.c +4 -0

+static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
+       .serdes         = 0,
+       .pcs            = 0x800,
+       .pcs_usb        = 0,

No, pcs_usb is not 0.

Not sure I understand this comment.

Since IPQ9574 uses new style DT entries, pcs_usb_offset = 0 and that will not be used.

qmp->pcs_usb is used in qmp_usb_enable_autonomous_mode and qmp_usb_disable_autonomous_mode. If "qmp->pcs_usb == 0", those functions use the value of qmp->pcs (0x7d800) for pcs_usb.

The registers used in these functions are QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR & QPHY_PCS_AUTONOMOUS_MODE_CTRL

The offsets for the above registers as specified in qmp_v3_usb3phy_regs_layout is

        #define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL        0x0d8
        #define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR       0x0dc

qphy_{set|clr}bits called from qmp_usb_enable_autonomous_mode and qmp_usb_disable_autonomous_mode will use the offset 0x7d8d8 and 0x78d8c. This offset matches with the register offset document of the IPQ9574. So, felt setting pcs_usb to zero should be ok. Can you please clarify.

Thanks
Varada

Quoted 55 lines

Quoted 48 lines

drivers/phy/qualcomm/phy-qcom-qmp-usb.c +29 -1

+       .tx             = 0x200,
+       .rx             = 0x400,
+};
+
 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
        .serdes         = 0,
        .pcs            = 0x0200,

@@ -1586,6 +1676,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
        .regs                   = qmp_v3_usb3phy_regs_layout,
 };
 
+static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
+       .lanes                  = 1,
+
+       .offsets                = &qmp_usb_offsets_ipq9574,
+
+       .serdes_tbl             = ipq9574_usb3_serdes_tbl,
+       .serdes_tbl_num         = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
+       .tx_tbl                 = ipq9574_usb3_tx_tbl,
+       .tx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
+       .rx_tbl                 = ipq9574_usb3_rx_tbl,
+       .rx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
+       .pcs_tbl                = ipq9574_usb3_pcs_tbl,
+       .pcs_tbl_num            = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
+       .clk_list               = qmp_v4_phy_clk_l,
+       .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
+       .reset_list             = qcm2290_usb3phy_reset_l,
+       .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
+       .vreg_list              = qmp_phy_vreg_l,
+       .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
+       .regs                   = qmp_v3_usb3phy_regs_layout,
+};
+
 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
        .lanes                  = 1,
 

@@ -2589,6 +2701,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
                .compatible = "qcom,ipq8074-qmp-usb3-phy",
                .data = &ipq8074_usb3phy_cfg,
        }, {
+               .compatible = "qcom,ipq9574-qmp-usb3-phy",
+               .data = &ipq9574_usb3phy_cfg,
+       }, {
                .compatible = "qcom,msm8996-qmp-usb3-phy",
                .data = &msm8996_usb3phy_cfg,
        }, {
--

Quoted 2 lines

2.7.4

--
With best wishes
Dmitry

Quoted 132 lines · Varadarajan Narayanan

Quoted 121 lines · Dmitry Baryshkov

Quoted 119 lines · Varadarajan Narayanan

Updated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets.

Signed-off-by Praveenkumar I <[email protected]>

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v5:
- Fix additional review comments
- Use V3 register offsets
Changes in v4:
- Use qmp_usb_offsets for register space access
Changes in v3:
- Fix hex captitalization
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order

---
 drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)

drivers/phy/qualcomm/phy-qcom-qmp-usb.c +82 -0

index a49711c..77041dd 100644
@@ -139,6 +139,88 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 };
 
+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+       /* PLL and Loop filter settings */
+       QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
+       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+       QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+       /* SSC settings */
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
+       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+       QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+       QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+       QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+};
+
 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),

@@ -1558,6 +1640,14 @@ static const char * const qmp_phy_vreg_l[] = {
        "vdda-phy", "vdda-pll",
 };
 

Quoted 6 lines

drivers/phy/qualcomm/phy-qcom-qmp-usb.c static const char * const qmp_phy_vreg_l[] = { · line 1646

Quoted 4 lines

drivers/phy/qualcomm/phy-qcom-qmp-usb.c +4 -0

+static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
+       .serdes         = 0,
+       .pcs            = 0x800,
+       .pcs_usb        = 0,

No, pcs_usb is not 0.

Not sure I understand this comment.

Quoted 6 lines

Since IPQ9574 uses new style DT entries, pcs_usb_offset = 0 and that will not be used.

qmp->pcs_usb is used in qmp_usb_enable_autonomous_mode and qmp_usb_disable_autonomous_mode. If "qmp->pcs_usb == 0", those functions use the value of qmp->pcs (0x7d800) for pcs_usb.

So, you mixed qmp->pcs_usb and offsets->pcs_usb here. They are not equal.

Quoted 6 lines

The registers used in these functions are QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR & QPHY_PCS_AUTONOMOUS_MODE_CTRL

The offsets for the above registers as specified in qmp_v3_usb3phy_regs_layout is

Quoted 8 lines

        #define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL        0x0d8
        #define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR       0x0dc

qphy_{set|clr}bits called from qmp_usb_enable_autonomous_mode and qmp_usb_disable_autonomous_mode will use the offset 0x7d8d8 and 0x78d8c. This offset matches with the register offset document of the IPQ9574. So, felt setting pcs_usb to zero should be ok. Can you please clarify.

And this tells you what pcs_usb offset is.

Quoted 60 lines

Thanks
Varada

Quoted 55 lines

Quoted 48 lines

drivers/phy/qualcomm/phy-qcom-qmp-usb.c +29 -1

+       .tx             = 0x200,
+       .rx             = 0x400,
+};
+
 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
        .serdes         = 0,
        .pcs            = 0x0200,

@@ -1586,6 +1676,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
        .regs                   = qmp_v3_usb3phy_regs_layout,
 };
 
+static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
+       .lanes                  = 1,
+
+       .offsets                = &qmp_usb_offsets_ipq9574,
+
+       .serdes_tbl             = ipq9574_usb3_serdes_tbl,
+       .serdes_tbl_num         = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
+       .tx_tbl                 = ipq9574_usb3_tx_tbl,
+       .tx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
+       .rx_tbl                 = ipq9574_usb3_rx_tbl,
+       .rx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
+       .pcs_tbl                = ipq9574_usb3_pcs_tbl,
+       .pcs_tbl_num            = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
+       .clk_list               = qmp_v4_phy_clk_l,
+       .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
+       .reset_list             = qcm2290_usb3phy_reset_l,
+       .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
+       .vreg_list              = qmp_phy_vreg_l,
+       .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
+       .regs                   = qmp_v3_usb3phy_regs_layout,
+};
+
 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
        .lanes                  = 1,
 

@@ -2589,6 +2701,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
                .compatible = "qcom,ipq8074-qmp-usb3-phy",
                .data = &ipq8074_usb3phy_cfg,
        }, {
+               .compatible = "qcom,ipq9574-qmp-usb3-phy",
+               .data = &ipq9574_usb3phy_cfg,
+       }, {
                .compatible = "qcom,msm8996-qmp-usb3-phy",
                .data = &msm8996_usb3phy_cfg,
        }, {
--

Quoted 2 lines

2.7.4

--
With best wishes
Dmitry

--
With best wishes
Dmitry

Add USB phy and controller related nodes

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v5:
- Fix additional comments
- Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
- 'make dtbs_check' giving the following messages since ipq9574 doesn't have power domains. Hope this is ok

/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml

Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issues

Changes in v3:
- Insert the nodes at proper location

Changes in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by make dtbs_check
- Remove NOC related clocks (to be added with proper interconnect support)

Signed-off-by Varadarajan Narayanan <[email protected]>

---
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 120 ++++++++++++++++++++++++++++++++++
 1 file changed, 120 insertions(+)

arch/arm64/boot/dts/qcom/ipq9574.dtsi +36 -0

index 2bb4053..8fa9e1a 100644
@@ -186,6 +186,33 @@
                method = "smc";
        };
 
+       reg_usb_3p3: s3300 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "usb-phy-vdd-dummy";
+       };
+
+       reg_usb_1p8: s1800 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "usb-phy-pll-dummy";
+       };
+
+       reg_usb_0p925: s0925 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <925000>;
+               regulator-max-microvolt = <925000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "usb-phy-dummy";
+       };
+
        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;

@@ -215,6 +242,52 @@
                #size-cells = <1>;
                ranges = <0 0 0 0xffffffff>;
 
+               qusb_phy_0: phy@7b000 {
+                       compatible = "qcom,ipq9574-qusb2-phy";
+                       reg = <0x0007b000 0x180>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&xo_board_clk>;
+                       clock-names = "cfg_ahb",
+                                     "ref";

arch/arm64/boot/dts/qcom/ipq9574.dtsi +74 -1

+                       compatible = "qcom,ipq9574-qmp-usb3-phy";
+                       reg = <0x0007d000 0xa00>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_AUX_CLK>,
+                                <&xo_board_clk>,
+                                <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&gcc GCC_USB0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "ref",
+                                     "com_aux",
+                                     "pipe";
+
+                       resets = <&gcc GCC_USB0_PHY_BCR>,
+                                <&gcc GCC_USB3PHY_0_PHY_BCR>;
+                       reset-names = "phy",
+                                     "phy_phy";
+
+                       vdda-pll-supply = <&reg_usb_1p8>;
+                       vdda-phy-supply = <&reg_usb_0p925>;
+
+                       status = "disabled";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "usb0_pipe_clk";
+               };
+
                pcie0_phy: phy@84000 {
                        compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
                        reg = <0x00084000 0x1bc>; /* Serdes PLL */

@@ -436,6 +509,53 @@
                        status = "disabled";
                };
 
+               usb3: usb@8a00000 {
+                       compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
+                       reg = <0x08af8800 0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       clocks = <&gcc GCC_SNOC_USB_CLK>,
+                                <&gcc GCC_ANOC_USB_AXI_CLK>,
+                                <&gcc GCC_USB0_MASTER_CLK>,
+                                <&gcc GCC_USB0_SLEEP_CLK>,
+                                <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+                       clock-names = "sys_noc_axi",
+                                     "anoc_axi",
+                                     "master",
+                                     "sleep",
+                                     "mock_utmi";
+
+                       assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+                                         <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+                       assigned-clock-rates = <200000000>,
+                                              <24000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event";
+
+                       resets = <&gcc GCC_USB_BCR>;
+                       status = "disabled";
+
+                       dwc_0: usb@8a00000 {
+                               compatible = "snps,dwc3";
+                               reg = <0x8a00000 0xcd00>;
+                               clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+                               clock-names = "ref";
+                               interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                               phys = <&qusb_phy_0>, <&ssphy_0>;
+                               phy-names = "usb2-phy", "usb3-phy";
+                               tx-fifo-resize;
+                               snps,is-utmi-l1-suspend;
+                               snps,hird-threshold = /bits/ 8 <0x0>;
+                               snps,dis_u2_susphy_quirk;
+                               snps,dis_u3_susphy_quirk;
+                               dr_mode = "host";
+                       };
+               };
+
                intc: interrupt-controller@b000000 {
                        compatible = "qcom,msm-qgic2";
                        reg = <0x0b000000 0x1000>,  /* GICD */
--

2.7.4

Quoted 11 lines · Varadarajan Narayanan

Add USB phy and controller related nodes

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v5:
- Fix additional comments
- Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
- 'make dtbs_check' giving the following messages since ipq9574 doesn't have power domains. Hope this is ok

Quoted 4 lines

                /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
                From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
                /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
                From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml

No, I think it is not.

Quoted 69 lines

Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issues

Changes in v3:
- Insert the nodes at proper location

Changes in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by make dtbs_check
- Remove NOC related clocks (to be added with proper interconnect support)

Signed-off-by Varadarajan Narayanan <[email protected]>

---
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 120 ++++++++++++++++++++++++++++++++++
 1 file changed, 120 insertions(+)

arch/arm64/boot/dts/qcom/ipq9574.dtsi +36 -0

index 2bb4053..8fa9e1a 100644
@@ -186,6 +186,33 @@
                method = "smc";
        };
 
+       reg_usb_3p3: s3300 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "usb-phy-vdd-dummy";
+       };
+
+       reg_usb_1p8: s1800 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "usb-phy-pll-dummy";
+       };
+
+       reg_usb_0p925: s0925 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <925000>;
+               regulator-max-microvolt = <925000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "usb-phy-dummy";
+       };
+
        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;

@@ -215,6 +242,52 @@
                #size-cells = <1>;
                ranges = <0 0 0 0xffffffff>;
 
+               qusb_phy_0: phy@7b000 {
+                       compatible = "qcom,ipq9574-qusb2-phy";
+                       reg = <0x0007b000 0x180>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&xo_board_clk>;
+                       clock-names = "cfg_ahb",
+                                     "ref";

arch/arm64/boot/dts/qcom/ipq9574.dtsi line 263

Quoted 10 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi +10 -0

+
+                       vdd-supply = <&reg_usb_0p925>;
+                       vdda-pll-supply = <&reg_usb_1p8>;
+                       vdda-phy-dpdm-supply = <&reg_usb_3p3>;
+
+                       resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+                       status = "disabled";
+               };
+
+               ssphy_0: phy@7d000 {

Nit: usually the label usb_0_qmpphy

Quoted 85 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi +74 -1

+                       compatible = "qcom,ipq9574-qmp-usb3-phy";
+                       reg = <0x0007d000 0xa00>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_AUX_CLK>,
+                                <&xo_board_clk>,
+                                <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&gcc GCC_USB0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "ref",
+                                     "com_aux",
+                                     "pipe";
+
+                       resets = <&gcc GCC_USB0_PHY_BCR>,
+                                <&gcc GCC_USB3PHY_0_PHY_BCR>;
+                       reset-names = "phy",
+                                     "phy_phy";
+
+                       vdda-pll-supply = <&reg_usb_1p8>;
+                       vdda-phy-supply = <&reg_usb_0p925>;
+
+                       status = "disabled";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "usb0_pipe_clk";
+               };
+
                pcie0_phy: phy@84000 {
                        compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
                        reg = <0x00084000 0x1bc>; /* Serdes PLL */

@@ -436,6 +509,53 @@
                        status = "disabled";
                };
 
+               usb3: usb@8a00000 {
+                       compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
+                       reg = <0x08af8800 0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       clocks = <&gcc GCC_SNOC_USB_CLK>,
+                                <&gcc GCC_ANOC_USB_AXI_CLK>,
+                                <&gcc GCC_USB0_MASTER_CLK>,
+                                <&gcc GCC_USB0_SLEEP_CLK>,
+                                <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+                       clock-names = "sys_noc_axi",
+                                     "anoc_axi",
+                                     "master",
+                                     "sleep",
+                                     "mock_utmi";
+
+                       assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+                                         <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+                       assigned-clock-rates = <200000000>,
+                                              <24000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event";
+
+                       resets = <&gcc GCC_USB_BCR>;
+                       status = "disabled";
+
+                       dwc_0: usb@8a00000 {
+                               compatible = "snps,dwc3";
+                               reg = <0x8a00000 0xcd00>;
+                               clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+                               clock-names = "ref";
+                               interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                               phys = <&qusb_phy_0>, <&ssphy_0>;
+                               phy-names = "usb2-phy", "usb3-phy";
+                               tx-fifo-resize;
+                               snps,is-utmi-l1-suspend;
+                               snps,hird-threshold = /bits/ 8 <0x0>;
+                               snps,dis_u2_susphy_quirk;
+                               snps,dis_u3_susphy_quirk;
+                               dr_mode = "host";
+                       };
+               };
+
                intc: interrupt-controller@b000000 {
                        compatible = "qcom,msm-qgic2";
                        reg = <0x0b000000 0x1000>,  /* GICD */
--

Quoted 2 lines

2.7.4

--
With best wishes
Dmitry

Quoted 13 lines · Dmitry Baryshkov

Quoted 11 lines · Varadarajan Narayanan

Add USB phy and controller related nodes

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v5:
- Fix additional comments
- Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
- 'make dtbs_check' giving the following messages since ipq9574 doesn't have power domains. Hope this is ok

Quoted 6 lines

Quoted 4 lines

                /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
                From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
                /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
                From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml

No, I think it is not.

There are no GDSCs in IPQ9574. Can you suggest how to proceed.

Quoted 4 lines

Quoted 1 line

+ ssphy_0: phy@7d000 {

Nit: usually the label usb_0_qmpphy

Quoted 11 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi line 274

Quoted 11 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi +11 -0

+                       compatible = "qcom,ipq9574-qmp-usb3-phy";
+                       reg = <0x0007d000 0xa00>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_AUX_CLK>,
+                                <&xo_board_clk>,
+                                <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&gcc GCC_USB0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "ref",
+                                     "com_aux",

Quoted 7 lines

Quoted 7 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi +7 -0

+                                     "pipe";
+
+                       resets = <&gcc GCC_USB0_PHY_BCR>,
+                                <&gcc GCC_USB3PHY_0_PHY_BCR>;
+                       reset-names = "phy",
+                                     "phy_phy";
+

Quoted 8 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi line 289

Quoted 8 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi +8 -0

+                       vdda-pll-supply = <&reg_usb_1p8>;
+                       vdda-phy-supply = <&reg_usb_0p925>;
+
+                       status = "disabled";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "usb0_pipe_clk";
+               };

Quoted 14 lines · Varadarajan Narayanan

Quoted 13 lines · Dmitry Baryshkov

Quoted 11 lines · Varadarajan Narayanan

Add USB phy and controller related nodes

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v5:
- Fix additional comments
- Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
- 'make dtbs_check' giving the following messages since ipq9574 doesn't have power domains. Hope this is ok

Quoted 8 lines

Quoted 6 lines

Quoted 4 lines

                /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
                From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
                /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
                From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml

No, I think it is not.

There are no GDSCs in IPQ9574. Can you suggest how to proceed.

You need to update the binding and either make the power domains property optional in the binding or dependent on the SoC.

Quoted 4 lines

Quoted 4 lines

Quoted 1 line

+ ssphy_0: phy@7d000 {

Nit: usually the label usb_0_qmpphy

Quoted 11 lines

Quoted 11 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi line 274

Quoted 11 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi +11 -0

+                       compatible = "qcom,ipq9574-qmp-usb3-phy";
+                       reg = <0x0007d000 0xa00>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_AUX_CLK>,
+                                <&xo_board_clk>,
+                                <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&gcc GCC_USB0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "ref",
+                                     "com_aux",

This is not the right name for this clock so you need to update the binding first.

Please be more careful.

Quoted 16 lines

Quoted 16 lines

Quoted 6 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi +5 -0

+                                     "pipe";
+
+                       resets = <&gcc GCC_USB0_PHY_BCR>,
+                                <&gcc GCC_USB3PHY_0_PHY_BCR>;
+                       reset-names = "phy",

arch/arm64/boot/dts/qcom/ipq9574.dtsi line 289

Quoted 10 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi +10 -0

+                                     "phy_phy";
+
+                       vdda-pll-supply = <&reg_usb_1p8>;
+                       vdda-phy-supply = <&reg_usb_0p925>;
+
+                       status = "disabled";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "usb0_pipe_clk";
+               };

Johan

Quoted 16 lines · Johan Hovold

Quoted 15 lines

Quoted 15 lines

Quoted 1 line

+ ssphy_0: phy@7d000 {

Nit: usually the label usb_0_qmpphy

Quoted 11 lines

arch/arm64/boot/dts/qcom/ipq9574.dtsi +11 -0

+                       compatible = "qcom,ipq9574-qmp-usb3-phy";
+                       reg = <0x0007d000 0xa00>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_AUX_CLK>,
+                                <&xo_board_clk>,
+                                <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&gcc GCC_USB0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "ref",
+                                     "com_aux",

Quoted 4 lines

This is not the right name for this clock so you need to update the binding first.

Please be more careful.

Thanks for your feedback. Have posted v6 with the above corrections.