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Add Sipeed Lichee Pi 4A RISC-V board support

PATCH Superseded Jisheng Zhang 9 participants 30 messages May 18, 2023 – May 30, 2023

Subsystems (6)
Device tree bindings RISC-V irqchip drivers Clocksource, clockevent drivers +2 more subsystems

v2 of 3 Superseded Latest is v3 →

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Jisheng Zhang

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#0 lore raw

v2 cover Add Sipeed Lichee Pi 4A RISC-V board support

Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board.

Support basic uart/gpio/dmac drivers, so supports booting to a basic shell.

FWICT, one issue I'm not sure is the cpu reset dt-binding: IIUC, the secondary CPUs in T-HEAD SMP capable platforms need some special handling. The first one is to write the warm reset entry to entry register. The second one is write a SoC specific control value to a SoC specific control reg. The last one is to clone some CSRs for secondary CPUs to ensure these CSRs' values are the same as the main boot CPU. This DT node is mainly used by opensbi firmware. Any suggestion about this reset dt-binding is appreciated!

Thanks

Since v1:
- add missing plic, clint, th1520 itself dt-bindings
- use c900-plic
- s/light/th1520
- add dt-binding for T-HEAD CPU reset
- enable ARCH_THEAD in defconfig
- fix all dtbs_check error/warning except the CPU RESET, see above.

Jisheng Zhang (9):
dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC
dt-bindings: timer: Add T-HEAD TH1520 clint
dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
dt-binding: riscv: add T-HEAD CPU reset
riscv: Add the T-HEAD SoC family Kconfig option
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: defconfig: enable T-HEAD SoC

 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../bindings/riscv/thead,cpu-reset.yaml       |  69 +++
 .../devicetree/bindings/riscv/thead.yaml      |  29 ++
 .../bindings/timer/sifive,clint.yaml          |   1 +
 MAINTAINERS                                   |   6 +
 arch/riscv/Kconfig.socs                       |   6 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/thead/Makefile            |   2 +
 .../dts/thead/th1520-lichee-module-4a.dtsi    |  38 ++
 .../boot/dts/thead/th1520-lichee-pi-4a.dts    |  32 ++
 arch/riscv/boot/dts/thead/th1520.dtsi         | 451 ++++++++++++++++++
 arch/riscv/configs/defconfig                  |   1 +
 12 files changed, 637 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
 create mode 100644 arch/riscv/boot/dts/thead/Makefile
 create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
 create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
 create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
Signature · 1 line
2.40.0
author
#1 lore raw

PATCH v2 1/9 dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC

Add compatible string for T-HEAD TH1520 plic.

Signed-off-by Jisheng Zhang <[email protected]>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +1 -0
index f75736a061af..0fa9b862e4a5 100644
@@ -65,6 +65,7 @@ properties:
       - items:
           - enum:
               - allwinner,sun20i-d1-plic
+              - thead,th1520-plic
           - const: thead,c900-plic
       - items:
           - const: sifive,plic-1.0.0
Signature · 1 line
2.40.0
maintainer Reviewed-by on v2 1/9
#3 lore raw

Re: [PATCH v2 1/9] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC

In reply to Jisheng Zhang
Reviewed-by Guo Ren <[email protected]>
Quoted 23 lines · Jisheng Zhang

Add compatible string for T-HEAD TH1520 plic.

Signed-off-by Jisheng Zhang <[email protected]>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +1 -1
index f75736a061af..0fa9b862e4a5 100644
@@ -65,6 +65,7 @@ properties:
       - items:
           - enum:
               - allwinner,sun20i-d1-plic
+              - thead,th1520-plic
           - const: thead,c900-plic
       - items:
           - const: sifive,plic-1.0.0
--

2.40.0

Signature · 7 lines
Best Regards
 Guo Ren

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author
#4 lore raw

PATCH v2 2/9 dt-bindings: timer: Add T-HEAD TH1520 clint

In reply to Jisheng Zhang

Add compatible string for the T-HEAD TH1520 clint.

Signed-off-by Jisheng Zhang <[email protected]>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/timer/sifive,clint.yaml +1 -0
index 94bef9424df1..388d3385d7eb 100644
@@ -37,6 +37,7 @@ properties:
       - items:
           - enum:
               - allwinner,sun20i-d1-clint
+              - thead,th1520-clint
           - const: thead,c900-clint
       - items:
           - const: sifive,clint0
Signature · 1 line
2.40.0
author
#6 lore raw

PATCH v2 3/9 dt-bindings: riscv: Add T-HEAD TH1520 board compatibles

In reply to Jisheng Zhang

Several SoMs and boards are available that feature the T-HEAD TH1520 SoC. Document the compatible strings.

Signed-off-by Jisheng Zhang <[email protected]>
---
 .../devicetree/bindings/riscv/thead.yaml      | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
Documentation/devicetree/bindings/riscv/thead.yaml new file +29 -0
new file mode 100644
index 000000000000..e62f6821372e
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/thead.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD SoC-based boards
+
+maintainers:
+  - Jisheng Zhang <[email protected]>
+
+description:
+  T-HEAD SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A
+        items:
+          - enum:
+              - sipeed,lichee-pi-4a
+          - const: sipeed,lichee-module-4a
+          - const: thead,th1520
+
+additionalProperties: true
+
+...
Signature · 1 line
2.40.0
#7 lore raw

Re: [PATCH v2 3/9] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles

Quoted 30 lines · Jisheng Zhang

Several SoMs and boards are available that feature the T-HEAD TH1520 SoC. Document the compatible strings.

Signed-off-by Jisheng Zhang <[email protected]>
---
 .../devicetree/bindings/riscv/thead.yaml      | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
Documentation/devicetree/bindings/riscv/thead.yaml new file +15 -0
new file mode 100644
index 000000000000..e62f6821372e
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/thead.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD SoC-based boards
+
+maintainers:
+  - Jisheng Zhang <[email protected]>
+
+description:
+  T-HEAD SoC-based boards
+
+properties:

Documentation/devicetree/bindings/riscv/thead.yaml line 25

Quoted 10 lines
Documentation/devicetree/bindings/riscv/thead.yaml new file +10 -0
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A
+        items:
+          - enum:
+              - sipeed,lichee-pi-4a
+          - const: sipeed,lichee-module-4a
+          - const: thead,th1520

Same here re: other SoMs I guess. Probably more interest in creating them here though!

I heard on the grapevine that the boards people have now are perhaps not the same as the design that they're going to ship in the main production run?
Do you know if there is a more detailed part number for the boards, just in case there are some software-visible changes?

Thanks,
Conor.

#8 lore raw

Re: [PATCH v2 3/9] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles

Quoted 50 lines · 在 2023-05-18星期四的 20:40 +0100，Conor Dooley写道：
Quoted 39 lines · Jisheng Zhang

Several SoMs and boards are available that feature the T-HEAD TH1520
SoC. Document the compatible strings.

Signed-off-by Jisheng Zhang <[email protected]>

---
 .../devicetree/bindings/riscv/thead.yaml      | 29
+++++++++++++++++++

 1 file changed, 29 insertions(+)

 create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml

Documentation/devicetree/bindings/riscv/thead.yaml new file +20 -0
new file mode 100644
index 000000000000..e62f6821372e
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/thead.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD SoC-based boards
+
+maintainers:
+  - Jisheng Zhang <[email protected]>
+
+description:
+  T-HEAD SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Sipeed Lichee Pi 4A board for the Sipeed
Quoted 6 lines

Lichee Module 4A
+        items:
+          - enum:
+              - sipeed,lichee-pi-4a
+          - const: sipeed,lichee-module-4a
+          - const: thead,th1520

Same here re: other SoMs I guess. Probably more interest in creating them here though!

Quoted 5 lines

I heard on the grapevine that the boards people have now are perhaps not
the same as the design that they're going to ship in the main production
run?

There really was an early EVB that is not public, but the EVB is called LM4A EVB instead of LP4A.

The Lichee Pi 4A board here is the production run one.

Quoted 6 lines

Do you know if there is a more detailed part number for the boards, just
in case there are some software-visible changes?

Thanks,
Conor.

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author
#9 lore raw

PATCH v2 4/9 dt-binding: riscv: add T-HEAD CPU reset

In reply to Jisheng Zhang

The secondary CPUs in T-HEAD SMP capable platforms need some special handling. The first one is to write the warm reset entry to entry register. The second one is write a SoC specific control value to a SoC specific control reg. The last one is to clone some CSRs for secondary CPUs to ensure these CSRs' values are the same as the main boot CPU. This DT node is mainly used by opensbi firmware.

Signed-off-by Jisheng Zhang <[email protected]>
---
 .../bindings/riscv/thead,cpu-reset.yaml       | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +69 -0
new file mode 100644
index 000000000000..ba8c87583b6b
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD cpu reset controller
+
+maintainers:
+  - Jisheng Zhang <[email protected]>
+
+description: |
+  The secondary CPUs in T-HEAD SMP capable platforms need some special
+  handling. The first one is to write the warm reset entry to entry
+  register. The second one is write a SoC specific control value to
+  a SoC specific control reg. The last one is to clone some CSRs for
+  secondary CPUs to ensure these CSRs' values are the same as the
+  main boot CPU.
+
+properties:
+  $nodename:
+    pattern: "^cpurst"
+
+  compatible:
+    oneOf:
+      - description: CPU reset on T-HEAD TH1520 SoC
+        items:
+          - const: thead,reset-th1520
+
+  entry-reg:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description: |
+      The entry reg address.
+
+  entry-cnt:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The entry reg count.
+
+  control-reg:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The control reg address.
+
+  control-val:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The value to be set into the control reg.
+
+  csr-copy:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      The CSR registers to be cloned during CPU warm reset.
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    cpurst: cpurst@ffff019050 {
+      compatible = "thead,reset-th1520";
+      entry-reg = <0xff 0xff019050>;
+      entry-cnt = <4>;
+      control-reg = <0xff 0xff015004>;
+      control-val = <0x1c>;
+      csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+    };
Signature · 7 lines
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maintainer
#10 lore raw

Re: [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset

Quoted 7 lines · Jisheng Zhang

The secondary CPUs in T-HEAD SMP capable platforms need some special handling. The first one is to write the warm reset entry to entry register. The second one is write a SoC specific control value to a SoC specific control reg. The last one is to clone some CSRs for secondary CPUs to ensure these CSRs' values are the same as the main boot CPU. This DT node is mainly used by opensbi firmware.

Quoted 6 lines
Signed-off-by Jisheng Zhang <[email protected]>
---
 .../bindings/riscv/thead,cpu-reset.yaml       | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dts:18.35-25.11: Warning (unit_address_vs_reg): /example-0/cpurst@ffff019050: node has a unit name, but no reg or ranges property /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dtb: cpurst@ffff019050: control-reg:0: [255, 4278276100] is too long
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]

The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.

#11 lore raw

Re: [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset

In reply to Jisheng Zhang

Hey Jisheng,

Quoted 27 lines · Jisheng Zhang

The secondary CPUs in T-HEAD SMP capable platforms need some special handling. The first one is to write the warm reset entry to entry register. The second one is write a SoC specific control value to a SoC specific control reg. The last one is to clone some CSRs for secondary CPUs to ensure these CSRs' values are the same as the main boot CPU. This DT node is mainly used by opensbi firmware.

Signed-off-by Jisheng Zhang <[email protected]>
---
 .../bindings/riscv/thead,cpu-reset.yaml       | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +8 -0
new file mode 100644
index 000000000000..ba8c87583b6b
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD cpu reset controller
+

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 18

Quoted 10 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +10 -0
+maintainers:
+  - Jisheng Zhang <[email protected]>
+
+description: |
+  The secondary CPUs in T-HEAD SMP capable platforms need some special
+  handling. The first one is to write the warm reset entry to entry
+  register. The second one is write a SoC specific control value to
+  a SoC specific control reg. The last one is to clone some CSRs for
+  secondary CPUs to ensure these CSRs' values are the same as the
+  main boot CPU.

Okay..

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 22

Quoted 4 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +4 -0
+
+properties:
+  $nodename:
+    pattern: "^cpurst"

Firstly, why the nodename enforcement? We have a compatible, so we should be okay, no?

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 28

Quoted 6 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +6 -0
+
+  compatible:
+    oneOf:
+      - description: CPU reset on T-HEAD TH1520 SoC
+        items:
+          - const: thead,reset-th1520

You've only got one thing here, you don't need the oneOf. Also, s/reset-th1520/th1520-reset/ please - although I do not know if "reset" is the right word here. Do we know what the IP block is called in the TRM/T-Head docs? Perhaps Guo Ren does if not.

Quoted 14 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +14 -0
+  entry-reg:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description: |
+      The entry reg address.
+
+  entry-cnt:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The entry reg count.
+
+  control-reg:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The control reg address.

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 53

Quoted 10 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +10 -0
+
+  control-val:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The value to be set into the control reg.
+
+  csr-copy:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      The CSR registers to be cloned during CPU warm reset.

All of these values set on a per-soc basis, right?
If so, I don't think they should be in here at all since you should be able to figure out the offsets from the base & the values to write based on the compatible string alone, no?

Putting register values into the DT is always "suspect"!

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 62

Quoted 8 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +8 -0
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    cpurst: cpurst@ffff019050 {

               ^^^^^^^^^^^^^^^^^

This is also "suspect" and implies that "entry reg" should just be a normal "reg" property.

Quoted 10 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +7 -0
+      compatible = "thead,reset-th1520";
+      entry-reg = <0xff 0xff019050>;
+      entry-cnt = <4>;
+      control-reg = <0xff 0xff015004>;
+      control-val = <0x1c>;
+      csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+    };
Signature · 1 line
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maintainer
#12 lore raw

Re: [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset

Quoted 44 lines · Conor Dooley

Hey Jisheng,

Quoted 27 lines · Jisheng Zhang

The secondary CPUs in T-HEAD SMP capable platforms need some special handling. The first one is to write the warm reset entry to entry register. The second one is write a SoC specific control value to a SoC specific control reg. The last one is to clone some CSRs for secondary CPUs to ensure these CSRs' values are the same as the main boot CPU. This DT node is mainly used by opensbi firmware.

Signed-off-by Jisheng Zhang <[email protected]>
---
 .../bindings/riscv/thead,cpu-reset.yaml       | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +8 -0
new file mode 100644
index 000000000000..ba8c87583b6b
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD cpu reset controller
+

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 18

Quoted 10 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +10 -0
+maintainers:
+  - Jisheng Zhang <[email protected]>
+
+description: |
+  The secondary CPUs in T-HEAD SMP capable platforms need some special
+  handling. The first one is to write the warm reset entry to entry
+  register. The second one is write a SoC specific control value to
+  a SoC specific control reg. The last one is to clone some CSRs for
+  secondary CPUs to ensure these CSRs' values are the same as the
+  main boot CPU.

Okay..

Quoted 7 lines

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 22

Quoted 4 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +4 -0
+
+properties:
+  $nodename:
+    pattern: "^cpurst"

Firstly, why the nodename enforcement? We have a compatible, so we should be okay, no?

Yes, it needn't.

Quoted 8 lines

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 28

Quoted 7 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +6 -0
+
+  compatible:
+    oneOf:
+      - description: CPU reset on T-HEAD TH1520 SoC
+        items:
+          - const: thead,reset-th1520
Quoted 4 lines

You've only got one thing here, you don't need the oneOf. Also, s/reset-th1520/th1520-reset/ please - although I do not know if "reset" is the right word here. Do we know what the IP block is called in the TRM/T-Head docs? Perhaps Guo Ren does if not.

It's called CPU reset controller; every core has reset_ctrl & reset_entry signals; Soc just gathers them into some regs. For th1520, we have 4 reset_entries registers and 1 reset_ctrl register. Fu Wei would give out more details about it.

Quoted 13 lines

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 41

Quoted 13 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +12 -0
+  entry-reg:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description: |
+      The entry reg address.
+
+  entry-cn
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The entry reg count.
+
+  control-reg:
+    $ref: /schemas/types.yaml#/definitions/uint32

It should be uint64.

Quoted 6 lines
Quoted 6 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +6 -0
+    description: |
+      The control reg address.
+
+  control-val:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
Quoted 8 lines

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 53

Quoted 6 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +6 -0
+      The value to be set into the control reg.
+
+  csr-copy:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      The CSR registers to be cloned during CPU warm reset.

All of these values set on a per-soc basis, right?

Yes

Quoted 3 lines

If so, I don't think they should be in here at all since you should be able to figure out the offsets from the base & the values to write based on the compatible string alone, no?

The driver works with all T-HEAD CPUs, not only for th1520. Some vendors may have their own custom CSRs, so the csr-copy feature is flexible enough to adjust in dts. As far as I can tell, hardware teams typically prefer to focus on the firmware binary rather than setting up the software compiling environment.

Quoted 2 lines

Putting register values into the DT is always "suspect"!

It's not register values, it's register offset/ CSR number.

Quoted 10 lines

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 62

Quoted 9 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +8 -0
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    cpurst: cpurst@ffff019050 {

               ^^^^^^^^^^^^^^^^^
Quoted 2 lines

This is also "suspect" and implies that "entry reg" should just be a normal "reg" property.

Yes, but we needn't reg, here. It should be:

cpurst {

Thx for debugging.

Quoted 12 lines
Quoted 12 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +7 -1
+      compatible = "thead,reset-th1520";
+      entry-reg = <0xff 0xff019050>;
+      entry-cnt = <4>;
+      control-reg = <0xff 0xff015004>;
+      control-val = <0x1c>;
+      csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+    };
--

2.40.0

Signature · 2 lines
Best Regards
 Guo Ren
#13 lore raw

Re: [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset

Hey,

Quoted 47 lines · Guo Ren
Quoted 46 lines · Conor Dooley
Quoted 44 lines · Jisheng Zhang

The secondary CPUs in T-HEAD SMP capable platforms need some special handling. The first one is to write the warm reset entry to entry register. The second one is write a SoC specific control value to a SoC specific control reg. The last one is to clone some CSRs for secondary CPUs to ensure these CSRs' values are the same as the main boot CPU. This DT node is mainly used by opensbi firmware.

Signed-off-by Jisheng Zhang <[email protected]>
---
 .../bindings/riscv/thead,cpu-reset.yaml       | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +24 -0
new file mode 100644
index 000000000000..ba8c87583b6b
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD cpu reset controller
+
+maintainers:
+  - Jisheng Zhang <[email protected]>
+
+description: |
+  The secondary CPUs in T-HEAD SMP capable platforms need some special
+  handling. The first one is to write the warm reset entry to entry
+  register. The second one is write a SoC specific control value to
+  a SoC specific control reg. The last one is to clone some CSRs for
+  secondary CPUs to ensure these CSRs' values are the same as the
+  main boot CPU.
 
+
+  compatible:
+    oneOf:
+      - description: CPU reset on T-HEAD TH1520 SoC
+        items:
+          - const: thead,reset-th1520
Quoted 8 lines
Quoted 4 lines

You've only got one thing here, you don't need the oneOf. Also, s/reset-th1520/th1520-reset/ please - although I do not know if "reset" is the right word here. Do we know what the IP block is called in the TRM/T-Head docs? Perhaps Guo Ren does if not.

It's called CPU reset controller; every core has reset_ctrl & reset_entry signals; Soc just gathers them into some regs. For th1520, we have 4 reset_entries registers and 1 reset_ctrl register. Fu Wei would give out more details about it.

Okay, thanks. Sounds like this SoC will have multiple reset controllers then, since there is likely one for the peripherals too? thead,th1520-cpu-reset seems like a good idea to me?

Quoted 29 lines
Quoted 4 lines
Quoted 4 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +4 -0
+  entry-reg:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description: |
+      The entry reg address.
Quoted 8 lines

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 41

Quoted 8 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +8 -0
+
+  entry-cn
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The entry reg count.
+
+  control-reg:
+    $ref: /schemas/types.yaml#/definitions/uint32

It should be uint64.

Quoted 6 lines
Quoted 6 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +6 -0
+    description: |
+      The control reg address.
+
+  control-val:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
Quoted 8 lines

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 53

Quoted 6 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +6 -0
+      The value to be set into the control reg.
+
+  csr-copy:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      The CSR registers to be cloned during CPU warm reset.

All of these values set on a per-soc basis, right?

Yes

Quoted 8 lines
Quoted 3 lines

If so, I don't think they should be in here at all since you should be able to figure out the offsets from the base & the values to write based on the compatible string alone, no?

The driver works with all T-HEAD CPUs, not only for th1520. Some vendors may have their own custom CSRs, so the csr-copy feature is flexible enough to adjust in dts. As far as I can tell, hardware teams typically prefer to focus on the firmware binary rather than setting up the software compiling environment.

In this case "firmware" means opensbi, since that's where Jisheng mentioned in their cover that they intended using this.

Quoted 2 lines
Quoted 1 line

Putting register values into the DT is always "suspect"!

It's not register values, it's register offset/ CSR number.

So "control-val" is not a value? "The value to be set into the control reg" makes it sound oddly like one!!

My point I guess is that this entry could be written like

reset-controller@ffff019050 {
compatible = "thead,th1520-cpu-reset";
reg = <0xff 0xff019050 0xfoo 0xbar>, <0xff 0xff015004 0xfoo 0xbar>;
};

or even:

reset-controller@ffff019050 {
compatible = "thead,th1520-cpu-reset";
reg = <0xff 0xff019050 0xfoo 0xbar>, <0xff 0xff015004 0xfoo 0xbar>; reg-names = "entry", "control";
};

And csr-copy, entry-cn and control-val can be derived from the compatible string given you've said they are set on a per-soc basis.

Quoted 11 lines
Quoted 11 lines

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 62

Quoted 8 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +8 -0
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    cpurst: cpurst@ffff019050 {

               ^^^^^^^^^^^^^^^^^

This is also "suspect" and implies that "entry reg" should just be a normal "reg" property.

Quoted 3 lines

Yes, but we needn't reg, here. It should be:

cpurst {

I don't think it should! Firstly, "cpurst" is not a generic node name, but I also don't agree that "control-reg" and "entry-reg" should not just be 2 reg entries.

Cheers,
Conor.

_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv

maintainer
#14 lore raw

Re: [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset

Quoted 96 lines · Conor Dooley

Hey,

Quoted 47 lines · Guo Ren
Quoted 46 lines · Conor Dooley
Quoted 44 lines · Jisheng Zhang

The secondary CPUs in T-HEAD SMP capable platforms need some special handling. The first one is to write the warm reset entry to entry register. The second one is write a SoC specific control value to a SoC specific control reg. The last one is to clone some CSRs for secondary CPUs to ensure these CSRs' values are the same as the main boot CPU. This DT node is mainly used by opensbi firmware.

Signed-off-by Jisheng Zhang <[email protected]>
---
 .../bindings/riscv/thead,cpu-reset.yaml       | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +24 -0
new file mode 100644
index 000000000000..ba8c87583b6b
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD cpu reset controller
+
+maintainers:
+  - Jisheng Zhang <[email protected]>
+
+description: |
+  The secondary CPUs in T-HEAD SMP capable platforms need some special
+  handling. The first one is to write the warm reset entry to entry
+  register. The second one is write a SoC specific control value to
+  a SoC specific control reg. The last one is to clone some CSRs for
+  secondary CPUs to ensure these CSRs' values are the same as the
+  main boot CPU.
 
+
+  compatible:
+    oneOf:
+      - description: CPU reset on T-HEAD TH1520 SoC
+        items:
+          - const: thead,reset-th1520
Quoted 8 lines
Quoted 4 lines

You've only got one thing here, you don't need the oneOf. Also, s/reset-th1520/th1520-reset/ please - although I do not know if "reset" is the right word here. Do we know what the IP block is called in the TRM/T-Head docs? Perhaps Guo Ren does if not.

It's called CPU reset controller; every core has reset_ctrl & reset_entry signals; Soc just gathers them into some regs. For th1520, we have 4 reset_entries registers and 1 reset_ctrl register. Fu Wei would give out more details about it.

Okay, thanks. Sounds like this SoC will have multiple reset controllers then, since there is likely one for the peripherals too? thead,th1520-cpu-reset seems like a good idea to me?

Quoted 32 lines
Quoted 4 lines
Quoted 4 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +4 -0
+  entry-reg:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description: |
+      The entry reg address.
Quoted 8 lines

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 41

Quoted 8 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +8 -0
+
+  entry-cn
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The entry reg count.
+
+  control-reg:
+    $ref: /schemas/types.yaml#/definitions/uint32

It should be uint64.

Quoted 6 lines
Quoted 6 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +6 -0
+    description: |
+      The control reg address.
+
+  control-val:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
Quoted 8 lines

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 53

Quoted 6 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +6 -0
+      The value to be set into the control reg.
+
+  csr-copy:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      The CSR registers to be cloned during CPU warm reset.

All of these values set on a per-soc basis, right?

Yes

Quoted 3 lines

If so, I don't think they should be in here at all since you should be able to figure out the offsets from the base & the values to write based on the compatible string alone, no?

Quoted 8 lines
Quoted 5 lines

The driver works with all T-HEAD CPUs, not only for th1520. Some vendors may have their own custom CSRs, so the csr-copy feature is flexible enough to adjust in dts. As far as I can tell, hardware teams typically prefer to focus on the firmware binary rather than setting up the software compiling environment.

In this case "firmware" means opensbi, since that's where Jisheng mentioned in their cover that they intended using this.

Yes, firmware -> opensbi. The hardware guys just modify dtb without recompiling the opensbi.

Quoted 14 lines
Quoted 3 lines
Quoted 2 lines

Putting register values into the DT is always "suspect"!

It's not register values, it's register offset/ CSR number.

So "control-val" is not a value? "The value to be set into the control reg" makes it sound oddly like one!!

My point I guess is that this entry could be written like

reset-controller@ffff019050 {
compatible = "thead,th1520-cpu-reset";
reg = <0xff 0xff019050 0xfoo 0xbar>, <0xff 0xff015004 0xfoo 0xbar>;
};

Quoted 7 lines

or even:

reset-controller@ffff019050 {
compatible = "thead,th1520-cpu-reset";
reg = <0xff 0xff019050 0xfoo 0xbar>, <0xff 0xff015004 0xfoo 0xbar>; reg-names = "entry", "control";
};

Better naming, I agree with you at this point.
But, we have to make changes to the current opensbi implementation to match your advice.

Quoted 15 lines

And csr-copy, entry-cn and control-val can be derived from the compatible string given you've said they are set on a per-soc basis.

Quoted 11 lines
Quoted 11 lines

Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml line 62

Quoted 8 lines
Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file +8 -0
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    cpurst: cpurst@ffff019050 {

               ^^^^^^^^^^^^^^^^^

This is also "suspect" and implies that "entry reg" should just be a normal "reg" property.

Quoted 5 lines
Quoted 3 lines

Yes, but we needn't reg, here. It should be:

cpurst {

I don't think it should! Firstly, "cpurst" is not a generic node name,

Yes, reset-controller is better.

Quoted 2 lines

but I also don't agree that "control-reg" and "entry-reg" should not just be 2 reg entries.

Yes, Yes. You've said.

Quoted 3 lines

Cheers,
Conor.

Signature · 2 lines
Best Regards
 Guo Ren
#15 lore raw

Re: [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset

In reply to Jisheng Zhang
Quoted 7 lines · Jisheng Zhang

The secondary CPUs in T-HEAD SMP capable platforms need some special handling. The first one is to write the warm reset entry to entry register. The second one is write a SoC specific control value to a SoC specific control reg. The last one is to clone some CSRs for secondary CPUs to ensure these CSRs' values are the same as the main boot CPU. This DT node is mainly used by opensbi firmware.

Quoted 6 lines
Signed-off-by Jisheng Zhang <[email protected]>
---
 .../bindings/riscv/thead,cpu-reset.yaml       | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dts:18.35-25.11: Warning (unit_address_vs_reg): /example-0/cpurst@ffff019050: node has a unit name, but no reg or ranges property /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dtb: cpurst@ffff019050: control-reg:0: [255, 4278276100] is too long
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1783487

This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:

pip3 install dtschema --upgrade

Please check and re-submit.

_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv

author
#16 lore raw

PATCH v2 5/9 riscv: Add the T-HEAD SoC family Kconfig option

In reply to Jisheng Zhang

The first SoC in the T-HEAD series is TH1520, containing quad T-HEAD C910 cores.

Signed-off-by Jisheng Zhang <[email protected]>
---
 arch/riscv/Kconfig.socs | 6 ++++++
 1 file changed, 6 insertions(+)
arch/riscv/Kconfig.socs +6 -0
index 1cf69f958f10..ce10a38dff37 100644
@@ -41,6 +41,12 @@ config ARCH_SUNXI
 	  This enables support for Allwinner sun20i platform hardware,
 	  including boards based on the D1 and D1s SoCs.
 
+config ARCH_THEAD
+	bool "T-HEAD RISC-V SoCs"
+	select ERRATA_THEAD
+	help
+	  This enables support for the RISC-V based T-HEAD SoCs.
+
 config ARCH_VIRT
 	def_bool SOC_VIRT
Signature · 7 lines
2.40.0


_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by on v2 5/9
#17 lore raw

Re: [PATCH v2 5/9] riscv: Add the T-HEAD SoC family Kconfig option

Quoted 3 lines · Jisheng Zhang

The first SoC in the T-HEAD series is TH1520, containing quad T-HEAD C910 cores.

Reviewed-by Conor Dooley <[email protected]>

Thanks,
Conor.

author
#18 lore raw

PATCH v2 6/9 riscv: dts: add initial T-HEAD TH1520 SoC device tree

In reply to Jisheng Zhang

Add initial device tree for the TH1520 RISC-V SoC by T-HEAD.

Signed-off-by Jisheng Zhang <[email protected]>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 451 ++++++++++++++++++++++++++
 1 file changed, 451 insertions(+)
 create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
arch/riscv/boot/dts/thead/th1520.dtsi new file +451 -0
new file mode 100644
index 000000000000..60754d7c6319
@@ -0,0 +1,451 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ * Copyright (C) 2023 Jisheng Zhang <[email protected]>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "thead,th1520";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+
+		c910_0: cpu@0 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <0>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		c910_1: cpu@1 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <1>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		c910_2: cpu@2 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <2>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		c910_3: cpu@3 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <3>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&c910_0>;
+				};
+
+				core1 {
+					cpu = <&c910_1>;
+				};
+
+				core2 {
+					cpu = <&c910_2>;
+				};
+
+				core3 {
+					cpu = <&c910_3>;
+				};
+			};
+		};
+
+		l2_cache: l2-cache {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+	};
+
+	osc: oscillator {
+		compatible = "fixed-clock";
+		clock-output-names = "osc_24m";
+		#clock-cells = <0>;
+	};
+
+	osc_32k: 32k-oscillator {
+		compatible = "fixed-clock";
+		clock-output-names = "osc_32k";
+		#clock-cells = <0>;
+	};
+
+	apb_clk: apb-clk-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "apb_clk";
+		#clock-cells = <0>;
+	};
+
+	uart_sclk: uart-sclk-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "uart_sclk";
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpurst: cpurst {
+			compatible = "thead,reset-th1520";
+			entry-reg = <0xff 0xff019050>;
+			entry-cnt = <4>;
+			control-reg = <0xff 0xff015004>;
+			control-val = <0x1c>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+		};
+
+		plic: interrupt-controller@ffd8000000 {
+			compatible = "thead,th1520-plic", "thead,c900-plic";
+			reg = <0xff 0xd8000000 0x0 0x01000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			riscv,ndev = <240>;
+		};
+
+		clint: timer@ffdc000000 {
+			compatible = "thead,th1520-clint", "thead,c900-clint";
+			reg = <0xff 0xdc000000 0x0 0x00010000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>;
+		};
+
+		uart0: serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x4000>;
+			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart1: serial@ffe7f00000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7f00000 0x0 0x4000>;
+			interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@ffe7f04000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7f04000 0x0 0x4000>;
+			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portc: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio3: gpio@ffe7f38000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f38000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portd: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portb: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		uart2: serial@ffec010000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xec010000 0x0 0x4000>;
+			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		dmac0: dma-controller@ffefc00000 {
+			compatible = "snps,axi-dma-1.01a";
+			reg = <0xff 0xefc00000 0x0 0x1000>;
+			interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&apb_clk>, <&apb_clk>;
+			clock-names = "core-clk", "cfgr-clk";
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			snps,block-size = <65536 65536 65536 65536>;
+			snps,priority = <0 1 2 3>;
+			snps,dma-masters = <1>;
+			snps,data-width = <4>;
+			snps,axi-max-burst-len = <16>;
+                        status = "disabled";
+		};
+
+		timer0: timer@ffefc32000 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32000 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer1: timer@ffefc32014 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32014 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer2: timer@ffefc32028 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32028 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer3: timer@ffefc3203c {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc3203c 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart4: serial@fff7f08000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xf7f08000 0x0 0x4000>;
+			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart5: serial@fff7f0c000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xf7f0c000 0x0 0x4000>;
+			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		timer4: timer@ffffc33000 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33000 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer5: timer@ffffc33014 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33014 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer6: timer@ffffc33028 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33028 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer7: timer@ffffc3303c {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc3303c 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		ao_gpio0: gpio@fffff41000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xfff41000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			porte: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		ao_gpio1: gpio@fffff52000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xfff52000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portf: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
Signature · 7 lines
2.40.0


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#19 lore raw

Re: [PATCH v2 6/9] riscv: dts: add initial T-HEAD TH1520 SoC device tree

Quoted 9 lines · Jisheng Zhang
arch/riscv/boot/dts/thead/th1520.dtsi new file +9 -0
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&c910_0>;
+				};
+
+				core1 {
+					cpu = <&c910_1>;
+				};

arch/riscv/boot/dts/thead/th1520.dtsi line 121

Quoted 10 lines
arch/riscv/boot/dts/thead/th1520.dtsi new file +10 -0
+
+				core2 {
+					cpu = <&c910_2>;
+				};
+
+				core3 {
+					cpu = <&c910_3>;
+				};
+			};
+		};

We actually don't need to add these anymore, I fixed our topology detection :) No harm to keep it though!

arch/riscv/boot/dts/thead/th1520.dtsi line 171

Quoted 8 lines
arch/riscv/boot/dts/thead/th1520.dtsi new file +8 -0
+		cpurst: cpurst {
+			compatible = "thead,reset-th1520";
+			entry-reg = <0xff 0xff019050>;
+			entry-cnt = <4>;
+			control-reg = <0xff 0xff015004>;
+			control-val = <0x1c>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+		};

I figure this will be no surprise to you:
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dtb: soc: cpurst: {'compatible': ['thead,reset-th1520'], 'entry-reg': [[1099494953040]], 'entry-cnt': [[4]], 'control-reg': [[255, 4278276100]], 'control-val': [[28]], 'csr-copy': [[2035, 1984, 1985, 1986, 1987, 1989, 1996]]} should not be valid under {'type': 'object'} arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dtb: cpurst: control-reg:0: [255, 4278276100] is too long

Quoted 4 lines
arch/riscv/boot/dts/thead/th1520.dtsi new file +4 -0
+		dmac0: dma-controller@ffefc00000 {
+			compatible = "snps,axi-dma-1.01a";
+			reg = <0xff 0xefc00000 0x0 0x1000>;
+			interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;

arch/riscv/boot/dts/thead/th1520.dtsi line 320

Quoted 10 lines
arch/riscv/boot/dts/thead/th1520.dtsi new file +10 -0
+			clocks = <&apb_clk>, <&apb_clk>;
+			clock-names = "core-clk", "cfgr-clk";
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			snps,block-size = <65536 65536 65536 65536>;
+			snps,priority = <0 1 2 3>;
+			snps,dma-masters = <1>;
+			snps,data-width = <4>;
+			snps,axi-max-burst-len = <16>;
+                        status = "disabled";

    ^^^^^^^^^^^^^^^^^^^^^^^

These are spaces :(

Review

Quoted 1 line
(quoted diff) +1 -0
+		};

Cheers,
Conor.

#20 lore raw

Re: [PATCH v2 6/9] riscv: dts: add initial T-HEAD TH1520 SoC device tree

In reply to Jisheng Zhang

Hi Jisheng:

Quoted 14 lines · Jisheng Zhang

Add initial device tree for the TH1520 RISC-V SoC by T-HEAD.

Signed-off-by Jisheng Zhang <[email protected]>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 451 ++++++++++++++++++++++++++
 1 file changed, 451 insertions(+)
 create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
arch/riscv/boot/dts/thead/th1520.dtsi new file +0 -0
new file mode 100644
index 000000000000..60754d7c6319

arch/riscv/boot/dts/thead/th1520.dtsi line 3

Quoted 3 lines
arch/riscv/boot/dts/thead/th1520.dtsi new file +3 -0
@@ -0,0 +1,451 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.

I think you are trying to copy this from vendor's kernel? would it be more proper/accurate to set as
T-HEAD Semiconductor Co., LTD

Quoted 184 lines
arch/riscv/boot/dts/thead/th1520.dtsi new file +184 -0
+ * Copyright (C) 2023 Jisheng Zhang <[email protected]>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "thead,th1520";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+
+		c910_0: cpu@0 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <0>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		c910_1: cpu@1 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <1>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		c910_2: cpu@2 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <2>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		c910_3: cpu@3 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <3>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&c910_0>;
+				};
+
+				core1 {
+					cpu = <&c910_1>;
+				};
+
+				core2 {
+					cpu = <&c910_2>;
+				};
+
+				core3 {
+					cpu = <&c910_3>;
+				};
+			};
+		};
+
+		l2_cache: l2-cache {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+	};
+
+	osc: oscillator {
+		compatible = "fixed-clock";
+		clock-output-names = "osc_24m";
+		#clock-cells = <0>;
+	};
+
+	osc_32k: 32k-oscillator {
+		compatible = "fixed-clock";
+		clock-output-names = "osc_32k";
+		#clock-cells = <0>;
+	};
+
+	apb_clk: apb-clk-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "apb_clk";
+		#clock-cells = <0>;
+	};
+
+	uart_sclk: uart-sclk-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "uart_sclk";
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpurst: cpurst {
+			compatible = "thead,reset-th1520";
+			entry-reg = <0xff 0xff019050>;
+			entry-cnt = <4>;
+			control-reg = <0xff 0xff015004>;
+			control-val = <0x1c>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+		};
+
+		plic: interrupt-controller@ffd8000000 {
+			compatible = "thead,th1520-plic", "thead,c900-plic";
+			reg = <0xff 0xd8000000 0x0 0x01000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			riscv,ndev = <240>;
+		};
+
+		clint: timer@ffdc000000 {
+			compatible = "thead,th1520-clint", "thead,c900-clint";

arch/riscv/boot/dts/thead/th1520.dtsi line 197

Quoted 10 lines
arch/riscv/boot/dts/thead/th1520.dtsi new file +10 -0
+			reg = <0xff 0xdc000000 0x0 0x00010000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>;
+		};
+
+		uart0: serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x4000>;

                                                     ~~~~~

probably you are writing this according to the address map?

from UART controller's perspective, it's valid reg range from 0x00 - 0xFF so I think limiting the address space to 0x100 would be more proper? less io space consumed, less page table needed?

Quoted 262 lines
arch/riscv/boot/dts/thead/th1520.dtsi new file +254 -0
+			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart1: serial@ffe7f00000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7f00000 0x0 0x4000>;
+			interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@ffe7f04000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7f04000 0x0 0x4000>;
+			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portc: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio3: gpio@ffe7f38000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f38000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portd: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portb: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		uart2: serial@ffec010000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xec010000 0x0 0x4000>;
+			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		dmac0: dma-controller@ffefc00000 {
+			compatible = "snps,axi-dma-1.01a";
+			reg = <0xff 0xefc00000 0x0 0x1000>;
+			interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&apb_clk>, <&apb_clk>;
+			clock-names = "core-clk", "cfgr-clk";
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			snps,block-size = <65536 65536 65536 65536>;
+			snps,priority = <0 1 2 3>;
+			snps,dma-masters = <1>;
+			snps,data-width = <4>;
+			snps,axi-max-burst-len = <16>;
+                        status = "disabled";
+		};
+
+		timer0: timer@ffefc32000 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32000 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer1: timer@ffefc32014 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32014 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer2: timer@ffefc32028 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32028 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer3: timer@ffefc3203c {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc3203c 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart4: serial@fff7f08000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xf7f08000 0x0 0x4000>;
+			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart5: serial@fff7f0c000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xf7f0c000 0x0 0x4000>;
+			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		timer4: timer@ffffc33000 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33000 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer5: timer@ffffc33014 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33014 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer6: timer@ffffc33028 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33028 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer7: timer@ffffc3303c {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc3303c 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		ao_gpio0: gpio@fffff41000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xfff41000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			porte: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		ao_gpio1: gpio@fffff52000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xfff52000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portf: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
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Signature · 3 lines
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
author
#21 lore raw

PATCH v2 7/9 riscv: dts: thead: add sipeed Lichee Pi 4A board device tree

In reply to Jisheng Zhang

Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board.

Support basic uart/gpio/dmac drivers, so supports booting to a basic shell.

Signed-off-by Jisheng Zhang <[email protected]>
---
 arch/riscv/boot/dts/Makefile                  |  1 +
 arch/riscv/boot/dts/thead/Makefile            |  2 +
 .../dts/thead/th1520-lichee-module-4a.dtsi    | 38 +++++++++++++++++++
 .../boot/dts/thead/th1520-lichee-pi-4a.dts    | 32 ++++++++++++++++
 4 files changed, 73 insertions(+)
 create mode 100644 arch/riscv/boot/dts/thead/Makefile
 create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
 create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
arch/riscv/boot/dts/Makefile +1 -0
index f0d9f89054f8..1e884868ccba 100644
@@ -2,6 +2,7 @@
 subdir-y += allwinner
 subdir-y += sifive
 subdir-y += starfive
+subdir-y += thead
 subdir-y += canaan
 subdir-y += microchip
 subdir-y += renesas
arch/riscv/boot/dts/thead/Makefile new file +2 -0
new file mode 100644
index 000000000000..e311fc9a5939
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi new file +38 -0
new file mode 100644
index 000000000000..4b0249ac710f
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <[email protected]>
+ */
+
+/dts-v1/;
+
+#include "th1520.dtsi"
+
+/ {
+	model = "Sipeed Lichee Module 4A";
+	compatible = "sipeed,lichee-module-4a", "thead,th1520";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x00000000 0x2 0x00000000>;
+	};
+};
+
+&osc {
+	clock-frequency = <24000000>;
+};
+
+&osc_32k {
+	clock-frequency = <32768>;
+};
+
+&apb_clk {
+	clock-frequency = <62500000>;
+};
+
+&uart_sclk {
+	clock-frequency = <100000000>;
+};
+
+&dmac0 {
+	status = "okay";
+};
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts new file +32 -0
new file mode 100644
index 000000000000..a1248b2ee3a3
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <[email protected]>
+ */
+
+#include "th1520-lichee-module-4a.dtsi"
+
+/ {
+	model = "Sipeed Lichee Pi 4A";
+	compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
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#22 lore raw

Re: [PATCH v2 7/9] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree

arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts line 10

Quoted 10 lines · Jisheng Zhang

Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board.

Support basic uart/gpio/dmac drivers, so supports booting to a basic shell.

Signed-off-by Jisheng Zhang <[email protected]>
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts new file +1 -0
+	compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";

This patch, modulo my comments elsewhere about the compatibles, seems fine.

author
#23 lore raw

PATCH v2 8/9 MAINTAINERS: add entry for T-HEAD RISC-V SoC

In reply to Jisheng Zhang

Currently, I would like to maintain the T-HEAD RISC-V SoC support.

Signed-off-by Jisheng Zhang <[email protected]>
---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)
MAINTAINERS +6 -0
index e0ad886d3163..6df20c65798a 100644
@@ -18162,6 +18162,12 @@ F:	drivers/perf/riscv_pmu.c
 F:	drivers/perf/riscv_pmu_legacy.c
 F:	drivers/perf/riscv_pmu_sbi.c
 
+RISC-V THEAD SoC SUPPORT
+M:	Jisheng Zhang <[email protected]>
+L:	[email protected]
+S:	Maintained
+F:	arch/riscv/boot/dts/thead/
+
 RNBD BLOCK DRIVERS
 M:	Md. Haris Iqbal <[email protected]>
 M:	Jack Wang <[email protected]>
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Acked-by on v2 8/9
#24 lore raw

Re: [PATCH v2 8/9] MAINTAINERS: add entry for T-HEAD RISC-V SoC

Quoted 3 lines · Jisheng Zhang

Currently, I would like to maintain the T-HEAD RISC-V SoC support.

Signed-off-by Jisheng Zhang <[email protected]>
Acked-by Conor Dooley <[email protected]>

Thanks,
Conor.

Quoted 24 lines
---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)
MAINTAINERS +6 -0
index e0ad886d3163..6df20c65798a 100644
@@ -18162,6 +18162,12 @@ F:	drivers/perf/riscv_pmu.c
 F:	drivers/perf/riscv_pmu_legacy.c
 F:	drivers/perf/riscv_pmu_sbi.c
 
+RISC-V THEAD SoC SUPPORT
+M:	Jisheng Zhang <[email protected]>
+L:	[email protected]
+S:	Maintained
+F:	arch/riscv/boot/dts/thead/
+
 RNBD BLOCK DRIVERS
 M:	Md. Haris Iqbal <[email protected]>
 M:	Jack Wang <[email protected]>
Signature · 1 line
2.40.0
author
#25 lore raw

PATCH v2 9/9 riscv: defconfig: enable T-HEAD SoC

In reply to Jisheng Zhang

Enable T-HEAD SoC config in defconfig to allow the default upstream kernel to boot on Sipeed Lichee Pi 4A board.

Signed-off-by Jisheng Zhang <[email protected]>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)
arch/riscv/configs/defconfig +1 -0
index d98d6e90b2b8..109e4b5b003c 100644
@@ -27,6 +27,7 @@ CONFIG_EXPERT=y
 CONFIG_PROFILING=y
 CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_THEAD=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
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Reviewed-by on v2 9/9
#26 lore raw

Re: [PATCH v2 9/9] riscv: defconfig: enable T-HEAD SoC

Quoted 2 lines · Jisheng Zhang

Enable T-HEAD SoC config in defconfig to allow the default upstream kernel to boot on Sipeed Lichee Pi 4A board.

Reviewed-by Conor Dooley <[email protected]>

Thanks,
Conor.

Quoted 21 lines
Signed-off-by Jisheng Zhang <[email protected]>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)
arch/riscv/configs/defconfig +1 -0
index d98d6e90b2b8..109e4b5b003c 100644
@@ -27,6 +27,7 @@ CONFIG_EXPERT=y
 CONFIG_PROFILING=y
 CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_THEAD=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
Signature · 1 line
2.40.0
maintainer Acked-by on v2 9/9
#27 lore raw

Re: [PATCH v2 9/9] riscv: defconfig: enable T-HEAD SoC

In reply to Jisheng Zhang
Quoted 13 lines · On Thu, 18 May 2023 11:45:41 PDT (-0700), [email protected] wrote:

Enable T-HEAD SoC config in defconfig to allow the default upstream kernel to boot on Sipeed Lichee Pi 4A board.

Signed-off-by Jisheng Zhang <[email protected]>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)
arch/riscv/configs/defconfig +0 -0
index d98d6e90b2b8..109e4b5b003c 100644

arch/riscv/configs/defconfig CONFIG_EXPERT=y · line 33

Quoted 7 lines
arch/riscv/configs/defconfig +1 -0
@@ -27,6 +27,7 @@ CONFIG_EXPERT=y
 CONFIG_PROFILING=y
 CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_THEAD=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
Acked-by Palmer Dabbelt <[email protected]>

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maintainer Acked-by
#28 lore raw

Re: [PATCH v2 9/9] riscv: defconfig: enable T-HEAD SoC

Acked-by Guo Ren <[email protected]>
Quoted 24 lines · Palmer Dabbelt
Quoted 13 lines · On Thu, 18 May 2023 11:45:41 PDT (-0700), [email protected] wrote:

Enable T-HEAD SoC config in defconfig to allow the default upstream kernel to boot on Sipeed Lichee Pi 4A board.

Signed-off-by Jisheng Zhang <[email protected]>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)
arch/riscv/configs/defconfig +0 -0
index d98d6e90b2b8..109e4b5b003c 100644

arch/riscv/configs/defconfig CONFIG_EXPERT=y · line 33

Quoted 7 lines
arch/riscv/configs/defconfig +1 -0
@@ -27,6 +27,7 @@ CONFIG_EXPERT=y
 CONFIG_PROFILING=y
 CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_THEAD=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
Acked-by Palmer Dabbelt <[email protected]>
Signature · 2 lines
Best Regards
 Guo Ren
#29 lore raw
In reply to Jisheng Zhang

Hi Jisheng

Quoted 18 lines · Jisheng Zhang

Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board.

Support basic uart/gpio/dmac drivers, so supports booting to a basic shell.

FWICT, one issue I'm not sure is the cpu reset dt-binding: IIUC, the secondary CPUs in T-HEAD SMP capable platforms need some special handling. The first one is to write the warm reset entry to entry register. The second one is write a SoC specific control value to a SoC specific control reg. The last one is to clone some CSRs for secondary CPUs to ensure these CSRs' values are the same as the main boot CPU. This DT node is mainly used by opensbi firmware. Any suggestion about this reset dt-binding is appreciated!

Thanks

Quoted 7 lines

Since v1:
- add missing plic, clint, th1520 itself dt-bindings
- use c900-plic
- s/light/th1520
- add dt-binding for T-HEAD CPU reset
- enable ARCH_THEAD in defconfig
- fix all dtbs_check error/warning except the CPU RESET, see above.

it would be nice to have a URL reference to v0
https://lore.kernel.org/all/[email protected]/

Quoted 40 lines

Jisheng Zhang (9):
dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC
dt-bindings: timer: Add T-HEAD TH1520 clint
dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
dt-binding: riscv: add T-HEAD CPU reset
riscv: Add the T-HEAD SoC family Kconfig option
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: defconfig: enable T-HEAD SoC

 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../bindings/riscv/thead,cpu-reset.yaml       |  69 +++
 .../devicetree/bindings/riscv/thead.yaml      |  29 ++
 .../bindings/timer/sifive,clint.yaml          |   1 +
 MAINTAINERS                                   |   6 +
 arch/riscv/Kconfig.socs                       |   6 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/thead/Makefile            |   2 +
 .../dts/thead/th1520-lichee-module-4a.dtsi    |  38 ++
 .../boot/dts/thead/th1520-lichee-pi-4a.dts    |  32 ++
 arch/riscv/boot/dts/thead/th1520.dtsi         | 451 ++++++++++++++++++
 arch/riscv/configs/defconfig                  |   1 +
 12 files changed, 637 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
 create mode 100644 arch/riscv/boot/dts/thead/Makefile
 create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
 create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
 create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
Signature · 7 lines
2.40.0


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Signature · 3 lines
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55