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Add initialization of clock for StarFive JH7110 SoC

PATCH Superseded William Qiu 2 participants 15 messages May 26, 2023 – Jun 1, 2023

Subsystems (4)

v1 of 6 Superseded Latest is v6 →

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#0 lore raw

cover Add initialization of clock for StarFive JH7110 SoC

Hi,

This patchset adds initial rudimentary support for the StarFive Quad SPI controller driver. And this driver will be used in StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB clocks changed from the default ON state to the default OFF state, so these clocks need to be enabled in the driver.At the same time, dts patch is added to this series.

The patch series is based on v6.4rc3.

William Qiu (3):
dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC

 .../bindings/spi/cdns,qspi-nor.yaml           | 15 +++++++--
 .../jh7110-starfive-visionfive-2.dtsi         | 32 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 18 +++++++++++
 drivers/spi/spi-cadence-quadspi.c             | 27 ++++++++++++++++
 4 files changed, 89 insertions(+), 3 deletions(-)

--
2.34.1

#1 lore raw

PATCH 1/3 dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC

The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Other platforms do not have this constraint.

---
 .../devicetree/bindings/spi/cdns,qspi-nor.yaml    | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +12 -3
index b310069762dd..737f1c162e01 100644
@@ -26,6 +26,15 @@ allOf:
             const: starfive,jh7110-qspi
     then:
       properties:
+        clocks:
+          maxItems: 3
+
+        clock-names:
+          items:
+            - const: qspi-ref
+            - const: qspi-ahb
+            - const: qspi-apb
+
         resets:
           minItems: 2
           maxItems: 3
@@ -38,6 +47,9 @@ allOf:
 
     else:
       properties:
+        clocks:
+          maxItems: 1
+
         resets:
           maxItems: 2
 
@@ -69,9 +81,6 @@ properties:
   interrupts:
     maxItems: 1
 
-  clocks:
-    maxItems: 1
-
   cdns,fifo-depth:
     description:
       Size of the data FIFO in words.
Signature · 1 line
2.34.1
maintainer
#2 lore raw

Re: [PATCH v1 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml allOf: · line 37

Quoted 11 lines · William Qiu

then:
properties:

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +9 -0
+        clocks:
+          maxItems: 3
+
+        clock-names:
+          items:
+            - const: qspi-ref
+            - const: qspi-ahb
+            - const: qspi-apb
+

Are these really the names that the clocks have in the IP? It seems weird that they'd include the IP name in there and not just be ref, ahb and apb.

#3 lore raw

Re: [PATCH v1 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC

Quoted 17 lines · Mark Brown

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml allOf: · line 37

Quoted 11 lines · William Qiu

then:
properties:

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +9 -0
+        clocks:
+          maxItems: 3
+
+        clock-names:
+          items:
+            - const: qspi-ref
+            - const: qspi-ahb
+            - const: qspi-apb
+

Are these really the names that the clocks have in the IP? It seems weird that they'd include the IP name in there and not just be ref, ahb and apb.

Hi Mark,

These three clocks are the internal clocks in the IP. The AHB
clock is the main system clock used to transfer data over the AHB bus between an external master and the QSPI controller. The APB clock is used to access the register map of the QSPI controller, perform controller and device configuration.service interrupts and control certain run time modes. The reference clock is used to serialize the data and drive the external SPI interface.

I'm going to change the names of these three clocks to hclk, pclk,
and ref_clk, as defined in the data book. What do you think?

Thanks for taking time to review this patch series and give useful
suggestions.

Best regards,
William

maintainer
#4 lore raw

Re: [PATCH v1 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC

Quoted 11 lines · William Qiu
Quoted 7 lines · Mark Brown

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml allOf: · line 36

Quoted 5 lines · William Qiu
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +5 -0
+        clock-names:
+          items:
+            - const: qspi-ref
+            - const: qspi-ahb
+            - const: qspi-apb

I'm going to change the names of these three clocks to hclk, pclk,
and ref_clk, as defined in the data book. What do you think?

That looks fine. ref, ahb and apb would also be fine, it's just the qspi- prefix that I was querying.

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#5 lore raw

Re: [PATCH v1 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC

Quoted 10 lines · Mark Brown
Quoted 8 lines · William Qiu
Quoted 7 lines · Mark Brown
Quoted 5 lines · William Qiu
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +5 -0
+        clock-names:
+          items:
+            - const: qspi-ref
+            - const: qspi-ahb
+            - const: qspi-apb
Quoted 5 lines
Quoted 2 lines

I'm going to change the names of these three clocks to hclk, pclk,
and ref_clk, as defined in the data book. What do you think?

That looks fine. ref, ahb and apb would also be fine, it's just the qspi- prefix that I was querying.

That's fine. I will fix it in next version.

Best regards,
William

#6 lore raw

PATCH 2/3 spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI

In reply to William Qiu

Add QSPI clock operation in device probe.

---
 drivers/spi/spi-cadence-quadspi.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
drivers/spi/spi-cadence-quadspi.c +27 -0
index 6ddb2dfc0f00..c6430fb3a0a4 100644
@@ -1624,6 +1624,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi)
 static int cqspi_probe(struct platform_device *pdev)
 {
 	const struct cqspi_driver_platdata *ddata;
+	struct clk *qspi_ahb, *qspi_apb;
 	struct reset_control *rstc, *rstc_ocp, *rstc_ref;
 	struct device *dev = &pdev->dev;
 	struct spi_master *master;
@@ -1715,6 +1716,32 @@ static int cqspi_probe(struct platform_device *pdev)
 	}
 
 	if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
+		qspi_ahb = devm_clk_get(dev, "qspi-ahb");
+		if (IS_ERR(qspi_ahb)) {
+			dev_err(dev, "Cannot claim QSPI_AHB clock.\n");
+			ret = PTR_ERR(qspi_ahb);
+			return ret;
+		}
+
+		ret = clk_prepare_enable(qspi_ahb);
+		if (ret) {
+			dev_err(dev, "Cannot enable QSPI AHB clock.\n");
+			goto probe_clk_failed;
+		}
+
+		qspi_apb = devm_clk_get(dev, "qspi-apb");
+		if (IS_ERR(qspi_apb)) {
+			dev_err(dev, "Cannot claim QSPI_APB clock.\n");
+			ret = PTR_ERR(qspi_apb);
+			return ret;
+		}
+
+		ret = clk_prepare_enable(qspi_apb);
+		if (ret) {
+			dev_err(dev, "Cannot enable QSPI APB clock.\n");
+			goto probe_clk_failed;
+		}
+
 		rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
 		if (IS_ERR(rstc_ref)) {
 			ret = PTR_ERR(rstc_ref);
Signature · 1 line
2.34.1
maintainer
#7 lore raw

Re: [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI

drivers/spi/spi-cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1730

Quoted 13 lines · William Qiu
drivers/spi/spi-cadence-quadspi.c +12 -0
 	if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
+		qspi_ahb = devm_clk_get(dev, "qspi-ahb");
+		if (IS_ERR(qspi_ahb)) {
+			dev_err(dev, "Cannot claim QSPI_AHB clock.\n");
+			ret = PTR_ERR(qspi_ahb);
+			return ret;
+		}
+
+		ret = clk_prepare_enable(qspi_ahb);
+		if (ret) {
+			dev_err(dev, "Cannot enable QSPI AHB clock.\n");
+			goto probe_clk_failed;
+		}

Nothing ever disables or unprepares this clock as far as I can tell? Perhaps also consider using the clk_bulk_ APIs.

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[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv

#8 lore raw

Re: [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI

Quoted 18 lines · Mark Brown

drivers/spi/spi-cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1730

Quoted 13 lines · William Qiu
drivers/spi/spi-cadence-quadspi.c +12 -0
 	if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
+		qspi_ahb = devm_clk_get(dev, "qspi-ahb");
+		if (IS_ERR(qspi_ahb)) {
+			dev_err(dev, "Cannot claim QSPI_AHB clock.\n");
+			ret = PTR_ERR(qspi_ahb);
+			return ret;
+		}
+
+		ret = clk_prepare_enable(qspi_ahb);
+		if (ret) {
+			dev_err(dev, "Cannot enable QSPI AHB clock.\n");
+			goto probe_clk_failed;
+		}

Nothing ever disables or unprepares this clock as far as I can tell? Perhaps also consider using the clk_bulk_ APIs.

I will add in next version.

Thanks for taking time to review this patch series and give useful suggestions.

Best regards,
William

#9 lore raw

Re: [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI

Quoted 22 lines · William Qiu
Quoted 18 lines · Mark Brown

drivers/spi/spi-cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1730

Quoted 13 lines · William Qiu
drivers/spi/spi-cadence-quadspi.c +12 -0
 	if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
+		qspi_ahb = devm_clk_get(dev, "qspi-ahb");
+		if (IS_ERR(qspi_ahb)) {
+			dev_err(dev, "Cannot claim QSPI_AHB clock.\n");
+			ret = PTR_ERR(qspi_ahb);
+			return ret;
+		}
+
+		ret = clk_prepare_enable(qspi_ahb);
+		if (ret) {
+			dev_err(dev, "Cannot enable QSPI AHB clock.\n");
+			goto probe_clk_failed;
+		}

Nothing ever disables or unprepares this clock as far as I can tell? Perhaps also consider using the clk_bulk_ APIs.

Quoted 7 lines

I will add in next version.

Thanks for taking time to review this patch series and give useful suggestions.

Best regards,
William

Hi Mark,

Now I want to replace the original devm_clk_get API in the
driver with devm_clk_bulk_get_all API, which can achieve compatibility, but it seems that it is not good for other ip with only one clock, so I want to ask about that can I replace it? Or define that inside jh7110?

Best regards,
William

_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv

maintainer
#10 lore raw

Re: [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI

Quoted 6 lines · William Qiu
Quoted 4 lines · William Qiu
Quoted 2 lines · Mark Brown

Nothing ever disables or unprepares this clock as far as I can tell? Perhaps also consider using the clk_bulk_ APIs.

Quoted 6 lines
Quoted 1 line

I will add in next version.

Now I want to replace the original devm_clk_get API in the
driver with devm_clk_bulk_get_all API, which can achieve compatibility, but it seems that it is not good for other ip with only one clock, so I want to ask about that can I replace it? Or define that inside jh7110?

You could always specify a different array of clocks depending on which compatible the driver sees, just like you'd conditionally request clocks individually.

_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv

#11 lore raw

Re: [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI

Quoted 9 lines · Mark Brown
Quoted 7 lines · William Qiu
Quoted 6 lines · William Qiu
Quoted 2 lines · Mark Brown

Nothing ever disables or unprepares this clock as far as I can tell? Perhaps also consider using the clk_bulk_ APIs.

I will add in next version.

Quoted 8 lines
Quoted 4 lines

Now I want to replace the original devm_clk_get API in the
driver with devm_clk_bulk_get_all API, which can achieve compatibility, but it seems that it is not good for other ip with only one clock, so I want to ask about that can I replace it? Or define that inside jh7110?

You could always specify a different array of clocks depending on which compatible the driver sees, just like you'd conditionally request clocks individually.

Hi Mark,

If specify a different array of clocks depending on which compatible
the driver sees, since there will also be clock operations in the suspend and resume interfaces, this can make the code look complicated.
My thoughts are as follows:
Modify the following code

1658 /* Obtain QSPI clock. */
1659 cqspi->clk = devm_clk_get(dev, NULL);
1660 if (IS_ERR(cqspi->clk)) {
1661 dev_err(dev, "Cannot claim QSPI clock.\n");
1662 ret = PTR_ERR(cqspi->clk);
1663 return ret;
1664 }

	as following:

	/* Obtain QSPI clock. */
	cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks);
	if (cqspi->num_clks < 0) {
		dev_err(dev, "Cannot claim QSPI clock: %u\n", cqspi->num_clks);
		return -EINVAL;
	}

	This way, the code will look simpler and clearer. How do you think

about it.

Best Regards,
William

maintainer
#12 lore raw

Re: [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI

Quoted 9 lines · William Qiu
Quoted 3 lines · Mark Brown

You could always specify a different array of clocks depending on which compatible the driver sees, just like you'd conditionally request clocks individually.

If specify a different array of clocks depending on which compatible
the driver sees, since there will also be clock operations in the suspend and resume interfaces, this can make the code look complicated.

If you store the clock count and array in the driver data that should be fairly simple I think.

Quoted 11 lines
	as following:

	/* Obtain QSPI clock. */
	cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks);
	if (cqspi->num_clks < 0) {
		dev_err(dev, "Cannot claim QSPI clock: %u\n", cqspi->num_clks);
		return -EINVAL;
	}

	This way, the code will look simpler and clearer. How do you think

about it.

I'm not clear how enable and disable would then work?

#13 lore raw

Re: [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI

Quoted 23 lines · Mark Brown
Quoted 9 lines · William Qiu
Quoted 3 lines · Mark Brown

You could always specify a different array of clocks depending on which compatible the driver sees, just like you'd conditionally request clocks individually.

If specify a different array of clocks depending on which compatible
the driver sees, since there will also be clock operations in the suspend and resume interfaces, this can make the code look complicated.

If you store the clock count and array in the driver data that should be fairly simple I think.

Quoted 8 lines
	as following:

	/* Obtain QSPI clock. */
	cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks);
	if (cqspi->num_clks < 0) {
		dev_err(dev, "Cannot claim QSPI clock: %u\n", cqspi->num_clks);
		return -EINVAL;
	}
Quoted 4 lines
Quoted 2 lines

This way, the code will look simpler and clearer. How do you think
about it.

I'm not clear how enable and disable would then work?

enable use this API:
clk_bulk_prepare_enable(dev->num_clks, dev->clks);

then disable:
clk_bulk_disable_unprepare(dev->num_clks, dev->clks);

But I'll first try specify a different array of clocks depending on which compatible the driver sees first.

Best regards,
William

#14 lore raw

PATCH 3/3 riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC

In reply to William Qiu

Add the quad spi controller node for the StarFive JH7110 SoC.

---
 .../jh7110-starfive-visionfive-2.dtsi         | 32 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 18 +++++++++++
 2 files changed, 50 insertions(+)
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +32 -0
index 2a6d81609284..22212c1150f9 100644
@@ -126,6 +126,38 @@ &i2c6 {
 	status = "okay";
 };
 
+&qspi {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nor_flash: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg=<0>;
+		cdns,read-delay = <5>;
+		spi-max-frequency = <12000000>;
+		cdns,tshsl-ns = <1>;
+		cdns,tsd2d-ns = <1>;
+		cdns,tchsh-ns = <1>;
+		cdns,tslch-ns = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			spl@0 {
+				reg = <0x0 0x20000>;
+			};
+			uboot@100000 {
+				reg = <0x100000 0x300000>;
+			};
+			data@f00000 {
+				reg = <0xf00000 0x100000>;
+			};
+		};
+	};
+};
+
 &sysgpio {
 	i2c0_pins: i2c0-0 {
 		i2c-pins {
arch/riscv/boot/dts/starfive/jh7110.dtsi +18 -0
index 4c5fdb905da8..6385443d011f 100644
@@ -440,6 +440,24 @@ i2c6: i2c@12060000 {
 			status = "disabled";
 		};
 
+		qspi: spi@13010000 {
+			compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
+			reg = <0x0 0x13010000 0x0 0x10000
+				0x0 0x21000000 0x0 0x400000>;
+			interrupts = <25>;
+			clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
+				 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
+				 <&syscrg JH7110_SYSCLK_QSPI_APB>;
+			clock-names = "qspi-ref", "qspi-ahb", "qspi-apb";
+			resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+				 <&syscrg JH7110_SYSRST_QSPI_AHB>,
+				 <&syscrg JH7110_SYSRST_QSPI_REF>;
+			reset-names = "qspi", "qspi-ocp", "rstc_ref";
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x0>;
+		};
+
 		syscrg: clock-controller@13020000 {
 			compatible = "starfive,jh7110-syscrg";
 			reg = <0x0 0x13020000 0x0 0x10000>;
Signature · 1 line
2.34.1