Add SPI module for StarFive JH7110 SoC

PATCH Superseded William Qiu 1 participant 7 messages Jul 4, 2023

Subsystems (5)

Device tree bindings RISC-V SPI StarFive devicetrees +1 more subsystems

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William Qiu

author

2023-07-04 09:19 UTC #0 lore raw

cover Add SPI module for StarFive JH7110 SoC

Hi,

This patchset adds initial rudimentary support for the StarFive SPI controller. And this driver will be used in StarFive's VisionFive 2 board. The first patch constrain minItems of clocks for JH7110 SPI and Patch 2 adds support for StarFive JH7110 SPI.

The patch series is based on v6.4rc7.

William Qiu (2):
dt-binding: spi: constrain minItems of clocks and clock-names
riscv: dts: starfive: Add spi node for JH7110 SoC

 .../devicetree/bindings/spi/spi-pl022.yaml    | 11 ++-
 .../jh7110-starfive-visionfive-2.dtsi         | 52 ++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 98 +++++++++++++++++++
 3 files changed, 158 insertions(+), 3 deletions(-)

--
2.34.1

William Qiu

author

2023-07-04 09:19 UTC #1 lore raw

PATCH 1/2 dt-binding: spi: constrain minItems of clocks and clock-names

The SPI controller only need apb_pclk clock to work properly on JH7110 SoC, so there add minItems whose value is equal to 1. Other platforms do not have this constraint.

Signed-off-by William Qiu <[email protected]>

---
 Documentation/devicetree/bindings/spi/spi-pl022.yaml | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

Documentation/devicetree/bindings/spi/spi-pl022.yaml +8 -3

index 91e540a92faf..42bb34c39971 100644
@@ -11,6 +11,7 @@ maintainers:
 
 allOf:
   - $ref: spi-controller.yaml#
+  - $ref: /schemas/arm/primecell.yaml#
 
 # We need a select here so we don't match all nodes with 'arm,primecell'
 select:

@@ -34,12 +35,16 @@ properties:
     maxItems: 1
 
   clocks:
+    minItems: 1
     maxItems: 2
 
   clock-names:
-    items:
-      - const: sspclk
-      - const: apb_pclk
+    oneOf:
+      - items:
+          - const: apb_pclk
+      - items:
+          - const: sspclk
+          - const: apb_pclk
 
   pl022,autosuspend-delay:
     description: delay in ms following transfer completion before the

Signature · 1 line

2.34.1

William Qiu

author

2023-07-04 09:19 UTC #2 lore raw

PATCH 2/2 riscv: dts: starfive: Add spi node for JH7110 SoC

In reply to William Qiu

Add spi node for JH7110 SoC.

Co-developed-by Xingyu Wu <[email protected]>

Signed-off-by William Qiu <[email protected]>

---
 .../jh7110-starfive-visionfive-2.dtsi         | 52 ++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 98 +++++++++++++++++++
 2 files changed, 150 insertions(+)

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +52 -0

index 2a6d81609284..a066d2e399c4 100644
@@ -126,6 +126,20 @@ &i2c6 {
 	status = "okay";
 };
 
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	status = "okay";
+
+	spi_dev0: spi@0 {
+		compatible = "st,m25p80";
+		pl022,com-mode = <1>;
+		spi-max-frequency = <10000000>;
+		reg = <0>;
+		status = "okay";
+	};
+};
+
 &sysgpio {
 	i2c0_pins: i2c0-0 {
 		i2c-pins {

@@ -183,6 +197,44 @@ GPOEN_SYS_I2C6_DATA,
 		};
 	};
 
+	spi0_pins: spi0-0 {
+		mosi-pins {
+			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+		};
+
+		miso-pins {
+			pinmux = <GPIOMUX(53, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_SYS_SPI0_RXD)>;
+			bias-pull-up;
+			input-enable;
+			input-schmitt-enable;
+		};
+
+		sck-pins {
+			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
+					      GPOEN_ENABLE,
+					      GPI_SYS_SPI0_CLK)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+		};
+
+		ss-pins {
+			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS,
+					      GPOEN_ENABLE,
+					      GPI_SYS_SPI0_FSS)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+		};
+	};
+
 	uart0_pins: uart0-0 {
 		tx-pins {
 			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,

arch/riscv/boot/dts/starfive/jh7110.dtsi +98 -0

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Signature · 1 line

2.34.1

William Qiu

author

2023-07-04 09:20 UTC #3 lore raw

v4 cover Add initialization of clock for StarFive JH7110 SoC

In reply to William Qiu

Hi,

This patchset adds initial rudimentary support for the StarFive Quad SPI controller driver. And this driver will be used in StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB clocks changed from the default ON state to the default OFF state, so these clocks need to be enabled in the driver.At the same time, dts patch is added to this series.

Changes v3->v4:
- Added minItems for clocks.
- Added clock names property.
- Fixed formatting issues.

Changes v2->v3:
- Rebaed to v6.4rc6.
- Renamed the clock names.
- Changed the variable definition type.

Changes v1->v2:
- Renamed the clock names.
- Specified a different array of clocks.
- Used clk_bulk_ APIs.

The patch series is based on v6.4rc6.

William Qiu (3):
dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC

 .../bindings/spi/cdns,qspi-nor.yaml           | 12 ++++++-
 .../jh7110-starfive-visionfive-2.dtsi         | 32 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 18 +++++++++++
 drivers/spi/spi-cadence-quadspi.c             | 20 ++++++++++++
 4 files changed, 81 insertions(+), 1 deletion(-)

--
2.34.1

William Qiu

author

2023-07-04 09:20 UTC #4 lore raw

PATCH v4 1/3 dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC

In reply to William Qiu

The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3.

Signed-off-by William Qiu <[email protected]>

Reviewed-by Hal Feng <[email protected]>

Reviewed-by Conor Dooley <[email protected]>

---
 .../devicetree/bindings/spi/cdns,qspi-nor.yaml       | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +11 -1

index b310069762dd..e048cf63215b 100644
@@ -70,7 +70,17 @@ properties:
     maxItems: 1
 
   clocks:
-    maxItems: 1
+    minItems: 1
+    maxItems: 3
+
+  clock-names:
+    oneOf:
+      - items:
+          - const: ref
+      - items:
+          - const: ref
+          - const: ahb
+          - const: apb
 
   cdns,fifo-depth:
     description:

Signature · 1 line

2.34.1

William Qiu

author

2023-07-04 09:20 UTC #5 lore raw

PATCH v4 2/3 spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI

In reply to William Qiu

Add QSPI clock operation in device probe.

Signed-off-by William Qiu <[email protected]>

Reviewed-by Hal Feng <[email protected]>

Reported-by kernel test robot <[email protected]>

Closes https://lore.kernel.org/oe-kbuild-all/[email protected]/ open here

Reported-by Julia Lawall <[email protected]>

Closes https://lore.kernel.org/r/[email protected]/ open here

---
 drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

drivers/spi/spi-cadence-quadspi.c +20 -0

index 6ddb2dfc0f00..8774f9aaff61 100644
@@ -63,6 +63,8 @@ struct cqspi_st {
 	struct platform_device	*pdev;
 	struct spi_master	*master;
 	struct clk		*clk;
+	struct clk_bulk_data	*clks;
+	int			num_clks;
 	unsigned int		sclk;
 
 	void __iomem		*iobase;

@@ -1715,6 +1717,16 @@ static int cqspi_probe(struct platform_device *pdev)
 	}
 
 	if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
+		cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks);
+		if (cqspi->num_clks < 0) {
+			dev_err(dev, "Cannot claim clock: %u\n", cqspi->num_clks);
+			return -EINVAL;
+		}
+
+		ret = clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
+		if (ret)
+			dev_err(dev, "Cannot enable clock clks\n");
+
 		rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
 		if (IS_ERR(rstc_ref)) {
 			ret = PTR_ERR(rstc_ref);

@@ -1816,6 +1828,9 @@ static void cqspi_remove(struct platform_device *pdev)
 
 	clk_disable_unprepare(cqspi->clk);
 
+	if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi"))
+		clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks);
+
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 }

@@ -1831,6 +1846,9 @@ static int cqspi_suspend(struct device *dev)
 
 	clk_disable_unprepare(cqspi->clk);
 
+	if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
+		clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks);
+
 	return ret;
 }

@@ -1840,6 +1858,8 @@ static int cqspi_resume(struct device *dev)
 	struct spi_master *master = dev_get_drvdata(dev);
 
 	clk_prepare_enable(cqspi->clk);
+	if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
+		clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
 	cqspi_wait_idle(cqspi);
 	cqspi_controller_init(cqspi);

Signature · 1 line

2.34.1

William Qiu

author

2023-07-04 09:20 UTC #6 lore raw

PATCH v4 3/3 riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC

In reply to William Qiu

Add the quad spi controller node for the StarFive JH7110 SoC.

Co-developed-by Ziv Xu <[email protected]>

Signed-off-by Ziv Xu <[email protected]>

Signed-off-by William Qiu <[email protected]>

Reviewed-by Hal Feng <[email protected]>

---
 .../jh7110-starfive-visionfive-2.dtsi         | 32 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 18 +++++++++++
 2 files changed, 50 insertions(+)

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +32 -0

index 2a6d81609284..983b683e2f27 100644
@@ -126,6 +126,38 @@ &i2c6 {
 	status = "okay";
 };
 
+&qspi {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nor_flash: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		cdns,read-delay = <5>;
+		spi-max-frequency = <12000000>;
+		cdns,tshsl-ns = <1>;
+		cdns,tsd2d-ns = <1>;
+		cdns,tchsh-ns = <1>;
+		cdns,tslch-ns = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			spl@0 {
+				reg = <0x0 0x20000>;
+			};
+			uboot@100000 {
+				reg = <0x100000 0x300000>;
+			};
+			data@f00000 {
+				reg = <0xf00000 0x100000>;
+			};
+		};
+	};
+};
+
 &sysgpio {
 	i2c0_pins: i2c0-0 {
 		i2c-pins {

arch/riscv/boot/dts/starfive/jh7110.dtsi +18 -0

index 4c5fdb905da8..fe33c5616565 100644
@@ -440,6 +440,24 @@ i2c6: i2c@12060000 {
 			status = "disabled";
 		};
 
+		qspi: spi@13010000 {
+			compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
+			reg = <0x0 0x13010000 0x0 0x10000>,
+			      <0x0 0x21000000 0x0 0x400000>;
+			interrupts = <25>;
+			clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
+				 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
+				 <&syscrg JH7110_SYSCLK_QSPI_APB>;
+			clock-names = "ref", "ahb", "apb";
+			resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+				 <&syscrg JH7110_SYSRST_QSPI_AHB>,
+				 <&syscrg JH7110_SYSRST_QSPI_REF>;
+			reset-names = "qspi", "qspi-ocp", "rstc_ref";
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x0>;
+		};
+
 		syscrg: clock-controller@13020000 {
 			compatible = "starfive,jh7110-syscrg";
 			reg = <0x0 0x13020000 0x0 0x10000>;

Signature · 1 line

2.34.1