target/riscv: add 'max' CPU type
v2 cover target/riscv: add 'max' CPU type
Hi,
This second version has smalls tweak in patch 6 that I found out missing while chatting with Conor in the v1 review.
Changes from v1:
- patch 6:
- enable RVG, RVJ and RVV in riscv_init_max_cpu_extensions()
- Added the resulting 'riscv,isa' DT in the commit message
- v1 link: https://lore.kernel.org/qemu-riscv/[email protected]/T/#t
Daniel Henrique Barboza (7):
target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] target/riscv/cpu.c: skip 'bool' check when filtering KVM props target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[] target/riscv/cpu.c: split non-ratified exts from
riscv_cpu_extensions[]
target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro target/riscv: add 'max' CPU type
avocado, risc-v: add opensbi tests for 'max' CPU
target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 109 +++++++++++++++++++++++++++------ tests/avocado/riscv_opensbi.py | 16 +++++ 3 files changed, 106 insertions(+), 20 deletions(-)
Signature · 1 line
2.41.0
PATCH v2 1/7 target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
We'll add a new CPU type that will enable a considerable amount of extensions. To make it easier for us we'll do a few cleanups in our existing riscv_cpu_extensions[] array.
Start by splitting all CPU non-boolean options from it. Create a new riscv_cpu_options[] array for them. Add all these properties in riscv_cpu_add_user_properties() as it is already being done today.
No functional changes made.
--- target/riscv/cpu.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-)
target/riscv/cpu.c +19 -8
@@ -1751,7 +1751,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)static Property riscv_cpu_extensions[] = {/* Defaults for standard extensions */ -DEFINE_PROP_UINT8 ("pmu-num" ,RISCVCPU , cfg.pmu_num,16 ),DEFINE_PROP_BOOL ("sscofpmf" ,RISCVCPU , cfg.ext_sscofpmf, false),DEFINE_PROP_BOOL ("Zifencei" ,RISCVCPU , cfg.ext_ifencei, true),DEFINE_PROP_BOOL ("Zicsr" ,RISCVCPU , cfg.ext_icsr, true),
@@ -1767,11 +1766,6 @@ static Property riscv_cpu_extensions[] = {DEFINE_PROP_BOOL ("pmp" ,RISCVCPU , cfg.pmp, true),DEFINE_PROP_BOOL ("sstc" ,RISCVCPU , cfg.ext_sstc, true), -DEFINE_PROP_STRING ("priv_spec" ,RISCVCPU , cfg.priv_spec), -DEFINE_PROP_STRING ("vext_spec" ,RISCVCPU , cfg.vext_spec), -DEFINE_PROP_UINT16 ("vlen" ,RISCVCPU , cfg.vlen,128 ), -DEFINE_PROP_UINT16 ("elen" ,RISCVCPU , cfg.elen,64 ), -DEFINE_PROP_BOOL ("smstateen" ,RISCVCPU , cfg.ext_smstateen, false),DEFINE_PROP_BOOL ("svadu" ,RISCVCPU , cfg.ext_svadu, true), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
@@ -1802,9 +1796,7 @@ static Property riscv_cpu_extensions[] = {DEFINE_PROP_BOOL ("zhinxmin" ,RISCVCPU , cfg.ext_zhinxmin, false),DEFINE_PROP_BOOL ("zicbom" ,RISCVCPU , cfg.ext_icbom, true), -DEFINE_PROP_UINT16 ("cbom_blocksize" ,RISCVCPU , cfg.cbom_blocksize,64 ),DEFINE_PROP_BOOL ("zicboz" ,RISCVCPU , cfg.ext_icboz, true), -DEFINE_PROP_UINT16 ("cboz_blocksize" ,RISCVCPU , cfg.cboz_blocksize,64 ), DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
@@ -1848,6 +1840,20 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; +static Property riscv_cpu_options[] = { +DEFINE_PROP_UINT8 ("pmu-num" ,RISCVCPU , cfg.pmu_num,16 ), + +DEFINE_PROP_STRING ("priv_spec" ,RISCVCPU , cfg.priv_spec), +DEFINE_PROP_STRING ("vext_spec" ,RISCVCPU , cfg.vext_spec), + +DEFINE_PROP_UINT16 ("vlen" ,RISCVCPU , cfg.vlen,128 ), +DEFINE_PROP_UINT16 ("elen" ,RISCVCPU , cfg.elen,64 ), + +DEFINE_PROP_UINT16 ("cbom_blocksize" ,RISCVCPU , cfg.cbom_blocksize,64 ), +DEFINE_PROP_UINT16 ("cboz_blocksize" ,RISCVCPU , cfg.cboz_blocksize,64 ), + +DEFINE_PROP_END_OF_LIST (), +};#ifndef CONFIG_USER_ONLY static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
@@ -1916,6 +1922,11 @@ static void riscv_cpu_add_user_properties(Object *obj)#endif qdev_property_add_static (dev, prop); } + +for (prop = riscv_cpu_options; prop && prop->name; prop++) { +qdev_property_add_static (dev, prop); + } + }static Property riscv_cpu_properties[] = {
Signature · 1 line
2.41.0
Re: [PATCH for-8.2 v2 1/7] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
Quoted 5 lines · Daniel Henrique Barboza
We'll add a new CPU type that will enable a considerable amount of extensions. To make it easier for us we'll do a few cleanups in our existing riscv_cpu_extensions[] array.
Quoted 7 lines
Start by splitting all CPU non-boolean options from it. Create a new riscv_cpu_options[] array for them. Add all these properties in
riscv_cpu_add_user_properties()as it is already being done today.No functional changes made.
Signed-off-by Daniel Henrique Barboza <[email protected]>
Alistair
Quoted 75 lines
--- target/riscv/cpu.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-)target/riscv/cpu.c +19
-9@@ -1751,7 +1751,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)static Property riscv_cpu_extensions[] = {/* Defaults for standard extensions */ -DEFINE_PROP_UINT8 ("pmu-num" ,RISCVCPU , cfg.pmu_num,16 ),DEFINE_PROP_BOOL ("sscofpmf" ,RISCVCPU , cfg.ext_sscofpmf, false),DEFINE_PROP_BOOL ("Zifencei" ,RISCVCPU , cfg.ext_ifencei, true),DEFINE_PROP_BOOL ("Zicsr" ,RISCVCPU , cfg.ext_icsr, true),@@ -1767,11 +1766,6 @@ static Property riscv_cpu_extensions[] = {DEFINE_PROP_BOOL ("pmp" ,RISCVCPU , cfg.pmp, true),DEFINE_PROP_BOOL ("sstc" ,RISCVCPU , cfg.ext_sstc, true), -DEFINE_PROP_STRING ("priv_spec" ,RISCVCPU , cfg.priv_spec), -DEFINE_PROP_STRING ("vext_spec" ,RISCVCPU , cfg.vext_spec), -DEFINE_PROP_UINT16 ("vlen" ,RISCVCPU , cfg.vlen,128 ), -DEFINE_PROP_UINT16 ("elen" ,RISCVCPU , cfg.elen,64 ), -DEFINE_PROP_BOOL ("smstateen" ,RISCVCPU , cfg.ext_smstateen, false),DEFINE_PROP_BOOL ("svadu" ,RISCVCPU , cfg.ext_svadu, true), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),@@ -1802,9 +1796,7 @@ static Property riscv_cpu_extensions[] = {DEFINE_PROP_BOOL ("zhinxmin" ,RISCVCPU , cfg.ext_zhinxmin, false),DEFINE_PROP_BOOL ("zicbom" ,RISCVCPU , cfg.ext_icbom, true), -DEFINE_PROP_UINT16 ("cbom_blocksize" ,RISCVCPU , cfg.cbom_blocksize,64 ),DEFINE_PROP_BOOL ("zicboz" ,RISCVCPU , cfg.ext_icboz, true), -DEFINE_PROP_UINT16 ("cboz_blocksize" ,RISCVCPU , cfg.cboz_blocksize,64 ), DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),@@ -1848,6 +1840,20 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; +static Property riscv_cpu_options[] = { +DEFINE_PROP_UINT8 ("pmu-num" ,RISCVCPU , cfg.pmu_num,16 ), + +DEFINE_PROP_STRING ("priv_spec" ,RISCVCPU , cfg.priv_spec), +DEFINE_PROP_STRING ("vext_spec" ,RISCVCPU , cfg.vext_spec), + +DEFINE_PROP_UINT16 ("vlen" ,RISCVCPU , cfg.vlen,128 ), +DEFINE_PROP_UINT16 ("elen" ,RISCVCPU , cfg.elen,64 ), + +DEFINE_PROP_UINT16 ("cbom_blocksize" ,RISCVCPU , cfg.cbom_blocksize,64 ), +DEFINE_PROP_UINT16 ("cboz_blocksize" ,RISCVCPU , cfg.cboz_blocksize,64 ), + +DEFINE_PROP_END_OF_LIST (), +};#ifndef CONFIG_USER_ONLY static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,@@ -1916,6 +1922,11 @@ static void riscv_cpu_add_user_properties(Object *obj)#endif qdev_property_add_static (dev, prop); } + +for (prop = riscv_cpu_options; prop && prop->name; prop++) { +qdev_property_add_static (dev, prop); + } + }static Property riscv_cpu_properties[] = { --2.41.0
PATCH v2 2/7 target/riscv/cpu.c: skip 'bool' check when filtering KVM props
In reply to Daniel Henrique BarbozaAfter the introduction of riscv_cpu_options[] all properties in riscv_cpu_extensions[] are booleans. This check is now obsolete.
--- target/riscv/cpu.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-)
target/riscv/cpu.c +4 -10
@@ -1907,17 +1907,11 @@ static void riscv_cpu_add_user_properties(Object *obj)* Set the default to disabled for every extension * unknown to KVM and error out if the user attempts * to enable any of them. -* -* We're giving a pass for non-bool properties since they're -* not related to the availability of extensions and can be -* safely ignored as is. */ -if (prop->info == &qdev_prop_bool) { -object_property_add (obj, prop->name,"bool" , -NULL , cpu_set_cfg_unavailable, -NULL , (void *)prop->name); -continue ; - } +object_property_add (obj, prop->name,"bool" , +NULL , cpu_set_cfg_unavailable, +NULL , (void *)prop->name); + continue; }#endif qdev_property_add_static (dev, prop);
Signature · 1 line
2.41.0
Re: [PATCH for-8.2 v2 2/7] target/riscv/cpu.c: skip 'bool' check when filtering KVM props
Quoted 5 lines · Daniel Henrique Barboza
After the introduction of riscv_cpu_options[] all properties in riscv_cpu_extensions[] are booleans. This check is now obsolete.
Signed-off-by Daniel Henrique Barboza <[email protected]>
Alistair
Quoted 34 lines
--- target/riscv/cpu.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-)target/riscv/cpu.c +4
-11@@ -1907,17 +1907,11 @@ static void riscv_cpu_add_user_properties(Object *obj)* Set the default to disabled for every extension * unknown to KVM and error out if the user attempts * to enable any of them. -* -* We're giving a pass for non-bool properties since they're -* not related to the availability of extensions and can be -* safely ignored as is. */ -if (prop->info == &qdev_prop_bool) { -object_property_add (obj, prop->name,"bool" , -NULL , cpu_set_cfg_unavailable, -NULL , (void *)prop->name); -continue ; - } +object_property_add (obj, prop->name,"bool" , +NULL , cpu_set_cfg_unavailable, +NULL , (void *)prop->name); + continue; }#endif qdev_property_add_static (dev, prop); --2.41.0
PATCH v2 3/7 target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
In reply to Daniel Henrique BarbozaOur goal is to make riscv_cpu_extensions[] hold only ratified, non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing riscv_cpu_add_user_properties() accordingly.
--- target/riscv/cpu.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-)
target/riscv/cpu.c +20 -14
@@ -1808,20 +1808,6 @@ static Property riscv_cpu_extensions[] = {DEFINE_PROP_BOOL ("zcmp" ,RISCVCPU , cfg.ext_zcmp, false),DEFINE_PROP_BOOL ("zcmt" ,RISCVCPU , cfg.ext_zcmt, false), -/* Vendor-specific custom extensions */ -DEFINE_PROP_BOOL ("xtheadba" ,RISCVCPU , cfg.ext_xtheadba, false), -DEFINE_PROP_BOOL ("xtheadbb" ,RISCVCPU , cfg.ext_xtheadbb, false), -DEFINE_PROP_BOOL ("xtheadbs" ,RISCVCPU , cfg.ext_xtheadbs, false), -DEFINE_PROP_BOOL ("xtheadcmo" ,RISCVCPU , cfg.ext_xtheadcmo, false), -DEFINE_PROP_BOOL ("xtheadcondmov" ,RISCVCPU , cfg.ext_xtheadcondmov, false), -DEFINE_PROP_BOOL ("xtheadfmemidx" ,RISCVCPU , cfg.ext_xtheadfmemidx, false), -DEFINE_PROP_BOOL ("xtheadfmv" ,RISCVCPU , cfg.ext_xtheadfmv, false), -DEFINE_PROP_BOOL ("xtheadmac" ,RISCVCPU , cfg.ext_xtheadmac, false), -DEFINE_PROP_BOOL ("xtheadmemidx" ,RISCVCPU , cfg.ext_xtheadmemidx, false), -DEFINE_PROP_BOOL ("xtheadmempair" ,RISCVCPU , cfg.ext_xtheadmempair, false), -DEFINE_PROP_BOOL ("xtheadsync" ,RISCVCPU , cfg.ext_xtheadsync, false), -DEFINE_PROP_BOOL ("xventanacondops" ,RISCVCPU , cfg.ext_XVentanaCondOps, false), -/* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
@@ -1840,6 +1826,23 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; +static Property riscv_cpu_vendor_exts[] = { +DEFINE_PROP_BOOL ("xtheadba" ,RISCVCPU , cfg.ext_xtheadba, false), +DEFINE_PROP_BOOL ("xtheadbb" ,RISCVCPU , cfg.ext_xtheadbb, false), +DEFINE_PROP_BOOL ("xtheadbs" ,RISCVCPU , cfg.ext_xtheadbs, false), +DEFINE_PROP_BOOL ("xtheadcmo" ,RISCVCPU , cfg.ext_xtheadcmo, false), +DEFINE_PROP_BOOL ("xtheadcondmov" ,RISCVCPU , cfg.ext_xtheadcondmov, false), +DEFINE_PROP_BOOL ("xtheadfmemidx" ,RISCVCPU , cfg.ext_xtheadfmemidx, false), +DEFINE_PROP_BOOL ("xtheadfmv" ,RISCVCPU , cfg.ext_xtheadfmv, false), +DEFINE_PROP_BOOL ("xtheadmac" ,RISCVCPU , cfg.ext_xtheadmac, false), +DEFINE_PROP_BOOL ("xtheadmemidx" ,RISCVCPU , cfg.ext_xtheadmemidx, false), +DEFINE_PROP_BOOL ("xtheadmempair" ,RISCVCPU , cfg.ext_xtheadmempair, false), +DEFINE_PROP_BOOL ("xtheadsync" ,RISCVCPU , cfg.ext_xtheadsync, false), +DEFINE_PROP_BOOL ("xventanacondops" ,RISCVCPU , cfg.ext_XVentanaCondOps, false), + +DEFINE_PROP_END_OF_LIST (), +}; +static Property riscv_cpu_options[] = {DEFINE_PROP_UINT8 ("pmu-num" ,RISCVCPU , cfg.pmu_num,16 ),
@@ -1921,6 +1924,9 @@ static void riscv_cpu_add_user_properties(Object *obj)qdev_property_add_static (dev, prop); } +for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) { +qdev_property_add_static (dev, prop); + } }static Property riscv_cpu_properties[] = {
Signature · 1 line
2.41.0
Re: [PATCH for-8.2 v2 3/7] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
Quoted 8 lines · Daniel Henrique Barboza
Our goal is to make riscv_cpu_extensions[] hold only ratified, non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties()accordingly.Signed-off-by Daniel Henrique Barboza <[email protected]>
Alistair
Quoted 67 lines
--- target/riscv/cpu.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-)target/riscv/cpu.c +20
-15@@ -1808,20 +1808,6 @@ static Property riscv_cpu_extensions[] = {DEFINE_PROP_BOOL ("zcmp" ,RISCVCPU , cfg.ext_zcmp, false),DEFINE_PROP_BOOL ("zcmt" ,RISCVCPU , cfg.ext_zcmt, false), -/* Vendor-specific custom extensions */ -DEFINE_PROP_BOOL ("xtheadba" ,RISCVCPU , cfg.ext_xtheadba, false), -DEFINE_PROP_BOOL ("xtheadbb" ,RISCVCPU , cfg.ext_xtheadbb, false), -DEFINE_PROP_BOOL ("xtheadbs" ,RISCVCPU , cfg.ext_xtheadbs, false), -DEFINE_PROP_BOOL ("xtheadcmo" ,RISCVCPU , cfg.ext_xtheadcmo, false), -DEFINE_PROP_BOOL ("xtheadcondmov" ,RISCVCPU , cfg.ext_xtheadcondmov, false), -DEFINE_PROP_BOOL ("xtheadfmemidx" ,RISCVCPU , cfg.ext_xtheadfmemidx, false), -DEFINE_PROP_BOOL ("xtheadfmv" ,RISCVCPU , cfg.ext_xtheadfmv, false), -DEFINE_PROP_BOOL ("xtheadmac" ,RISCVCPU , cfg.ext_xtheadmac, false), -DEFINE_PROP_BOOL ("xtheadmemidx" ,RISCVCPU , cfg.ext_xtheadmemidx, false), -DEFINE_PROP_BOOL ("xtheadmempair" ,RISCVCPU , cfg.ext_xtheadmempair, false), -DEFINE_PROP_BOOL ("xtheadsync" ,RISCVCPU , cfg.ext_xtheadsync, false), -DEFINE_PROP_BOOL ("xventanacondops" ,RISCVCPU , cfg.ext_XVentanaCondOps, false), -/* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),@@ -1840,6 +1826,23 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; +static Property riscv_cpu_vendor_exts[] = { +DEFINE_PROP_BOOL ("xtheadba" ,RISCVCPU , cfg.ext_xtheadba, false), +DEFINE_PROP_BOOL ("xtheadbb" ,RISCVCPU , cfg.ext_xtheadbb, false), +DEFINE_PROP_BOOL ("xtheadbs" ,RISCVCPU , cfg.ext_xtheadbs, false), +DEFINE_PROP_BOOL ("xtheadcmo" ,RISCVCPU , cfg.ext_xtheadcmo, false), +DEFINE_PROP_BOOL ("xtheadcondmov" ,RISCVCPU , cfg.ext_xtheadcondmov, false), +DEFINE_PROP_BOOL ("xtheadfmemidx" ,RISCVCPU , cfg.ext_xtheadfmemidx, false), +DEFINE_PROP_BOOL ("xtheadfmv" ,RISCVCPU , cfg.ext_xtheadfmv, false), +DEFINE_PROP_BOOL ("xtheadmac" ,RISCVCPU , cfg.ext_xtheadmac, false), +DEFINE_PROP_BOOL ("xtheadmemidx" ,RISCVCPU , cfg.ext_xtheadmemidx, false), +DEFINE_PROP_BOOL ("xtheadmempair" ,RISCVCPU , cfg.ext_xtheadmempair, false), +DEFINE_PROP_BOOL ("xtheadsync" ,RISCVCPU , cfg.ext_xtheadsync, false), +DEFINE_PROP_BOOL ("xventanacondops" ,RISCVCPU , cfg.ext_XVentanaCondOps, false), + +DEFINE_PROP_END_OF_LIST (), +}; +static Property riscv_cpu_options[] = {DEFINE_PROP_UINT8 ("pmu-num" ,RISCVCPU , cfg.pmu_num,16 ),@@ -1921,6 +1924,9 @@ static void riscv_cpu_add_user_properties(Object *obj)qdev_property_add_static (dev, prop); } +for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) { +qdev_property_add_static (dev, prop); + } }static Property riscv_cpu_properties[] = { --2.41.0
PATCH v2 4/7 target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
In reply to Daniel Henrique BarbozaCreate a new riscv_cpu_experimental_exts[] to store the non-ratified extensions properties. Once they are ratified we'll move them back to riscv_cpu_extensions[].
Change riscv_cpu_add_user_properties to keep adding them to users.
--- target/riscv/cpu.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-)
target/riscv/cpu.c +23 -15
@@ -1808,21 +1808,6 @@ static Property riscv_cpu_extensions[] = {DEFINE_PROP_BOOL ("zcmp" ,RISCVCPU , cfg.ext_zcmp, false),DEFINE_PROP_BOOL ("zcmt" ,RISCVCPU , cfg.ext_zcmt, false), -/* These are experimental so mark with 'x-' */ -DEFINE_PROP_BOOL ("x-zicond" ,RISCVCPU , cfg.ext_zicond, false), - -/* ePMP 0.9.3 */ -DEFINE_PROP_BOOL ("x-epmp" ,RISCVCPU , cfg.epmp, false), -DEFINE_PROP_BOOL ("x-smaia" ,RISCVCPU , cfg.ext_smaia, false), -DEFINE_PROP_BOOL ("x-ssaia" ,RISCVCPU , cfg.ext_ssaia, false), - -DEFINE_PROP_BOOL ("x-zvfh" ,RISCVCPU , cfg.ext_zvfh, false), -DEFINE_PROP_BOOL ("x-zvfhmin" ,RISCVCPU , cfg.ext_zvfhmin, false), - -DEFINE_PROP_BOOL ("x-zfbfmin" ,RISCVCPU , cfg.ext_zfbfmin, false), -DEFINE_PROP_BOOL ("x-zvfbfmin" ,RISCVCPU , cfg.ext_zvfbfmin, false), -DEFINE_PROP_BOOL ("x-zvfbfwma" ,RISCVCPU , cfg.ext_zvfbfwma, false), - DEFINE_PROP_END_OF_LIST(), };
@@ -1843,6 +1828,25 @@ static Property riscv_cpu_vendor_exts[] = { DEFINE_PROP_END_OF_LIST(), }; +/* These are experimental so mark with 'x-' */ +static Property riscv_cpu_experimental_exts[] = { +DEFINE_PROP_BOOL ("x-zicond" ,RISCVCPU , cfg.ext_zicond, false), + +/* ePMP 0.9.3 */ +DEFINE_PROP_BOOL ("x-epmp" ,RISCVCPU , cfg.epmp, false), +DEFINE_PROP_BOOL ("x-smaia" ,RISCVCPU , cfg.ext_smaia, false), +DEFINE_PROP_BOOL ("x-ssaia" ,RISCVCPU , cfg.ext_ssaia, false), + +DEFINE_PROP_BOOL ("x-zvfh" ,RISCVCPU , cfg.ext_zvfh, false), +DEFINE_PROP_BOOL ("x-zvfhmin" ,RISCVCPU , cfg.ext_zvfhmin, false), + +DEFINE_PROP_BOOL ("x-zfbfmin" ,RISCVCPU , cfg.ext_zfbfmin, false), +DEFINE_PROP_BOOL ("x-zvfbfmin" ,RISCVCPU , cfg.ext_zvfbfmin, false), +DEFINE_PROP_BOOL ("x-zvfbfwma" ,RISCVCPU , cfg.ext_zvfbfwma, false), + +DEFINE_PROP_END_OF_LIST (), +}; +static Property riscv_cpu_options[] = {DEFINE_PROP_UINT8 ("pmu-num" ,RISCVCPU , cfg.pmu_num,16 ),
@@ -1927,6 +1931,10 @@ static void riscv_cpu_add_user_properties(Object *obj)for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {qdev_property_add_static (dev, prop); } + +for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) { +qdev_property_add_static (dev, prop); + } }static Property riscv_cpu_properties[] = {
Signature · 1 line
2.41.0
Re: [PATCH for-8.2 v2 4/7] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
Quoted 8 lines · Daniel Henrique Barboza
Create a new riscv_cpu_experimental_exts[] to store the non-ratified extensions properties. Once they are ratified we'll move them back to riscv_cpu_extensions[].
Change
riscv_cpu_add_user_propertiesto keep adding them to users.Signed-off-by Daniel Henrique Barboza <[email protected]>
Alistair
Quoted 71 lines
--- target/riscv/cpu.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-)target/riscv/cpu.c +23
-16@@ -1808,21 +1808,6 @@ static Property riscv_cpu_extensions[] = {DEFINE_PROP_BOOL ("zcmp" ,RISCVCPU , cfg.ext_zcmp, false),DEFINE_PROP_BOOL ("zcmt" ,RISCVCPU , cfg.ext_zcmt, false), -/* These are experimental so mark with 'x-' */ -DEFINE_PROP_BOOL ("x-zicond" ,RISCVCPU , cfg.ext_zicond, false), - -/* ePMP 0.9.3 */ -DEFINE_PROP_BOOL ("x-epmp" ,RISCVCPU , cfg.epmp, false), -DEFINE_PROP_BOOL ("x-smaia" ,RISCVCPU , cfg.ext_smaia, false), -DEFINE_PROP_BOOL ("x-ssaia" ,RISCVCPU , cfg.ext_ssaia, false), - -DEFINE_PROP_BOOL ("x-zvfh" ,RISCVCPU , cfg.ext_zvfh, false), -DEFINE_PROP_BOOL ("x-zvfhmin" ,RISCVCPU , cfg.ext_zvfhmin, false), - -DEFINE_PROP_BOOL ("x-zfbfmin" ,RISCVCPU , cfg.ext_zfbfmin, false), -DEFINE_PROP_BOOL ("x-zvfbfmin" ,RISCVCPU , cfg.ext_zvfbfmin, false), -DEFINE_PROP_BOOL ("x-zvfbfwma" ,RISCVCPU , cfg.ext_zvfbfwma, false), - DEFINE_PROP_END_OF_LIST(), };@@ -1843,6 +1828,25 @@ static Property riscv_cpu_vendor_exts[] = { DEFINE_PROP_END_OF_LIST(), }; +/* These are experimental so mark with 'x-' */ +static Property riscv_cpu_experimental_exts[] = { +DEFINE_PROP_BOOL ("x-zicond" ,RISCVCPU , cfg.ext_zicond, false), + +/* ePMP 0.9.3 */ +DEFINE_PROP_BOOL ("x-epmp" ,RISCVCPU , cfg.epmp, false), +DEFINE_PROP_BOOL ("x-smaia" ,RISCVCPU , cfg.ext_smaia, false), +DEFINE_PROP_BOOL ("x-ssaia" ,RISCVCPU , cfg.ext_ssaia, false), + +DEFINE_PROP_BOOL ("x-zvfh" ,RISCVCPU , cfg.ext_zvfh, false), +DEFINE_PROP_BOOL ("x-zvfhmin" ,RISCVCPU , cfg.ext_zvfhmin, false), + +DEFINE_PROP_BOOL ("x-zfbfmin" ,RISCVCPU , cfg.ext_zfbfmin, false), +DEFINE_PROP_BOOL ("x-zvfbfmin" ,RISCVCPU , cfg.ext_zvfbfmin, false), +DEFINE_PROP_BOOL ("x-zvfbfwma" ,RISCVCPU , cfg.ext_zvfbfwma, false), + +DEFINE_PROP_END_OF_LIST (), +}; +static Property riscv_cpu_options[] = {DEFINE_PROP_UINT8 ("pmu-num" ,RISCVCPU , cfg.pmu_num,16 ),@@ -1927,6 +1931,10 @@ static void riscv_cpu_add_user_properties(Object *obj)for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {qdev_property_add_static (dev, prop); } + +for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) { +qdev_property_add_static (dev, prop); + } }static Property riscv_cpu_properties[] = { --2.41.0
PATCH v2 5/7 target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro
In reply to Daniel Henrique BarbozaThe code inside riscv_cpu_add_user_properties() became quite repetitive after recent changes. Add a macro to hide the repetition away.
--- target/riscv/cpu.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-)
target/riscv/cpu.c +8 -11
@@ -1881,6 +1881,11 @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, }#endif +#define ADD_CPU_PROPERTIES_ARRAY (_dev, _array) \ + for (prop = _array; prop && prop->name; prop++) { \ + qdev_property_add_static(_dev, prop); \ + } \ +/* * Add CPU properties with user-facing flags. *
@@ -1924,17 +1929,9 @@ static void riscv_cpu_add_user_properties(Object *obj)qdev_property_add_static (dev, prop); } -for (prop = riscv_cpu_options; prop && prop->name; prop++) { -qdev_property_add_static (dev, prop); - } - -for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) { -qdev_property_add_static (dev, prop); - } - -for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) { -qdev_property_add_static (dev, prop); - } +ADD_CPU_PROPERTIES_ARRAY (dev, riscv_cpu_options); +ADD_CPU_PROPERTIES_ARRAY (dev, riscv_cpu_vendor_exts); +ADD_CPU_PROPERTIES_ARRAY (dev, riscv_cpu_experimental_exts); }static Property riscv_cpu_properties[] = {
Signature · 1 line
2.41.0
Re: [PATCH for-8.2 v2 5/7] target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro
target/riscv/cpu.c static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, · line 1887
Quoted 4 lines · Daniel Henrique Barboza
target/riscv/cpu.c +4
-0+#define ADD_CPU_PROPERTIES_ARRAY (_dev, _array) \ + for (prop = _array; prop && prop->name; prop++) { \ + qdev_property_add_static(_dev, prop); \ + } \
do { } while(0)
Watch the \ on the last line of the macro.
Declare the iterator within the macro, rather than use one defined in the outer scope. Why not use ARRAY_SIZE?
r~
Re: [PATCH for-8.2 v2 5/7] target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro
Quoted 10 lines · Richard Henderson
Quoted 4 lines · Daniel Henrique Barboza
+#define
ADD_CPU_PROPERTIES_ARRAY(_dev, _array)\
+ for (prop =_array; prop &&prop->name; prop++) { \
+qdev_property_add_static(_dev, prop); \
+ } \do { } while(0)
Watch the \ on the last line of the macro.
Declare the iterator within the macro, rather than use one defined in the outer scope.
Like this?
#define ADD_CPU_PROPERTIES_ARRAY(_dev, _array) \
do { \
Property *prop; \
for (prop = _array; prop && prop->name; prop++) { \
qdev_property_add_static(_dev, prop); \
} \
} while(0)Quoted 1 line
Why not use
ARRAY_SIZE?
Hm, the arrays are finishing with DEFINE_PROP_END_OF_LIST() (I copied the existing array structure), which adds an empty element, so ARRAY_SIZE will get empty stuff in the end.
Since these are new arrays I can get rid of the end_of_list blank element and use ARRAY_SIZE().
Daniel
Quoted 3 lines
r~
Re: [PATCH for-8.2 v2 5/7] target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro
Quoted 16 lines · Daniel Henrique Barboza
Quoted 10 lines · Richard Henderson
Quoted 4 lines · Daniel Henrique Barboza
+#define
ADD_CPU_PROPERTIES_ARRAY(_dev, _array)\
+ for (prop =_array; prop &&prop->name; prop++) { \
+qdev_property_add_static(_dev, prop); \
+ } \do { } while(0)
Watch the \ on the last line of the macro.
Declare the iterator within the macro, rather than use one defined in the outer scope.Like this?
Quoted 7 lines
#define
ADD_CPU_PROPERTIES_ARRAY(_dev, _array)\
do { \
Property *prop; \
for (prop =_array; prop &&prop->name; prop++) { \
qdev_property_add_static(_dev, prop); \
} \
} while(0)
Yes, like that, thanks.
r~
PATCH v2 6/7 target/riscv: add 'max' CPU type
In reply to Daniel Henrique BarbozaThe 'max' CPU type is used by tooling to determine what's the most capable CPU a current QEMU version implements. Other archs such as ARM implements this type. Let's add it to RISC-V.
What we consider "most capable CPU" in this context are related to ratified, non-vendor extensions. This means that we want the 'max' CPU to enable all (possible) ratified extensions by default. The reasoning behind this design is (1) vendor extensions can conflict with each other and we won't play favorities deciding which one is default or not and
(2) non-ratified extensions are always prone to changes, not being stable enough to be enabled by default.
All this said, we're still not able to enable all ratified extensions due to conflicts between them. Zfinx and all its dependencies aren't enabled because of a conflict with RVF. zce, zcmp and zcmt are also disabled due to RVD conflicts. When running with 64 bits we're also disabling zcf.
MISA bits RVG, RVJ and RVV are also being set manually since they're default disabled.
This is the resulting 'riscv,isa' DT for this new CPU:
rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_ zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_ zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_ smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt
--- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 53 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+)
target/riscv/cpu-qom.h +1 -0
@@ -30,6 +30,7 @@#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") +#define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
target/riscv/cpu.c +53 -0
77 lines not on this page · raw message
Signature · 1 line
2.41.0
Quoted 40 lines · Daniel Henrique Barboza
The 'max' CPU type is used by tooling to determine what's the most capable CPU a current QEMU version implements. Other archs such as ARM implements this type. Let's add it to RISC-V.
What we consider "most capable CPU" in this context are related to ratified, non-vendor extensions. This means that we want the 'max' CPU to enable all (possible) ratified extensions by default. The reasoning behind this design is (1) vendor extensions can conflict with each other and we won't play favorities deciding which one is default or not and
(2) non-ratified extensions are always prone to changes, not being stable enough to be enabled by default.All this said, we're still not able to enable all ratified extensions due to conflicts between them. Zfinx and all its dependencies aren't enabled because of a conflict with RVF. zce, zcmp and zcmt are also disabled due to RVD conflicts. When running with 64 bits we're also disabling zcf.
MISA bits RVG, RVJ and RVV are also being set manually since they're default disabled.
This is the resulting 'riscv,isa' DT for this new CPU:
rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmtSigned-off-by Daniel Henrique Barboza <[email protected]>--- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 53 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+)target/riscv/cpu-qom.h +0
-0
target/riscv/cpu-qom.h line 33
Quoted 4 lines
target/riscv/cpu-qom.h +1
-0@@ -30,6 +30,7 @@#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") +#define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
From memory the "any" CPU was supposed to do this, so we might want to remove it
Alistair
Quoted 92 lines
target/riscv/cpu-qom.h +0
-0#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")target/riscv/cpu.c +53
-1@@ -248,6 +248,7 @@ static const char * const riscv_intr_names[] = { };static void riscv_cpu_add_user_properties (Object *obj); +static void riscv_init_max_cpu_extensions (Object *obj);const char *riscv_cpu_get_trap_name (target_ulong cause,bool async) {@@ -374,6 +375,25 @@ static void riscv_any_cpu_init(Object *obj) cpu->cfg.pmp = true; } +static void riscv_max_cpu_init (Object *obj) +{ +RISCVCPU *cpu =RISCV_CPU (obj); +CPURISCVState *env = &cpu->env; +RISCVMXL mlx =MXL_RV64 ; + +#ifdef TARGET_RISCV32 + mlx =MXL_RV32 ; +#endif +set_misa (env, mlx,0 ); +riscv_cpu_add_user_properties (obj); +riscv_init_max_cpu_extensions (obj); + env->priv_ver =PRIV_VERSION_LATEST ; +#ifndef CONFIG_USER_ONLY +set_satp_mode_max_supported (RISCV_CPU (obj), mlx ==MXL_RV32 ? +VM_1_10_SV32 :VM_1_10_SV57 ); +#endif +} +#if defined(TARGET_RISCV64 )static void rv64_base_cpu_init (Object *obj) {@@ -1934,6 +1954,38 @@ static void riscv_cpu_add_user_properties(Object *obj)ADD_CPU_PROPERTIES_ARRAY (dev, riscv_cpu_experimental_exts); } +/* +* The 'max' type CPU will have all possible ratified +* non-vendor extensions enabled. +*/ +static void riscv_init_max_cpu_extensions (Object *obj) +{ +RISCVCPU *cpu =RISCV_CPU (obj); +CPURISCVState *env = &cpu->env; +Property *prop; + +/* Enable RVG, RVJ and RVV that are disabled by default */ +set_misa (env, env->misa_mxl, env->misa_ext |RVG |RVJ |RVV ); + +for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { +object_property_set_bool (obj, prop->name, true,NULL ); + } + +/* Zfinx is not compatible with F. Disable it */ +object_property_set_bool (obj,"zfinx" , false,NULL ); +object_property_set_bool (obj,"zdinx" , false,NULL ); +object_property_set_bool (obj,"zhinx" , false,NULL ); +object_property_set_bool (obj,"zhinxmin" , false,NULL ); + +object_property_set_bool (obj,"zce" , false,NULL ); +object_property_set_bool (obj,"zcmp" , false,NULL ); +object_property_set_bool (obj,"zcmt" , false,NULL ); + +if (env->misa_mxl !=MXL_RV32 ) { +object_property_set_bool (obj,"zcf" , false,NULL ); + } +} +static Property riscv_cpu_properties[] = {DEFINE_PROP_BOOL ("debug" ,RISCVCPU , cfg.debug, true),@@ -2272,6 +2324,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .abstract = true, }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init),#if defined(CONFIG_KVM ) DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),#endif --2.41.0
PATCH v2 7/7 avocado, risc-v: add opensbi tests for 'max' CPU
In reply to Daniel Henrique BarbozaAdd smoke tests to ensure that we'll not break the 'max' CPU type when adding new ratified extensions to be enabled.
--- tests/avocado/riscv_opensbi.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
tests/avocado/riscv_opensbi.py +16 -0
@@ -61,3 +61,19 @@ def test_riscv64_virt(self): :avocado: tags=machine:virt """ self.boot_opensbi() + + def test_riscv32_virt_maxcpu(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:virt + :avocado: tags=cpu:max + """ + self.boot_opensbi() + + def test_riscv64_virt_maxcpu(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:virt + :avocado: tags=cpu:max + """ + self.boot_opensbi()
Signature · 1 line
2.41.0