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AMD Pstate Preferred Core

PATCH Superseded Meng Li 3 participants 18 messages Aug 24, 2023 – Aug 25, 2023

Subsystems (8)
Documentation x86 Kselftest ACPI +4 more subsystems

v3 of 14 Superseded Latest is v14 →

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Meng Li

author
#0 lore raw

v3 cover AMD Pstate Preferred Core

Hi all:

The core frequency is subjected to the process variation in semiconductors. Not all cores are able to reach the maximum frequency respecting the infrastructure limits. Consequently, AMD has redefined the concept of maximum frequency of a part. This means that a fraction of cores can reach maximum frequency. To find the best process scheduling policy for a given scenario, OS needs to know the core ordering informed by the platform through highest performance capability register of the CPPC interface.

Earlier implementations of AMD Pstate Preferred Core only support a static core ranking and targeted performance. Now it has the ability to dynamically change the preferred core based on the workload and platform conditions and accounting for thermals and aging.

AMD Pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage.
We call it AMD Pstate Preferrred Core.

Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. AMD Pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority.

AMD Pstate driver will provide an initial core ordering at boot time. It relies on the CPPC interface to communicate the core ranking to the operating system and scheduler to make sure that OS is choosing the cores with highest performance firstly for scheduling the process. When AMD Pstate driver receives a message with the highest performance change, it will update the core ranking.

Changes form V2->V3:
- x86:
- - Modify kconfig and description.
- cpufreq: amd-pstate:
- - Add Co-developed-by tag in commit message.
- cpufreq:
- - Modify commit message.
- Documentation: amd-pstate:
- - Modify inappropriate descriptions.

Changes form V1->V2:
- acpi: cppc:
- - Add reference link.
- cpufreq:
- - Moidfy link error.
- cpufreq: amd-pstate:
- - Init the priorities of all online CPUs
- - Use a single variable to represent the status of Preferred Core.
- Documentation:
- - Default enabled preferred core.
- Documentation: amd-pstate:
- - Modify inappropriate descriptions.
- - Default enabled preferred core.
- - Use a single variable to represent the status of Preferred Core.

Meng Li (7):
x86: Drop CPU_SUP_INTEL from SCHED_MC_PRIO for the expansion.
acpi: cppc: Add get the highest performance cppc control
cpufreq: amd-pstate: Enable AMD Pstate Preferred Core Supporting.
cpufreq: Add a notification message that the highest perf has changed
cpufreq: amd-pstate: Update AMD Pstate Preferred Core ranking
dynamically
Documentation: amd-pstate: introduce AMD Pstate Preferred Core
Documentation: introduce AMD Pstate Preferrd Core mode kernel command
line options

 .../admin-guide/kernel-parameters.txt         |   5 +
 Documentation/admin-guide/pm/amd-pstate.rst   |  53 ++++++
 arch/x86/Kconfig                              |   5 +-
 drivers/acpi/cppc_acpi.c                      |  13 ++
 drivers/acpi/processor_driver.c               |   6 +
 drivers/cpufreq/amd-pstate.c                  | 152 ++++++++++++++++--
 drivers/cpufreq/cpufreq.c                     |  13 ++
 include/acpi/cppc_acpi.h                      |   5 +
 include/linux/amd-pstate.h                    |   1 +
 include/linux/cpufreq.h                       |   4 +
 10 files changed, 239 insertions(+), 18 deletions(-)
Signature · 1 line
2.34.1
author
#1 lore raw

PATCH v3 1/7 x86: Drop CPU_SUP_INTEL from SCHED_MC_PRIO for the expansion.

AMD Pstate driver also uses SCHED_MC_PRIO, so decouple the requirement of CPU_SUP_INTEL from the dependencies to allow compilation in kernels without Intel CPU support.

Signed-off-by Meng Li <[email protected]>
---
 arch/x86/Kconfig | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
arch/x86/Kconfig +3 -2
index e36261b4ea14..16df141bd8a2 100644
@@ -1052,8 +1052,9 @@ config SCHED_MC
 
 config SCHED_MC_PRIO
 	bool "CPU core priorities scheduler support"
-	depends on SCHED_MC && CPU_SUP_INTEL
-	select X86_INTEL_PSTATE
+	depends on SCHED_MC
+	select X86_INTEL_PSTATE if CPU_SUP_INTEL
+	select X86_AMD_PSTATE if CPU_SUP_AMD
 	select CPU_FREQ
 	default y
 	help
Signature · 1 line
2.34.1
author
#2 lore raw

PATCH v3 2/7 acpi: cppc: Add get the highest performance cppc control

In reply to Meng Li

Add support for getting the highest performance to the generic CPPC driver. This enables downstream drivers such as amd-pstate to discover and use these values.

Please refer to the ACPI_Spec for details on continuous performance control of CPPC.

Signed-off-by Meng Li <[email protected]>
Reviewed-by Mario Limonciello <[email protected]>
Link https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#cpc-continuous-performance-control
---
 drivers/acpi/cppc_acpi.c | 13 +++++++++++++
 include/acpi/cppc_acpi.h |  5 +++++
 2 files changed, 18 insertions(+)
drivers/acpi/cppc_acpi.c +13 -0
index 7ff269a78c20..ad388a0e8484 100644
@@ -1154,6 +1154,19 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
 	return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
 }
 
+/**
+ * cppc_get_highest_perf - Get the highest performance register value.
+ * @cpunum: CPU from which to get highest performance.
+ * @highest_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
+{
+	return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf);
+}
+EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
+
 /**
  * cppc_get_epp_perf - Get the epp register value.
  * @cpunum: CPU from which to get epp preference value.
include/acpi/cppc_acpi.h +5 -0
index 6126c977ece0..c0b69ffe7bdb 100644
@@ -139,6 +139,7 @@ struct cppc_cpudata {
 #ifdef CONFIG_ACPI_CPPC_LIB
 extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf);
 extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf);
+extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf);
 extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs);
 extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
 extern int cppc_set_enable(int cpu, bool enable);

@@ -165,6 +166,10 @@ static inline int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
 {
 	return -ENOTSUPP;
 }
+static inline int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
+{
+	return -ENOTSUPP;
+}
 static inline int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
 {
 	return -ENOTSUPP;
Signature · 1 line
2.34.1
Reviewed-by on v3 2/7
#3 lore raw

Re: [PATCH V3 2/7] acpi: cppc: Add get the highest performance cppc control

Quoted 9 lines · Meng Li

Add support for getting the highest performance to the generic CPPC driver. This enables downstream drivers such as amd-pstate to discover and use these values.

Please refer to the ACPI_Spec for details on continuous performance control of CPPC.

Signed-off-by Meng Li <[email protected]>
Reviewed-by Mario Limonciello <[email protected]>
Reviewed-by Wyes Karny <[email protected]>
Quoted 56 lines
Link https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#cpc-continuous-performance-control
---
 drivers/acpi/cppc_acpi.c | 13 +++++++++++++
 include/acpi/cppc_acpi.h |  5 +++++
 2 files changed, 18 insertions(+)
drivers/acpi/cppc_acpi.c +13 -0
index 7ff269a78c20..ad388a0e8484 100644
@@ -1154,6 +1154,19 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
 	return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
 }
 
+/**
+ * cppc_get_highest_perf - Get the highest performance register value.
+ * @cpunum: CPU from which to get highest performance.
+ * @highest_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
+{
+	return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf);
+}
+EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
+
 /**
  * cppc_get_epp_perf - Get the epp register value.
  * @cpunum: CPU from which to get epp preference value.
include/acpi/cppc_acpi.h +5 -0
index 6126c977ece0..c0b69ffe7bdb 100644
@@ -139,6 +139,7 @@ struct cppc_cpudata {
 #ifdef CONFIG_ACPI_CPPC_LIB
 extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf);
 extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf);
+extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf);
 extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs);
 extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
 extern int cppc_set_enable(int cpu, bool enable);

@@ -165,6 +166,10 @@ static inline int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
 {
 	return -ENOTSUPP;
 }
+static inline int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
+{
+	return -ENOTSUPP;
+}
 static inline int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
 {
 	return -ENOTSUPP;
Signature · 1 line
2.34.1
Reviewed-by on v3 2/7
#4 lore raw

Re: [PATCH V3 2/7] acpi: cppc: Add get the highest performance cppc control

In reply to Meng Li
Quoted 9 lines · Meng Li

Add support for getting the highest performance to the generic CPPC driver. This enables downstream drivers such as amd-pstate to discover and use these values.

Please refer to the ACPI_Spec for details on continuous performance control of CPPC.

Signed-off-by Meng Li <[email protected]>
Reviewed-by Mario Limonciello <[email protected]>
Reviewed-by Wyes Karny <[email protected]>
Quoted 56 lines
Link https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#cpc-continuous-performance-control
---
 drivers/acpi/cppc_acpi.c | 13 +++++++++++++
 include/acpi/cppc_acpi.h |  5 +++++
 2 files changed, 18 insertions(+)
drivers/acpi/cppc_acpi.c +13 -0
index 7ff269a78c20..ad388a0e8484 100644
@@ -1154,6 +1154,19 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
 	return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
 }
 
+/**
+ * cppc_get_highest_perf - Get the highest performance register value.
+ * @cpunum: CPU from which to get highest performance.
+ * @highest_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
+{
+	return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf);
+}
+EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
+
 /**
  * cppc_get_epp_perf - Get the epp register value.
  * @cpunum: CPU from which to get epp preference value.
include/acpi/cppc_acpi.h +5 -0
index 6126c977ece0..c0b69ffe7bdb 100644
@@ -139,6 +139,7 @@ struct cppc_cpudata {
 #ifdef CONFIG_ACPI_CPPC_LIB
 extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf);
 extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf);
+extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf);
 extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs);
 extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
 extern int cppc_set_enable(int cpu, bool enable);

@@ -165,6 +166,10 @@ static inline int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
 {
 	return -ENOTSUPP;
 }
+static inline int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
+{
+	return -ENOTSUPP;
+}
 static inline int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
 {
 	return -ENOTSUPP;
Signature · 1 line
2.34.1
author
#5 lore raw

PATCH v3 3/7 cpufreq: amd-pstate: Enable AMD Pstate Preferred Core Supporting.

In reply to Meng Li

AMD Pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage. We call it AMD Pstate Preferrred Core.

Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. AMD Pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority.

The initial core rankings are set up by AMD Pstate when the system boots.

Add device attribute for preferred core states.

Add one new early parameter enable to allow user to enable the preferred core if the processor and power firmware can support preferred core feature.

Signed-off-by Perry Yuan <[email protected]>
Co-developed-by Perry Yuan <[email protected]>
Signed-off-by Meng Li <[email protected]>
Co-developed-by Meng Li <[email protected]>
Reviewed-by Mario Limonciello <[email protected]>
---
 drivers/cpufreq/amd-pstate.c | 120 ++++++++++++++++++++++++++++++-----
 1 file changed, 104 insertions(+), 16 deletions(-)
drivers/cpufreq/amd-pstate.c +104 -16
index 9a1e194d5cf8..d02305675f66 100644
@@ -37,6 +37,7 @@
 #include <linux/uaccess.h>
 #include <linux/static_call.h>
 #include <linux/amd-pstate.h>
+#include <linux/topology.h>
 
 #include <acpi/processor.h>
 #include <acpi/cppc_acpi.h>

@@ -49,6 +50,8 @@
 
 #define AMD_PSTATE_TRANSITION_LATENCY	20000
 #define AMD_PSTATE_TRANSITION_DELAY	1000
+#define AMD_PSTATE_PREFCORE_THRESHOLD	166
+#define AMD_PSTATE_MAX_CPPC_PERF	255
 
 /*
  * TODO: We need more time to fine tune processors with shared memory solution

@@ -65,6 +68,9 @@ static struct cpufreq_driver amd_pstate_epp_driver;
 static int cppc_state = AMD_PSTATE_UNDEFINED;
 static bool cppc_enabled;
 
+/*Preferred Core featue is supported*/
+static bool prefcore = true;
+
 /*
  * AMD Energy Preference Performance (EPP)
  * The EPP is used in the CCLK DPM controller to drive

@@ -290,23 +296,21 @@ static inline int amd_pstate_enable(bool enable)
 static int pstate_init_perf(struct amd_cpudata *cpudata)
 {
 	u64 cap1;
-	u32 highest_perf;
 
 	int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
 				     &cap1);
 	if (ret)
 		return ret;
 
-	/*
-	 * TODO: Introduce AMD specific power feature.
-	 *
-	 * CPPC entry doesn't indicate the highest performance in some ASICs.
+	/* For platforms that do not support the preferred core feature, the
+	 * highest_pef may be configured with 166 or 255, to avoid max frequency
+	 * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as
+	 * the default max perf.
 	 */
-	highest_perf = amd_get_highest_perf();
-	if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1))
-		highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
-
-	WRITE_ONCE(cpudata->highest_perf, highest_perf);
+	if (prefcore)
+		WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD);
+	else
+		WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
 
 	WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));

@@ -318,17 +322,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
 static int cppc_init_perf(struct amd_cpudata *cpudata)
 {
 	struct cppc_perf_caps cppc_perf;
-	u32 highest_perf;
 
 	int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
 	if (ret)
 		return ret;
 
-	highest_perf = amd_get_highest_perf();
-	if (highest_perf > cppc_perf.highest_perf)
-		highest_perf = cppc_perf.highest_perf;
-
-	WRITE_ONCE(cpudata->highest_perf, highest_perf);
+	if (prefcore)
+		WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD);
+	else
+		WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf);
 
 	WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf,

@@ -676,6 +678,72 @@ static void amd_perf_ctl_reset(unsigned int cpu)
 	wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);
 }
 
+/*
+ * Set AMD Pstate Preferred Core enable can't be done directly from cpufreq callbacks
+ * due to locking, so queue the work for later.
+ */
+static void amd_pstste_sched_prefcore_workfn(struct work_struct *work)
+{
+	sched_set_itmt_support();
+}
+static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn);
+
+/**
+ * Get the highest performance register value.
+ * @cpu: CPU from which to get highest performance.
+ * @highest_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf)
+{
+       int ret;
+
+       if (boot_cpu_has(X86_FEATURE_CPPC)) {
+               u64 cap1;
+
+               ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1);
+               if (ret)
+                       return ret;
+               WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
+       } else {
+               ret = cppc_get_highest_perf(cpu, highest_perf);
+       }
+
+       return (ret);
+}
+
+static void amd_pstate_init_prefcore(void)
+{
+	int cpu, ret;
+	u64 highest_perf;
+
+	if (!prefcore)
+		return;
+
+	for_each_online_cpu(cpu) {
+		ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+		if (ret)
+			break;
+
+		sched_set_itmt_core_prio(highest_perf, cpu);
+
+		/* check if CPPC preferred core feature is enabled*/
+		if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) {
+			prefcore = false;
+			return;
+		}
+	}
+
+	/*
+	 * This code can be run during CPU online under the
+	 * CPU hotplug locks, so sched_set_amd_prefcore_support()
+	 * cannot be called from here.  Queue up a work item
+	 * to invoke it.
+	 */
+	schedule_work(&sched_prefcore_work);
+}
+
 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
 {
 	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;

@@ -1037,6 +1105,12 @@ static ssize_t status_store(struct device *a, struct device_attribute *b,
 	return ret < 0 ? ret : count;
 }
 
+static ssize_t prefcore_show(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled");
+}
+
 cpufreq_freq_attr_ro(amd_pstate_max_freq);
 cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
 

@@ -1044,6 +1118,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
 cpufreq_freq_attr_rw(energy_performance_preference);
 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 static DEVICE_ATTR_RW(status);
+static DEVICE_ATTR_RO(prefcore);
 
 static struct freq_attr *amd_pstate_attr[] = {
 	&amd_pstate_max_freq,

@@ -1063,6 +1138,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
 
 static struct attribute *pstate_global_attributes[] = {
 	&dev_attr_status.attr,
+	&dev_attr_prefcore.attr,
 	NULL
 };
 

@@ -1506,6 +1582,8 @@ static int __init amd_pstate_init(void)
 		}
 	}
 
+	amd_pstate_init_prefcore();
+
 	return ret;
 
 global_attr_free:

@@ -1527,7 +1605,17 @@ static int __init amd_pstate_param(char *str)
 
 	return amd_pstate_set_driver(mode_idx);
 }
+
+static int __init amd_prefcore_param(char *str)
+{
+	if (!strcmp(str, "disable"))
+		prefcore = false;
+
+	return 0;
+}
+
 early_param("amd_pstate", amd_pstate_param);
+early_param("amd_prefcore", amd_prefcore_param);
 
 MODULE_AUTHOR("Huang Rui <[email protected]>");
 MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");
Signature · 1 line
2.34.1
#6 lore raw

Re: [PATCH V3 3/7] cpufreq: amd-pstate: Enable AMD Pstate Preferred Core Supporting.

Hi Meng Li,

Quoted 78 lines · Meng Li

AMD Pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage. We call it AMD Pstate Preferrred Core.

Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. AMD Pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority.

The initial core rankings are set up by AMD Pstate when the system boots.

Add device attribute for preferred core states.

Add one new early parameter enable to allow user to enable the preferred core if the processor and power firmware can support preferred core feature.

Signed-off-by Perry Yuan <[email protected]>
Co-developed-by Perry Yuan <[email protected]>
Signed-off-by Meng Li <[email protected]>
Co-developed-by Meng Li <[email protected]>
Reviewed-by Mario Limonciello <[email protected]>
---
 drivers/cpufreq/amd-pstate.c | 120 ++++++++++++++++++++++++++++++-----
 1 file changed, 104 insertions(+), 16 deletions(-)
drivers/cpufreq/amd-pstate.c +10 -5
index 9a1e194d5cf8..d02305675f66 100644
@@ -37,6 +37,7 @@
 #include <linux/uaccess.h>
 #include <linux/static_call.h>
 #include <linux/amd-pstate.h>
+#include <linux/topology.h>
 
 #include <acpi/processor.h>
 #include <acpi/cppc_acpi.h>

@@ -49,6 +50,8 @@
 
 #define AMD_PSTATE_TRANSITION_LATENCY	20000
 #define AMD_PSTATE_TRANSITION_DELAY	1000
+#define AMD_PSTATE_PREFCORE_THRESHOLD	166
+#define AMD_PSTATE_MAX_CPPC_PERF	255
 
 /*
  * TODO: We need more time to fine tune processors with shared memory solution

@@ -65,6 +68,9 @@ static struct cpufreq_driver amd_pstate_epp_driver;
 static int cppc_state = AMD_PSTATE_UNDEFINED;
 static bool cppc_enabled;
 
+/*Preferred Core featue is supported*/
+static bool prefcore = true;
+
 /*
  * AMD Energy Preference Performance (EPP)
  * The EPP is used in the CCLK DPM controller to drive

@@ -290,23 +296,21 @@ static inline int amd_pstate_enable(bool enable)
 static int pstate_init_perf(struct amd_cpudata *cpudata)
 {
 	u64 cap1;
-	u32 highest_perf;
 
 	int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
 				     &cap1);
 	if (ret)
 		return ret;
 
-	/*
-	 * TODO: Introduce AMD specific power feature.
-	 *
-	 * CPPC entry doesn't indicate the highest performance in some ASICs.
+	/* For platforms that do not support the preferred core feature, the
+	 * highest_pef may be configured with 166 or 255, to avoid max frequency
+	 * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as
+	 * the default max perf.

drivers/cpufreq/amd-pstate.c static inline int amd_pstate_enable(bool enable) · line 313

Quoted 10 lines
drivers/cpufreq/amd-pstate.c +4 -5
 	 */
-	highest_perf = amd_get_highest_perf();
-	if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1))
-		highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
-
-	WRITE_ONCE(cpudata->highest_perf, highest_perf);
+	if (prefcore)
+		WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD);
+	else
+		WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));

Can we disable preferred core in HW? If not then when we disable preferred core in software (via the cmd line param you have created), HW still gives core ranking through highest perf register/MSR. So, we have to filter the core ranking info form the highest perf register/MSR and set cpudata->highest_perf accordingly. IMO we should have two variables, one which indicated HW support and other one which indicates SW overwrite. In this function we should be checking only HW support.

Quoted 12 lines
drivers/cpufreq/amd-pstate.c +0 -1
 	WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));

@@ -318,17 +322,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
 static int cppc_init_perf(struct amd_cpudata *cpudata)
 {
 	struct cppc_perf_caps cppc_perf;
-	u32 highest_perf;
 
 	int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
 	if (ret)
 		return ret;

drivers/cpufreq/amd-pstate.c static int pstate_init_perf(struct amd_cpudata *cpudata) · line 333

Quoted 10 lines
drivers/cpufreq/amd-pstate.c +4 -5
 
-	highest_perf = amd_get_highest_perf();
-	if (highest_perf > cppc_perf.highest_perf)
-		highest_perf = cppc_perf.highest_perf;
-
-	WRITE_ONCE(cpudata->highest_perf, highest_perf);
+	if (prefcore)
+		WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD);
+	else
+		WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf);

Here also we should be checking only HW support.

Quoted 51 lines
drivers/cpufreq/amd-pstate.c +44 -0
 	WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf,

@@ -676,6 +678,72 @@ static void amd_perf_ctl_reset(unsigned int cpu)
 	wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);
 }
 
+/*
+ * Set AMD Pstate Preferred Core enable can't be done directly from cpufreq callbacks
+ * due to locking, so queue the work for later.
+ */
+static void amd_pstste_sched_prefcore_workfn(struct work_struct *work)
+{
+	sched_set_itmt_support();
+}
+static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn);
+
+/**
+ * Get the highest performance register value.
+ * @cpu: CPU from which to get highest performance.
+ * @highest_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf)
+{
+       int ret;
+
+       if (boot_cpu_has(X86_FEATURE_CPPC)) {
+               u64 cap1;
+
+               ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1);
+               if (ret)
+                       return ret;
+               WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
+       } else {
+               ret = cppc_get_highest_perf(cpu, highest_perf);
+       }
+
+       return (ret);
+}
+
+static void amd_pstate_init_prefcore(void)
+{
+	int cpu, ret;
+	u64 highest_perf;
+
+	if (!prefcore)
+		return;
+
+	for_each_online_cpu(cpu) {

drivers/cpufreq/amd-pstate.c static void amd_perf_ctl_reset(unsigned int cpu) · line 734

Quoted 10 lines
drivers/cpufreq/amd-pstate.c +10 -0
+		ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+		if (ret)
+			break;
+
+		sched_set_itmt_core_prio(highest_perf, cpu);
+
+		/* check if CPPC preferred core feature is enabled*/
+		if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) {
+			prefcore = false;
+			return;

255 is a valid core ranking right?

Thanks & Regards,
Wyes

Quoted 74 lines
drivers/cpufreq/amd-pstate.c +32 -0
+		}
+	}
+
+	/*
+	 * This code can be run during CPU online under the
+	 * CPU hotplug locks, so sched_set_amd_prefcore_support()
+	 * cannot be called from here.  Queue up a work item
+	 * to invoke it.
+	 */
+	schedule_work(&sched_prefcore_work);
+}
+
 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
 {
 	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;

@@ -1037,6 +1105,12 @@ static ssize_t status_store(struct device *a, struct device_attribute *b,
 	return ret < 0 ? ret : count;
 }
 
+static ssize_t prefcore_show(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled");
+}
+
 cpufreq_freq_attr_ro(amd_pstate_max_freq);
 cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
 

@@ -1044,6 +1118,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
 cpufreq_freq_attr_rw(energy_performance_preference);
 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 static DEVICE_ATTR_RW(status);
+static DEVICE_ATTR_RO(prefcore);
 
 static struct freq_attr *amd_pstate_attr[] = {
 	&amd_pstate_max_freq,

@@ -1063,6 +1138,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
 
 static struct attribute *pstate_global_attributes[] = {
 	&dev_attr_status.attr,
+	&dev_attr_prefcore.attr,
 	NULL
 };
 

@@ -1506,6 +1582,8 @@ static int __init amd_pstate_init(void)
 		}
 	}
 
+	amd_pstate_init_prefcore();
+
 	return ret;
 
 global_attr_free:

@@ -1527,7 +1605,17 @@ static int __init amd_pstate_param(char *str)
 
 	return amd_pstate_set_driver(mode_idx);
 }
+
+static int __init amd_prefcore_param(char *str)
+{
+	if (!strcmp(str, "disable"))
+		prefcore = false;
+
+	return 0;
+}
+
 early_param("amd_pstate", amd_pstate_param);
+early_param("amd_prefcore", amd_prefcore_param);
 
 MODULE_AUTHOR("Huang Rui <[email protected]>");
 MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");
Signature · 1 line
2.34.1
author
#7 lore raw

RE: [PATCH V3 3/7] cpufreq: amd-pstate: Enable AMD Pstate Preferred Core Supporting.

[AMD Official Use Only - General]

Hello Wyes:

Quoted 116 lines

-----Original Message-----
From: Karny, Wyes <[email protected]>
Sent: Thursday, August 24, 2023 2:48 PM
To: Meng, Li (Jassmine) <[email protected]>
Cc: Karny, Wyes <[email protected]>; Rafael J . Wysocki <[email protected]>; Huang, Ray <[email protected]>; linux- [email protected]; [email protected]; [email protected]; linux- [email protected]; Shuah Khan <[email protected]>; linux- [email protected]; Fontenot, Nathan <[email protected]>; Sharma, Deepak <[email protected]>; Deucher, Alexander <[email protected]>; Limonciello, Mario <[email protected]>; Huang, Shimmer <[email protected]>; Yuan, Perry <[email protected]>; Du, Xiaojian <[email protected]>; Viresh Kumar <[email protected]>; Borislav Petkov <[email protected]>
Subject: Re: [PATCH V3 3/7] cpufreq: amd-pstate: Enable AMD Pstate Preferred Core Supporting.

Hi Meng Li,

Quoted 50 lines · Meng Li

AMD Pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage. We call it AMD Pstate Preferrred Core.

Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. AMD Pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority.

The initial core rankings are set up by AMD Pstate when the system boots.

Add device attribute for preferred core states.

Add one new early parameter enable to allow user to enable the preferred core if the processor and power firmware can support preferred core feature.

Signed-off-by Perry Yuan <[email protected]>
Co-developed-by Perry Yuan <[email protected]>
Signed-off-by Meng Li <[email protected]>
Co-developed-by Meng Li <[email protected]>
Reviewed-by Mario Limonciello <[email protected]>
---
 drivers/cpufreq/amd-pstate.c | 120
++++++++++++++++++++++++++++++-----
 1 file changed, 104 insertions(+), 16 deletions(-)
(quoted diff) +0 -0

b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..d02305675f66 100644

drivers/cpufreq/amd-pstate.c +3 -0
@@ -37,6 +37,7 @@
 #include <linux/uaccess.h>
 #include <linux/static_call.h>
 #include <linux/amd-pstate.h>
+#include <linux/topology.h>
 
 #include <acpi/processor.h>
 #include <acpi/cppc_acpi.h>

@@ -49,6 +50,8 @@
 
 #define AMD_PSTATE_TRANSITION_LATENCY      20000
 #define AMD_PSTATE_TRANSITION_DELAY        1000
+#define AMD_PSTATE_PREFCORE_THRESHOLD      166
+#define AMD_PSTATE_MAX_CPPC_PERF   255
 
 /*
  * TODO: We need more time to fine tune processors with shared memory
Quoted 2 lines

solution @@ -65,6 +68,9 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state =

AMD_PSTATE_UNDEFINED;

Quoted 11 lines

static bool cppc_enabled;

drivers/cpufreq/amd-pstate.c +3 -0
+/*Preferred Core featue is supported*/ static bool prefcore = true;
+
 /*
  * AMD Energy Preference Performance (EPP)
  * The EPP is used in the CCLK DPM controller to drive @@ -290,23
+296,21 @@ static inline int amd_pstate_enable(bool enable)  static

int pstate_init_perf(struct amd_cpudata *cpudata)  {
    u64 cap1;
drivers/cpufreq/amd-pstate.c +0 -1
-   u32 highest_perf;

drivers/cpufreq/amd-pstate.c static inline int amd_pstate_enable(bool enable)

Quoted 10 lines
drivers/cpufreq/amd-pstate.c +0 -4
 
    int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
                                 &cap1);
    if (ret)
            return ret;
 
-   /*
-    * TODO: Introduce AMD specific power feature.
-    *
-    * CPPC entry doesn't indicate the highest performance in some

ASICs.

drivers/cpufreq/amd-pstate.c

Quoted 2 lines
drivers/cpufreq/amd-pstate.c +2 -0
+   /* For platforms that do not support the preferred core feature, the
+    * highest_pef may be configured with 166 or 255, to avoid max

frequency

Quoted 1 line

+ * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1)

value as

drivers/cpufreq/amd-pstate.c static inline int amd_pstate_enable(bool enable)

Quoted 9 lines
drivers/cpufreq/amd-pstate.c +3 -5
+    * the default max perf.
     */
-   highest_perf = amd_get_highest_perf();
-   if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1))
-           highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
-
-   WRITE_ONCE(cpudata->highest_perf, highest_perf);
+   if (prefcore)
+           WRITE_ONCE(cpudata->highest_perf,

AMD_PSTATE_PREFCORE_THRESHOLD);

drivers/cpufreq/amd-pstate.c

Quoted 2 lines
drivers/cpufreq/amd-pstate.c +2 -0
+   else
+           WRITE_ONCE(cpudata->highest_perf,

AMD_CPPC_HIGHEST_PERF(cap1));

Quoted 8 lines

Can we disable preferred core in HW? If not then when we disable preferred core in software (via the cmd line param you have created), HW still gives core ranking through highest perf register/MSR. So, we have to filter the core ranking info form the highest perf register/MSR and set cpudata->highest_perf accordingly. IMO we should have two variables, one which indicated HW support and other one which indicates SW overwrite. In this function we should be checking only HW support.

[Meng, Li (Jassmine)]
We use one variable 'prefcore' to check whether the preferred core is supported. When either HW or SW does not support preferred core, it will be set to false. When 'highest_perf' is 255, it indicates that HW does not support preferred core.

Quoted 166 lines
Quoted 2 lines
    WRITE_ONCE(cpudata->nominal_perf,

AMD_CPPC_NOMINAL_PERF(cap1));

Quoted 8 lines
    WRITE_ONCE(cpudata->lowest_nonlinear_perf,
AMD_CPPC_LOWNONLIN_PERF(cap1)); @@ -318,17 +322,15 @@ static int
pstate_init_perf(struct amd_cpudata *cpudata)  static int
cppc_init_perf(struct amd_cpudata *cpudata)  {
    struct cppc_perf_caps cppc_perf;
drivers/cpufreq/amd-pstate.c +0 -1
-   u32 highest_perf;
 
    int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);

drivers/cpufreq/amd-pstate.c static int pstate_init_perf(struct amd_cpudata *cpudata)

Quoted 10 lines
drivers/cpufreq/amd-pstate.c +2 -5
    if (ret)
            return ret;
 
-   highest_perf = amd_get_highest_perf();
-   if (highest_perf > cppc_perf.highest_perf)
-           highest_perf = cppc_perf.highest_perf;
-
-   WRITE_ONCE(cpudata->highest_perf, highest_perf);
+   if (prefcore)
+           WRITE_ONCE(cpudata->highest_perf,

AMD_PSTATE_PREFCORE_THRESHOLD);

drivers/cpufreq/amd-pstate.c

Quoted 2 lines
drivers/cpufreq/amd-pstate.c +2 -0
+   else
+           WRITE_ONCE(cpudata->highest_perf,

cppc_perf.highest_perf);

Here also we should be checking only HW support.

Quoted 50 lines
    WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
    WRITE_ONCE(cpudata->lowest_nonlinear_perf,
drivers/cpufreq/amd-pstate.c +44 -0
@@ -676,6 +678,72 @@ static void amd_perf_ctl_reset(unsigned int cpu)
    wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);  }
 
+/*
+ * Set AMD Pstate Preferred Core enable can't be done directly from
+cpufreq callbacks
+ * due to locking, so queue the work for later.
+ */
+static void amd_pstste_sched_prefcore_workfn(struct work_struct
+*work) {
+   sched_set_itmt_support();
+}
+static DECLARE_WORK(sched_prefcore_work,
+amd_pstste_sched_prefcore_workfn);
+
+/**
+ * Get the highest performance register value.
+ * @cpu: CPU from which to get highest performance.
+ * @highest_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf) {
+       int ret;
+
+       if (boot_cpu_has(X86_FEATURE_CPPC)) {
+               u64 cap1;
+
+               ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1);
+               if (ret)
+                       return ret;
+               WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
+       } else {
+               ret = cppc_get_highest_perf(cpu, highest_perf);
+       }
+
+       return (ret);
+}
+
+static void amd_pstate_init_prefcore(void) {
+   int cpu, ret;
+   u64 highest_perf;
+
+   if (!prefcore)
+           return;
+
+   for_each_online_cpu(cpu) {

drivers/cpufreq/amd-pstate.c static void amd_perf_ctl_reset(unsigned int cpu) · line 733

Quoted 10 lines
drivers/cpufreq/amd-pstate.c +10 -0
+           ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+           if (ret)
+                   break;
+
+           sched_set_itmt_core_prio(highest_perf, cpu);
+
+           /* check if CPPC preferred core feature is enabled*/
+           if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) {
+                   prefcore = false;
+                   return;

255 is a valid core ranking right?

Thanks & Regards,
Wyes

Quoted 4 lines
drivers/cpufreq/amd-pstate.c +4 -0
+           }
+   }
+
+   /*

drivers/cpufreq/amd-pstate.c static void amd_perf_ctl_reset(unsigned int cpu) · line 749

Quoted 10 lines
drivers/cpufreq/amd-pstate.c +8 -0
+    * This code can be run during CPU online under the
+    * CPU hotplug locks, so sched_set_amd_prefcore_support()
+    * cannot be called from here.  Queue up a work item
+    * to invoke it.
+    */
+   schedule_work(&sched_prefcore_work);
+}
+
 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)  {
    int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;

@@

drivers/cpufreq/amd-pstate.c static void amd_perf_ctl_reset(unsigned int cpu) · line 680

Quoted 1 line
drivers/cpufreq/amd-pstate.c +0 -1
-1037,6 +1105,12 @@ static ssize_t status_store(struct device *a, struct

device_attribute *b,

Quoted 55 lines
drivers/cpufreq/amd-pstate.c +17 -1
    return ret < 0 ? ret : count;
 }
 
+static ssize_t prefcore_show(struct device *dev,
+                              struct device_attribute *attr, char *buf) {
+   return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled"); }
+
 cpufreq_freq_attr_ro(amd_pstate_max_freq);
 cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);

@@ -1044,6 +1118,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
 cpufreq_freq_attr_rw(energy_performance_preference);
 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 static DEVICE_ATTR_RW(status);
+static DEVICE_ATTR_RO(prefcore);
 
 static struct freq_attr *amd_pstate_attr[] = {
    &amd_pstate_max_freq,

@@ -1063,6 +1138,7 @@ static struct freq_attr *amd_pstate_epp_attr[] =
 {
 
 static struct attribute *pstate_global_attributes[] = {
    &dev_attr_status.attr,
+   &dev_attr_prefcore.attr,
    NULL
 };

@@ -1506,6 +1582,8 @@ static int __init amd_pstate_init(void)
            }
    }
 
+   amd_pstate_init_prefcore();
+
    return ret;
 
 global_attr_free:

@@ -1527,7 +1605,17 @@ static int __init amd_pstate_param(char *str)
 
    return amd_pstate_set_driver(mode_idx);  }
+
+static int __init amd_prefcore_param(char *str) {
+   if (!strcmp(str, "disable"))
+           prefcore = false;
+
+   return 0;
+}
+
 early_param("amd_pstate", amd_pstate_param);
+early_param("amd_prefcore", amd_prefcore_param);
 
 MODULE_AUTHOR("Huang Rui <[email protected]>");
 MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");
--

2.34.1

author
#8 lore raw

PATCH v3 4/7 cpufreq: Add a notification message that the highest perf has changed

In reply to Meng Li

ACPI 6.5 section 8.4.6.1.1.1 specifies that Notify event 0x85 can be emmitted to cause the the OSPM to re-evaluate the highest performance register. Add support for this event.

Signed-off-by Meng Li <[email protected]>
Link https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#cpc-continuous-performance-control
---
 drivers/acpi/processor_driver.c |  6 ++++++
 drivers/cpufreq/cpufreq.c       | 13 +++++++++++++
 include/linux/cpufreq.h         |  4 ++++
 3 files changed, 23 insertions(+)
drivers/acpi/processor_driver.c +6 -0
index 4bd16b3f0781..29b2fb68a35d 100644
@@ -27,6 +27,7 @@
 #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80
 #define ACPI_PROCESSOR_NOTIFY_POWER	0x81
 #define ACPI_PROCESSOR_NOTIFY_THROTTLING	0x82
+#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED	0x85
 
 MODULE_AUTHOR("Paul Diefenbaugh");
 MODULE_DESCRIPTION("ACPI Processor Driver");

@@ -83,6 +84,11 @@ static void acpi_processor_notify(acpi_handle handle, u32 event, void *data)
 		acpi_bus_generate_netlink_event(device->pnp.device_class,
 						  dev_name(&device->dev), event, 0);
 		break;
+	case ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED:
+		cpufreq_update_highest_perf(pr->id);
+		acpi_bus_generate_netlink_event(device->pnp.device_class,
+						  dev_name(&device->dev), event, 0);
+		break;
 	default:
 		acpi_handle_debug(handle, "Unsupported event [0x%x]\n", event);
 		break;
drivers/cpufreq/cpufreq.c +13 -0
index 50bbc969ffe5..842357abfae6 100644
@@ -2675,6 +2675,19 @@ void cpufreq_update_limits(unsigned int cpu)
 }
 EXPORT_SYMBOL_GPL(cpufreq_update_limits);
 
+/**
+ * cpufreq_update_highest_perf - Update highest performance for a given CPU.
+ * @cpu: CPU to update the highest performance for.
+ *
+ * Invoke the driver's ->update_highest_perf callback if present
+ */
+void cpufreq_update_highest_perf(unsigned int cpu)
+{
+	if (cpufreq_driver->update_highest_perf)
+		cpufreq_driver->update_highest_perf(cpu);
+}
+EXPORT_SYMBOL_GPL(cpufreq_update_highest_perf);
+
 /*********************************************************************
  *               BOOST						     *
  *********************************************************************/
include/linux/cpufreq.h +4 -0
index 9bf94ae08158..58106b3d9183 100644
@@ -232,6 +232,7 @@ int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu);
 void refresh_frequency_limits(struct cpufreq_policy *policy);
 void cpufreq_update_policy(unsigned int cpu);
 void cpufreq_update_limits(unsigned int cpu);
+void cpufreq_update_highest_perf(unsigned int cpu);
 bool have_governor_per_policy(void);
 bool cpufreq_supports_freq_invariance(void);
 struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy);

@@ -377,6 +378,9 @@ struct cpufreq_driver {
 	/* Called to update policy limits on firmware notifications. */
 	void		(*update_limits)(unsigned int cpu);
 
+	/* Called to update highest performance on firmware notifications. */
+	void		(*update_highest_perf)(unsigned int cpu);
+
 	/* optional */
 	int		(*bios_limit)(int cpu, unsigned int *limit);
Signature · 1 line
2.34.1
#9 lore raw

Re: [PATCH V3 4/7] cpufreq: Add a notification message that the highest perf has changed

Quoted 73 lines · Meng Li

ACPI 6.5 section 8.4.6.1.1.1 specifies that Notify event 0x85 can be emmitted to cause the the OSPM to re-evaluate the highest performance register. Add support for this event.

Signed-off-by Meng Li <[email protected]>
Link https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#cpc-continuous-performance-control
---
 drivers/acpi/processor_driver.c |  6 ++++++
 drivers/cpufreq/cpufreq.c       | 13 +++++++++++++
 include/linux/cpufreq.h         |  4 ++++
 3 files changed, 23 insertions(+)
drivers/acpi/processor_driver.c +6 -0
index 4bd16b3f0781..29b2fb68a35d 100644
@@ -27,6 +27,7 @@
 #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80
 #define ACPI_PROCESSOR_NOTIFY_POWER	0x81
 #define ACPI_PROCESSOR_NOTIFY_THROTTLING	0x82
+#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED	0x85
 
 MODULE_AUTHOR("Paul Diefenbaugh");
 MODULE_DESCRIPTION("ACPI Processor Driver");

@@ -83,6 +84,11 @@ static void acpi_processor_notify(acpi_handle handle, u32 event, void *data)
 		acpi_bus_generate_netlink_event(device->pnp.device_class,
 						  dev_name(&device->dev), event, 0);
 		break;
+	case ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED:
+		cpufreq_update_highest_perf(pr->id);
+		acpi_bus_generate_netlink_event(device->pnp.device_class,
+						  dev_name(&device->dev), event, 0);
+		break;
 	default:
 		acpi_handle_debug(handle, "Unsupported event [0x%x]\n", event);
 		break;
drivers/cpufreq/cpufreq.c +13 -0
index 50bbc969ffe5..842357abfae6 100644
@@ -2675,6 +2675,19 @@ void cpufreq_update_limits(unsigned int cpu)
 }
 EXPORT_SYMBOL_GPL(cpufreq_update_limits);
 
+/**
+ * cpufreq_update_highest_perf - Update highest performance for a given CPU.
+ * @cpu: CPU to update the highest performance for.
+ *
+ * Invoke the driver's ->update_highest_perf callback if present
+ */
+void cpufreq_update_highest_perf(unsigned int cpu)
+{
+	if (cpufreq_driver->update_highest_perf)
+		cpufreq_driver->update_highest_perf(cpu);
+}
+EXPORT_SYMBOL_GPL(cpufreq_update_highest_perf);
+
 /*********************************************************************
  *               BOOST						     *
  *********************************************************************/
include/linux/cpufreq.h +1 -0
index 9bf94ae08158..58106b3d9183 100644
@@ -232,6 +232,7 @@ int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu);
 void refresh_frequency_limits(struct cpufreq_policy *policy);
 void cpufreq_update_policy(unsigned int cpu);
 void cpufreq_update_limits(unsigned int cpu);
+void cpufreq_update_highest_perf(unsigned int cpu);
 bool have_governor_per_policy(void);
 bool cpufreq_supports_freq_invariance(void);
 struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy);

include/linux/cpufreq.h struct cpufreq_driver { · line 383

Quoted 6 lines
include/linux/cpufreq.h +3 -0
@@ -377,6 +378,9 @@ struct cpufreq_driver {
 	/* Called to update policy limits on firmware notifications. */
 	void		(*update_limits)(unsigned int cpu);
 
+	/* Called to update highest performance on firmware notifications. */
+	void		(*update_highest_perf)(unsigned int cpu);
+

Can we use the existing update_limits callback?

Thanks,
Wyes

Quoted 6 lines
include/linux/cpufreq.h +0 -0
 	/* optional */
 	int		(*bios_limit)(int cpu, unsigned int *limit);
Signature · 1 line
2.34.1
author
#10 lore raw

RE: [PATCH V3 4/7] cpufreq: Add a notification message that the highest perf has changed

[AMD Official Use Only - General]

Hello Wyes:

Quoted 108 lines

-----Original Message-----
From: Karny, Wyes <[email protected]>
Sent: Thursday, August 24, 2023 7:19 PM
To: Meng, Li (Jassmine) <[email protected]>
Cc: Karny, Wyes <[email protected]>; Rafael J . Wysocki <[email protected]>; Huang, Ray <[email protected]>; linux- [email protected]; [email protected]; [email protected]; linux- [email protected]; Shuah Khan <[email protected]>; linux- [email protected]; Fontenot, Nathan <[email protected]>; Sharma, Deepak <[email protected]>; Deucher, Alexander <[email protected]>; Limonciello, Mario <[email protected]>; Huang, Shimmer <[email protected]>; Yuan, Perry <[email protected]>; Du, Xiaojian <[email protected]>; Viresh Kumar <[email protected]>; Borislav Petkov <[email protected]>
Subject: Re: [PATCH V3 4/7] cpufreq: Add a notification message that the highest perf has changed

Quoted 27 lines · Meng Li

ACPI 6.5 section 8.4.6.1.1.1 specifies that Notify event 0x85 can be emmitted to cause the the OSPM to re-evaluate the highest performance register. Add support for this event.

Signed-off-by Meng Li <[email protected]>

Link:
https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control
.html?highlight=cppc#cpc-continuous-performance-control

---
 drivers/acpi/processor_driver.c |  6 ++++++
 drivers/cpufreq/cpufreq.c       | 13 +++++++++++++
 include/linux/cpufreq.h         |  4 ++++
 3 files changed, 23 insertions(+)
(quoted diff) +0 -0

b/drivers/acpi/processor_driver.c index 4bd16b3f0781..29b2fb68a35d 100644

drivers/acpi/processor_driver.c +1 -0
@@ -27,6 +27,7 @@
 #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80
 #define ACPI_PROCESSOR_NOTIFY_POWER        0x81
 #define ACPI_PROCESSOR_NOTIFY_THROTTLING   0x82
+#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED  0x85
 
 MODULE_AUTHOR("Paul Diefenbaugh");
 MODULE_DESCRIPTION("ACPI Processor Driver"); @@ -83,6 +84,11 @@
Quoted 1 line

static void acpi_processor_notify(acpi_handle handle, u32 event, void

*data)

Quoted 2 lines
            acpi_bus_generate_netlink_event(device->pnp.device_class,
                                              dev_name(&device->dev),

event, 0);

drivers/acpi/processor_driver.c static void acpi_processor_notify(acpi_handle handle, u32 event, void *data)

Quoted 5 lines
            break;
drivers/acpi/processor_driver.c +4 -0
+   case ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED:
+           cpufreq_update_highest_perf(pr->id);
+           acpi_bus_generate_netlink_event(device->pnp.device_class,
+                                             dev_name(&device->dev),

event, 0);

Quoted 3 lines
+           break;
    default:
            acpi_handle_debug(handle, "Unsupported event [0x%x]\n",

event);

drivers/cpufreq/cpufreq.c void cpufreq_update_limits(unsigned int cpu) } · line 2678

Quoted 10 lines
            break;
drivers/cpufreq/cpufreq.c +2 -0
index 50bbc969ffe5..842357abfae6 100644
@@ -2675,6 +2675,19 @@ void cpufreq_update_limits(unsigned int cpu)  }
 EXPORT_SYMBOL_GPL(cpufreq_update_limits);
 
+/**
+ * cpufreq_update_highest_perf - Update highest performance for a

given CPU.

drivers/cpufreq/cpufreq.c void cpufreq_update_limits(unsigned int cpu)

Quoted 10 lines
drivers/cpufreq/cpufreq.c +9 -0
+ * @cpu: CPU to update the highest performance for.
+ *
+ * Invoke the driver's ->update_highest_perf callback if present  */
+void cpufreq_update_highest_perf(unsigned int cpu) {
+   if (cpufreq_driver->update_highest_perf)
+           cpufreq_driver->update_highest_perf(cpu);
+}
+EXPORT_SYMBOL_GPL(cpufreq_update_highest_perf);
+

/**********************************************************
***********

drivers/cpufreq/cpufreq.c void cpufreq_update_limits(unsigned int cpu) } · line 2691

Quoted 3 lines
drivers/cpufreq/cpufreq.c +0 -0
  *               BOOST                                                  *

**********************************************************
***********/

Quoted 12 lines
include/linux/cpufreq.h index renamed from include/linux/cpufreq.h +0 -0

9bf94ae08158..58106b3d9183 100644

include/linux/cpufreq.h +0 -0
@@ -232,6 +232,7 @@ int cpufreq_get_policy(struct cpufreq_policy
 *policy, unsigned int cpu);  void refresh_frequency_limits(struct

cpufreq_policy *policy); void cpufreq_update_policy(unsigned int cpu); void cpufreq_update_limits(unsigned int cpu); +void cpufreq_update_highest_perf(unsigned int cpu);
bool have_governor_per_policy(void);
bool cpufreq_supports_freq_invariance(void);
struct kobject *get_governor_parent_kobj(struct cpufreq_policy

Quoted 5 lines
*policy); @@ -377,6 +378,9 @@ struct cpufreq_driver {
    /* Called to update policy limits on firmware notifications. */
    void            (*update_limits)(unsigned int cpu);

+ /* Called to update highest performance on firmware notifications.

*/

Quoted 7 lines

include/linux/cpufreq.h struct cpufreq_driver { · line 383

Quoted 2 lines
include/linux/cpufreq.h +2 -0
+   void            (*update_highest_perf)(unsigned int cpu);
+

Can we use the existing update_limits callback?

Thanks,
Wyes

[Meng, Li (Jassmine)]
I think there is a difference between the two functions.
When ACPI received ACPI_PROCESSOR_NOTIFY_PERFORMANCE event, it will call 'update_limits' to update policy data. However 'update_highest_perf' handles the message ACPI_PROCESSOR_NOTIFY_HIGHEST_PERF_CHANGED.

Quoted 6 lines
Quoted 6 lines
    /* optional */
    int             (*bios_limit)(int cpu, unsigned int *limit);

--
2.34.1

author
#11 lore raw

PATCH v3 5/7 cpufreq: amd-pstate: Update AMD Pstate Preferred Core ranking dynamically

In reply to Meng Li

Preferred core rankings can be changed dynamically by the platform based on the workload and platform conditions and accounting for thermals and aging.
When this occurs, cpu priority need to be set.

Signed-off-by Meng Li <[email protected]>
---
 drivers/cpufreq/amd-pstate.c | 32 ++++++++++++++++++++++++++++++++
 include/linux/amd-pstate.h   |  1 +
 2 files changed, 33 insertions(+)
drivers/cpufreq/amd-pstate.c +32 -0
index d02305675f66..8a8e4ecb1b5c 100644
@@ -315,6 +315,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
 	WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));
 	WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1));
+	WRITE_ONCE(cpudata->prefcore_highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
 
 	return 0;
 }

@@ -336,6 +337,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata)
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf,
 		   cppc_perf.lowest_nonlinear_perf);
 	WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
+	WRITE_ONCE(cpudata->prefcore_highest_perf, cppc_perf.highest_perf);
 
 	if (cppc_state == AMD_PSTATE_ACTIVE)
 		return 0;

@@ -744,6 +746,34 @@ static void amd_pstate_init_prefcore(void)
 	schedule_work(&sched_prefcore_work);
 }
 
+static void amd_pstate_update_highest_perf(unsigned int cpu)
+{
+	struct cpufreq_policy *policy;
+	struct amd_cpudata *cpudata;
+	u32 prev_high = 0, cur_high = 0;
+	u64 highest_perf;
+	int ret;
+
+	if (!prefcore)
+		return;
+
+	ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+	if (ret)
+		return;
+
+	policy = cpufreq_cpu_get(cpu);
+	cpudata = policy->driver_data;
+	cur_high = highest_perf;
+	prev_high = READ_ONCE(cpudata->prefcore_highest_perf);
+
+	if (prev_high != cur_high) {
+		WRITE_ONCE(cpudata->prefcore_highest_perf, cur_high);
+		sched_set_itmt_core_prio(cur_high, cpu);
+	}
+
+	cpufreq_cpu_put(policy);
+}
+
 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
 {
 	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;

@@ -1468,6 +1498,7 @@ static struct cpufreq_driver amd_pstate_driver = {
 	.suspend	= amd_pstate_cpu_suspend,
 	.resume		= amd_pstate_cpu_resume,
 	.set_boost	= amd_pstate_set_boost,
+	.update_highest_perf	= amd_pstate_update_highest_perf,
 	.name		= "amd-pstate",
 	.attr		= amd_pstate_attr,
 };

@@ -1482,6 +1513,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = {
 	.online		= amd_pstate_epp_cpu_online,
 	.suspend	= amd_pstate_epp_suspend,
 	.resume		= amd_pstate_epp_resume,
+	.update_highest_perf	= amd_pstate_update_highest_perf,
 	.name		= "amd-pstate-epp",
 	.attr		= amd_pstate_epp_attr,
 };
include/linux/amd-pstate.h +1 -0
index 446394f84606..fa86bc953d3e 100644
@@ -70,6 +70,7 @@ struct amd_cpudata {
 	u32	nominal_perf;
 	u32	lowest_nonlinear_perf;
 	u32	lowest_perf;
+	u32     prefcore_highest_perf;
 
 	u32	max_freq;
 	u32	min_freq;
Signature · 1 line
2.34.1
Reviewed-by on v3 5/7
#12 lore raw

Re: [PATCH V3 5/7] cpufreq: amd-pstate: Update AMD Pstate Preferred Core ranking dynamically

Quoted 75 lines · Meng Li

Preferred core rankings can be changed dynamically by the platform based on the workload and platform conditions and accounting for thermals and aging.
When this occurs, cpu priority need to be set.

Signed-off-by Meng Li <[email protected]>
---
 drivers/cpufreq/amd-pstate.c | 32 ++++++++++++++++++++++++++++++++
 include/linux/amd-pstate.h   |  1 +
 2 files changed, 33 insertions(+)
drivers/cpufreq/amd-pstate.c +31 -0
index d02305675f66..8a8e4ecb1b5c 100644
@@ -315,6 +315,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
 	WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));
 	WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1));
+	WRITE_ONCE(cpudata->prefcore_highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
 
 	return 0;
 }

@@ -336,6 +337,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata)
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf,
 		   cppc_perf.lowest_nonlinear_perf);
 	WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
+	WRITE_ONCE(cpudata->prefcore_highest_perf, cppc_perf.highest_perf);
 
 	if (cppc_state == AMD_PSTATE_ACTIVE)
 		return 0;

@@ -744,6 +746,34 @@ static void amd_pstate_init_prefcore(void)
 	schedule_work(&sched_prefcore_work);
 }
 
+static void amd_pstate_update_highest_perf(unsigned int cpu)
+{
+	struct cpufreq_policy *policy;
+	struct amd_cpudata *cpudata;
+	u32 prev_high = 0, cur_high = 0;
+	u64 highest_perf;
+	int ret;
+
+	if (!prefcore)
+		return;
+
+	ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+	if (ret)
+		return;
+
+	policy = cpufreq_cpu_get(cpu);
+	cpudata = policy->driver_data;
+	cur_high = highest_perf;
+	prev_high = READ_ONCE(cpudata->prefcore_highest_perf);
+
+	if (prev_high != cur_high) {
+		WRITE_ONCE(cpudata->prefcore_highest_perf, cur_high);
+		sched_set_itmt_core_prio(cur_high, cpu);
+	}
+
+	cpufreq_cpu_put(policy);
+}
+
 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
 {
 	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;

@@ -1468,6 +1498,7 @@ static struct cpufreq_driver amd_pstate_driver = {
 	.suspend	= amd_pstate_cpu_suspend,
 	.resume		= amd_pstate_cpu_resume,
 	.set_boost	= amd_pstate_set_boost,
+	.update_highest_perf	= amd_pstate_update_highest_perf,
 	.name		= "amd-pstate",
 	.attr		= amd_pstate_attr,
 };

drivers/cpufreq/amd-pstate.c static struct cpufreq_driver amd_pstate_epp_driver = { · line 1518

Quoted 6 lines
drivers/cpufreq/amd-pstate.c +1 -0
@@ -1482,6 +1513,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = {
 	.online		= amd_pstate_epp_cpu_online,
 	.suspend	= amd_pstate_epp_suspend,
 	.resume		= amd_pstate_epp_resume,
+	.update_highest_perf	= amd_pstate_update_highest_perf,
 	.name		= "amd-pstate-epp",
 	.attr		= amd_pstate_epp_attr,

If we intend to use the existing update_limits callback then this patch needed to update. Otherwise looks good to me.

Reviewed-by Wyes Karny <[email protected]>
Quoted 16 lines
drivers/cpufreq/amd-pstate.c +0 -0
 };
include/linux/amd-pstate.h +1 -0
index 446394f84606..fa86bc953d3e 100644
@@ -70,6 +70,7 @@ struct amd_cpudata {
 	u32	nominal_perf;
 	u32	lowest_nonlinear_perf;
 	u32	lowest_perf;
+	u32     prefcore_highest_perf;
 
 	u32	max_freq;
 	u32	min_freq;
Signature · 1 line
2.34.1
author
#13 lore raw

PATCH v3 6/7 Documentation: amd-pstate: introduce AMD Pstate Preferred Core

In reply to Meng Li

Introduce AMD Pstate Preferred Core.

check preferred core state:

$ cat /sys/devices/system/cpu/amd-pstate/prefcore
Signed-off-by Meng Li <[email protected]>
---
 Documentation/admin-guide/pm/amd-pstate.rst | 53 +++++++++++++++++++++
 1 file changed, 53 insertions(+)
Documentation/admin-guide/pm/amd-pstate.rst +53 -0
index 1cf40f69278c..2369b58a3521 100644
@@ -353,6 +353,47 @@ is activated.  In this mode, driver requests minimum and maximum performance
 level and the platform autonomously selects a performance level in this range
 and appropriate to the current workload.
 
+AMD Pstate Preferred Core
+=================================
+
+The core frequency is subjected to the process variation in semiconductors.
+Not all cores are able to reach the maximum frequency respecting the
+infrastructure limits. Consequently, AMD has redefined the concept of
+maximum frequency of a part. This means that a fraction of cores can reach
+maximum frequency. To find the best process scheduling policy for a given
+scenario, OS needs to know the core ordering informed by the platform through
+highest performance capability register of the CPPC interface.
+
+``AMD Pstate Preferred Core`` enable the scheduler to favor scheduling on cores
+can be get a higher frequency with lower voltage under preferred core.
+And it has the ability to dynamically change the preferred core based on the
+workload and platform conditions and accounting for thermals and aging.
+
+The priority metric will be initialized by the AMD Pstate driver. The AMD Pstate
+driver will also determine whether or not ``AMD Pstate Preferred Core`` is
+supported by the platform.
+
+AMD Pstate driver will provide an initial core ordering when the system boots.
+The platform uses the CPPC interfaces to communicate the core ranking to the
+operating system and scheduler to make sure that OS is choosing the cores
+with highest performance firstly for scheduling the process. When AMD Pstate
+driver receives a message with the highest performance change, it will
+update the core ranking and set the cpu's priority.
+
+AMD Preferred Core Switch
+=================================
+Kernel Parameters
+-----------------
+
+``AMD Pstate Preferred Core`` has two states: enable and disable.
+Enable/disable states can be chosen by different kernel parameters.
+Default enable ``AMD Pstate Preferred Core``.
+
+``amd_prefcore=disable``
+
+``AMD Pstate Preferred Core`` will be enabled if the underlying platform
+supports it. It can be disabled by kernerl parameter: ``amd_prefcore=disable``.
+
 User Space Interface in ``sysfs`` - General
 ===========================================
 

@@ -385,6 +426,18 @@ control its functionality at the system level.  They are located in the
         to the operation mode represented by that string - or to be
         unregistered in the "disable" case.
 
+``prefcore``
+	Preferred Core state of the driver: "enabled" or "disabled".
+
+	"enabled"
+		Enable the AMD Preferred Core.
+
+	"disabled"
+		Disable the AMD Preferred Core
+
+
+        This attribute is read-only to check the state of Preferred Core.
+
 ``cpupower`` tool support for ``amd-pstate``
 ===============================================
Signature · 1 line
2.34.1
#14 lore raw

Re: [PATCH V3 6/7] Documentation: amd-pstate: introduce AMD Pstate Preferred Core

Quoted 19 lines · Meng Li

Introduce AMD Pstate Preferred Core.

check preferred core state:

$ cat /sys/devices/system/cpu/amd-pstate/prefcore
Signed-off-by Meng Li <[email protected]>
---
 Documentation/admin-guide/pm/amd-pstate.rst | 53 +++++++++++++++++++++
 1 file changed, 53 insertions(+)
Documentation/admin-guide/pm/amd-pstate.rst +1 -0
index 1cf40f69278c..2369b58a3521 100644
@@ -353,6 +353,47 @@ is activated.  In this mode, driver requests minimum and maximum performance
 level and the platform autonomously selects a performance level in this range
 and appropriate to the current workload.
 
+AMD Pstate Preferred Core

Documentation/admin-guide/pm/amd-pstate.rst is activated. In this mode, driver requests minimum and maximum performance · line 366

Quoted 10 lines
Documentation/admin-guide/pm/amd-pstate.rst +10 -0
+=================================
+
+The core frequency is subjected to the process variation in semiconductors.
+Not all cores are able to reach the maximum frequency respecting the
+infrastructure limits. Consequently, AMD has redefined the concept of
+maximum frequency of a part. This means that a fraction of cores can reach
+maximum frequency. To find the best process scheduling policy for a given
+scenario, OS needs to know the core ordering informed by the platform through
+highest performance capability register of the CPPC interface.
+

---------------------------->8----------------------------------

Documentation/admin-guide/pm/amd-pstate.rst is activated. In this mode, driver requests minimum and maximum performance · line 370

Quoted 4 lines
Documentation/admin-guide/pm/amd-pstate.rst +4 -0
+``AMD Pstate Preferred Core`` enable the scheduler to favor scheduling on cores
+can be get a higher frequency with lower voltage under preferred core.
+And it has the ability to dynamically change the preferred core based on the
+workload and platform conditions and accounting for thermals and aging.

Can we reword this like below:

``AMD Pstate Preferred Core`` enables the scheduler to prefer scheduling on cores that can achieve a higher frequency with lower voltage. The preferred core rankings can dynamically change based on the workload, platform conditions, thermals and ageing.

Quoted 7 lines
Documentation/admin-guide/pm/amd-pstate.rst +7 -0
+
+The priority metric will be initialized by the AMD Pstate driver. The AMD Pstate
+driver will also determine whether or not ``AMD Pstate Preferred Core`` is
+supported by the platform.
+
+AMD Pstate driver will provide an initial core ordering when the system boots.
+The platform uses the CPPC interfaces to communicate the core ranking to the

Documentation/admin-guide/pm/amd-pstate.rst is activated. In this mode, driver requests minimum and maximum performance · line 387

Quoted 10 lines
Documentation/admin-guide/pm/amd-pstate.rst +10 -0
+operating system and scheduler to make sure that OS is choosing the cores
+with highest performance firstly for scheduling the process. When AMD Pstate
+driver receives a message with the highest performance change, it will
+update the core ranking and set the cpu's priority.
+
+AMD Preferred Core Switch
+=================================
+Kernel Parameters
+-----------------
+

----------------------------->8------------------------------

Documentation/admin-guide/pm/amd-pstate.rst is activated. In this mode, driver requests minimum and maximum performance · line 395

Quoted 8 lines
Documentation/admin-guide/pm/amd-pstate.rst +8 -0
+``AMD Pstate Preferred Core`` has two states: enable and disable.
+Enable/disable states can be chosen by different kernel parameters.
+Default enable ``AMD Pstate Preferred Core``.
+
+``amd_prefcore=disable``
+
+``AMD Pstate Preferred Core`` will be enabled if the underlying platform
+supports it. It can be disabled by kernerl parameter: ``amd_prefcore=disable``.

Can we re-word this like below:

``amd_prefcore=disable``

For systems that support ``AMD Pstate Preferred Core``, the core rankings will always be advertised by the platform. But OS can choose to ignore that via the kernel parameter ``amd_prefcore=disable``.

Thanks,
Wyes

Quoted 26 lines
Documentation/admin-guide/pm/amd-pstate.rst +13 -0
+
 User Space Interface in ``sysfs`` - General
 ===========================================
 

@@ -385,6 +426,18 @@ control its functionality at the system level.  They are located in the
         to the operation mode represented by that string - or to be
         unregistered in the "disable" case.
 
+``prefcore``
+	Preferred Core state of the driver: "enabled" or "disabled".
+
+	"enabled"
+		Enable the AMD Preferred Core.
+
+	"disabled"
+		Disable the AMD Preferred Core
+
+
+        This attribute is read-only to check the state of Preferred Core.
+
 ``cpupower`` tool support for ``amd-pstate``
 ===============================================
Signature · 1 line
2.34.1
author
#15 lore raw

PATCH v3 7/7 Documentation: introduce AMD Pstate Preferrd Core mode kernel command line options

In reply to Meng Li

AMD Pstate driver support enable/disable Preferred core. Default enabled on platforms supporting AMD Preferred Core. Disable AMD Pstate Preferred Core with "amd_prefcore=disable" added to the kernel command line.

Signed-off-by Meng Li <[email protected]>
Reviewed-by Mario Limonciello <[email protected]>
---
 Documentation/admin-guide/kernel-parameters.txt | 5 +++++
 1 file changed, 5 insertions(+)
Documentation/admin-guide/kernel-parameters.txt +5 -0
index 23ebe34ff901..4f78067bb8af 100644
@@ -363,6 +363,11 @@
 			  selects a performance level in this range and appropriate
 			  to the current workload.
 
+	amd_prefcore=
+			[X86]
+			disable
+			  Disable AMD Pstate Preferred Core.
+
 	amijoy.map=	[HW,JOY] Amiga joystick support
 			Map of devices attached to JOY0DAT and JOY1DAT
 			Format: <a>,<b>
Signature · 1 line
2.34.1
Reviewed-by on v3 7/7
#16 lore raw

Re: [PATCH V3 7/7] Documentation: introduce AMD Pstate Preferrd Core mode kernel command line options

Quoted 7 lines · Meng Li

AMD Pstate driver support enable/disable Preferred core. Default enabled on platforms supporting AMD Preferred Core. Disable AMD Pstate Preferred Core with "amd_prefcore=disable" added to the kernel command line.

Signed-off-by Meng Li <[email protected]>
Reviewed-by Mario Limonciello <[email protected]>
Reviewed-by Wyes Karny <[email protected]>
Quoted 23 lines
---
 Documentation/admin-guide/kernel-parameters.txt | 5 +++++
 1 file changed, 5 insertions(+)
Documentation/admin-guide/kernel-parameters.txt +5 -0
index 23ebe34ff901..4f78067bb8af 100644
@@ -363,6 +363,11 @@
 			  selects a performance level in this range and appropriate
 			  to the current workload.
 
+	amd_prefcore=
+			[X86]
+			disable
+			  Disable AMD Pstate Preferred Core.
+
 	amijoy.map=	[HW,JOY] Amiga joystick support
 			Map of devices attached to JOY0DAT and JOY1DAT
 			Format: <a>,<b>
Signature · 1 line
2.34.1
maintainer Reviewed-by on the v3 series
#17 lore raw
In reply to Meng Li
Quoted 68 lines · Meng Li

Hi all:

The core frequency is subjected to the process variation in semiconductors. Not all cores are able to reach the maximum frequency respecting the infrastructure limits. Consequently, AMD has redefined the concept of maximum frequency of a part. This means that a fraction of cores can reach maximum frequency. To find the best process scheduling policy for a given scenario, OS needs to know the core ordering informed by the platform through highest performance capability register of the CPPC interface.

Earlier implementations of AMD Pstate Preferred Core only support a static core ranking and targeted performance. Now it has the ability to dynamically change the preferred core based on the workload and platform conditions and accounting for thermals and aging.

AMD Pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage.
We call it AMD Pstate Preferrred Core.

Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. AMD Pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority.

AMD Pstate driver will provide an initial core ordering at boot time. It relies on the CPPC interface to communicate the core ranking to the operating system and scheduler to make sure that OS is choosing the cores with highest performance firstly for scheduling the process. When AMD Pstate driver receives a message with the highest performance change, it will update the core ranking.

Changes form V2->V3:
- x86:
- - Modify kconfig and description.
- cpufreq: amd-pstate:
- - Add Co-developed-by tag in commit message.
- cpufreq:
- - Modify commit message.
- Documentation: amd-pstate:
- - Modify inappropriate descriptions.

Changes form V1->V2:
- acpi: cppc:
- - Add reference link.
- cpufreq:
- - Moidfy link error.
- cpufreq: amd-pstate:
- - Init the priorities of all online CPUs
- - Use a single variable to represent the status of Preferred Core.
- Documentation:
- - Default enabled preferred core.
- Documentation: amd-pstate:
- - Modify inappropriate descriptions.
- - Default enabled preferred core.
- - Use a single variable to represent the status of Preferred Core.

Meng Li (7):
x86: Drop CPU_SUP_INTEL from SCHED_MC_PRIO for the expansion.
acpi: cppc: Add get the highest performance cppc control
cpufreq: amd-pstate: Enable AMD Pstate Preferred Core Supporting.
cpufreq: Add a notification message that the highest perf has changed
cpufreq: amd-pstate: Update AMD Pstate Preferred Core ranking
dynamically
Documentation: amd-pstate: introduce AMD Pstate Preferred Core
Documentation: introduce AMD Pstate Preferrd Core mode kernel command
line options

Quoted 12 lines
  .../admin-guide/kernel-parameters.txt         |   5 +
  Documentation/admin-guide/pm/amd-pstate.rst   |  53 ++++++
  arch/x86/Kconfig                              |   5 +-
  drivers/acpi/cppc_acpi.c                      |  13 ++
  drivers/acpi/processor_driver.c               |   6 +
  drivers/cpufreq/amd-pstate.c                  | 152 ++++++++++++++++--
  drivers/cpufreq/cpufreq.c                     |  13 ++
  include/acpi/cppc_acpi.h                      |   5 +
  include/linux/amd-pstate.h                    |   1 +
  include/linux/cpufreq.h                       |   4 +
  10 files changed, 239 insertions(+), 18 deletions(-)
Reviewed-by Mario Limonciello <[email protected]>