Add Milk-V Pioneer RISC-V board support

The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V cores.

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 arch/riscv/Kconfig.socs | 5 +++++
 1 file changed, 5 insertions(+)

arch/riscv/Kconfig.socs +0 -0

index 6833d01e2e70..d4df7b5d0f16 100644

arch/riscv/Kconfig.socs +0 -1

 config ARCH_STARFIVE
        def_bool SOC_STARFIVE
 
--

2.25.1

Add new vendor strings to dt bindings. These new vendor strings are used by
- Sophgo SG2042 SoC [1]
- Milk-V Pioneer board [2], which uses SG2042 chip.

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/vendor-prefixes.yaml +4 -1

index 573578db9509..fcca9e070a9a 100644
@@ -863,6 +863,8 @@ patternProperties:
     description: MikroElektronika d.o.o.
   "^mikrotik,.*":
     description: MikroTik
+  "^milkv,.*":
+    description: MilkV Technology Co., Ltd
   "^miniand,.*":
     description: Miniand Tech
   "^minix,.*":

@@ -1273,6 +1275,8 @@ patternProperties:
     description: Solomon Systech Limited
   "^sony,.*":
     description: Sony Corporation
+  "^sophgo,.*":
+    description: Sophgo Technology Inc.
   "^sourceparts,.*":
     description: Source Parts Inc.
   "^spansion,.*":
--

2.25.1

Add new vendor strings to dt bindings. These new vendor strings are used by
- Sophgo SG2042 SoC [1]
- Milk-V Pioneer board [2], which uses SG2042 chip.

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/vendor-prefixes.yaml +4 -0

index 573578db9509..fcca9e070a9a 100644
@@ -863,6 +863,8 @@ patternProperties:
     description: MikroElektronika d.o.o.
   "^mikrotik,.*":
     description: MikroTik
+  "^milkv,.*":
+    description: MilkV Technology Co., Ltd
   "^miniand,.*":
     description: Miniand Tech
   "^minix,.*":

@@ -1273,6 +1275,8 @@ patternProperties:
     description: Solomon Systech Limited
   "^sony,.*":
     description: Sony Corporation
+  "^sophgo,.*":
+    description: Sophgo Technology Inc.
   "^sourceparts,.*":
     description: Source Parts Inc.
   "^spansion,.*":

Signature · 1 line

2.25.1

Yo,

Quoted 5 lines · Chen Wang

Add new vendor strings to dt bindings. These new vendor strings are used by
- Sophgo SG2042 SoC [1]
- Milk-V Pioneer board [2], which uses SG2042 chip.

Quoted 2 lines

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

If you resend, make these link tags please. Otherwise,

Reviewed-by Conor Dooley <[email protected]>

Thanks,
Conor.

Quoted 31 lines

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/vendor-prefixes.yaml +4 -1

index 573578db9509..fcca9e070a9a 100644
@@ -863,6 +863,8 @@ patternProperties:
     description: MikroElektronika d.o.o.
   "^mikrotik,.*":
     description: MikroTik
+  "^milkv,.*":
+    description: MilkV Technology Co., Ltd
   "^miniand,.*":
     description: Miniand Tech
   "^minix,.*":

@@ -1273,6 +1275,8 @@ patternProperties:
     description: Solomon Systech Limited
   "^sony,.*":
     description: Sony Corporation
+  "^sophgo,.*":
+    description: Sophgo Technology Inc.
   "^sourceparts,.*":
     description: Source Parts Inc.
   "^spansion,.*":
--

2.25.1

Add DT binding documentation for the Sophgo SG2042 Soc [1] and the Milk-V Pioneer board [2].

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

Acked-by Chao Wei <[email protected]>

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
 MAINTAINERS                                   |  7 +++++
 2 files changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml

Documentation/devicetree/bindings/riscv/sophgo.yaml new file +28 -0

new file mode 100644
index 000000000000..82468ae915db
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SoC-based boards
+
+maintainers:
+  - Chao Wei <[email protected]>
+  - Xiaoguang Xing <[email protected]>
+
+description:
+  Sophgo SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - milkv,pioneer
+          - const: sophgo,sg2042
+
+additionalProperties: true
+
+...

MAINTAINERS +7 -1

index 90f13281d297..b74d505003e2 100644
@@ -20063,6 +20063,13 @@ F:     drivers/char/sonypi.c
 F:     drivers/platform/x86/sony-laptop.c
 F:     include/linux/sony-laptop.h
 
+SOPHGO DEVICETREES
+M:     Xiaoguang Xing <[email protected]>
+M:     Chao Wei <[email protected]>
+S:     Maintained
+F:     Documentation/devicetree/bindings/riscv/sophgo.yaml
+F:     arch/riscv/boot/dts/sophgo/
+
 SOUND
 M:     Jaroslav Kysela <[email protected]>
 M:     Takashi Iwai <[email protected]>
--

2.25.1

Add DT binding documentation for the Sophgo SG2042 Soc [1] and the Milk-V Pioneer board [2].

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

Acked-by Chao Wei <[email protected]>

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
 MAINTAINERS                                   |  7 +++++
 2 files changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml

Documentation/devicetree/bindings/riscv/sophgo.yaml new file +28 -0

new file mode 100644
index 000000000000..82468ae915db
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SoC-based boards
+
+maintainers:
+  - Chao Wei <[email protected]>
+  - Xiaoguang Xing <[email protected]>
+
+description:
+  Sophgo SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - milkv,pioneer
+          - const: sophgo,sg2042
+
+additionalProperties: true
+
+...

MAINTAINERS +0 -0

index 90f13281d297..b74d505003e2 100644

MAINTAINERS +1 -0

+
 SOUND
 M:	Jaroslav Kysela <[email protected]>

M: Takashi Iwai <[email protected]>

Signature · 1 line

2.25.1

Yo,

Quoted 5 lines · Chen Wang

Add DT binding documentation for the Sophgo SG2042 Soc [1] and the Milk-V Pioneer board [2].

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

Again, link tags please.

Quoted 48 lines

Acked-by Chao Wei <[email protected]>

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
 MAINTAINERS                                   |  7 +++++
 2 files changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml

Documentation/devicetree/bindings/riscv/sophgo.yaml new file +28 -0

new file mode 100644
index 000000000000..82468ae915db
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SoC-based boards
+
+maintainers:
+  - Chao Wei <[email protected]>
+  - Xiaoguang Xing <[email protected]>
+
+description:
+  Sophgo SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - milkv,pioneer
+          - const: sophgo,sg2042
+
+additionalProperties: true
+
+...

MAINTAINERS +0 -0

index 90f13281d297..b74d505003e2 100644

MAINTAINERS F: drivers/char/sonypi.c · line 20072

Quoted 10 lines

MAINTAINERS +6 -0

@@ -20063,6 +20063,13 @@ F:   drivers/char/sonypi.c
 F:   drivers/platform/x86/sony-laptop.c
 F:   include/linux/sony-laptop.h
 
+SOPHGO DEVICETREES
+M:   Xiaoguang Xing <[email protected]>
+M:   Chao Wei <[email protected]>
+S:   Maintained
+F:   Documentation/devicetree/bindings/riscv/sophgo.yaml
 
+F:   arch/riscv/boot/dts/sophgo/

Firstly, this directory does not exist at the time of this patch, so it should not be added here, but rather at the time that you create it.

Secondly, are Xiaoguang Xing and Chao Wei going to monitor the lists & apply patches for these files? If so, you should add a git tree here that they will apply patches to & add to linux-next. Also, I'd really like to see some on-list signs of life from these people, otherwise I'd rather see your name here instead of theirs.

If they don't intend reviewing/testing/applying patches, I can do it as a last resort but I would rather that someone who specifically cares for this hardware does it.

Thanks,
Conor.

Quoted 7 lines

MAINTAINERS +1 -0

+
 SOUND
 M:   Jaroslav Kysela <[email protected]>

M: Takashi Iwai <[email protected]>
--
2.25.1

Quoted 77 lines · Conor Dooley <[email protected]> 于2023年9月20日周三 16:29写道：

Quoted 5 lines · Chen Wang

Add DT binding documentation for the Sophgo SG2042 Soc [1] and the Milk-V Pioneer board [2].

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

Again, link tags please.

Quoted 48 lines

Acked-by Chao Wei <[email protected]>

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
 MAINTAINERS                                   |  7 +++++
 2 files changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml

Documentation/devicetree/bindings/riscv/sophgo.yaml new file +28 -0

new file mode 100644
index 000000000000..82468ae915db
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SoC-based boards
+
+maintainers:
+  - Chao Wei <[email protected]>
+  - Xiaoguang Xing <[email protected]>
+
+description:
+  Sophgo SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - milkv,pioneer
+          - const: sophgo,sg2042
+
+additionalProperties: true
+
+...

MAINTAINERS +0 -0

index 90f13281d297..b74d505003e2 100644

MAINTAINERS F: drivers/char/sonypi.c · line 20072

Quoted 10 lines

MAINTAINERS +6 -0

@@ -20063,6 +20063,13 @@ F:   drivers/char/sonypi.c
 F:   drivers/platform/x86/sony-laptop.c
 F:   include/linux/sony-laptop.h
 
+SOPHGO DEVICETREES
+M:   Xiaoguang Xing <[email protected]>
+M:   Chao Wei <[email protected]>
+S:   Maintained
+F:   Documentation/devicetree/bindings/riscv/sophgo.yaml
 
+F:   arch/riscv/boot/dts/sophgo/

Firstly, this directory does not exist at the time of this patch, so it should not be added here, but rather at the time that you create it.

Secondly, are Xiaoguang Xing and Chao Wei going to monitor the lists & apply patches for these files? If so, you should add a git tree here that they will apply patches to & add to linux-next. Also, I'd really like to see some on-list signs of life from these people, otherwise I'd rather see your name here instead of theirs.

Quoted 3 lines

If they don't intend reviewing/testing/applying patches, I can do it as a last resort but I would rather that someone who specifically cares for this hardware does it.

Please allow me to explain first. As a community volunteer, I actually had full discussions and testing with Sophgo people when submitting patches, so I added tag such "Acked-by: Xiaoguang Xing ..." to the signature part of most patches. Also if you think a formal email is required, I will talk them to send it.

As for the issue of MAINTAINERS, I discussed it with the people from Sophgo. They (including me also) feel that we are not very familiar with the community process (especially as maintainer, and actually I modify the file MAINTAINERS is just to suppress warning information when running checkpatch.pl), so we sincerely hope to invite you, Mr. Conor,

to help us for a period of time on maintenance work, including checking relevant patches, merging and submitting PRs, we will learn together with you for a while, and then take over this part of the work when we become familiar with it. We know that you are also very busy at work, especially if you don't have the hardware at hand. I have the hardware here and I can take the responsibility to run testing. What do you think? I'm waiting for your reply. Thanks in advance.

Quoted 82 lines · Chen Wang

Quoted 77 lines · Conor Dooley <[email protected]> 于2023年9月20日周三 16:29写道：

Quoted 5 lines · Chen Wang

Add DT binding documentation for the Sophgo SG2042 Soc [1] and the Milk-V Pioneer board [2].

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

Again, link tags please.

Quoted 48 lines

Acked-by Chao Wei <[email protected]>

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
 MAINTAINERS                                   |  7 +++++
 2 files changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml

Documentation/devicetree/bindings/riscv/sophgo.yaml new file +28 -0

new file mode 100644
index 000000000000..82468ae915db
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SoC-based boards
+
+maintainers:
+  - Chao Wei <[email protected]>
+  - Xiaoguang Xing <[email protected]>
+
+description:
+  Sophgo SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - milkv,pioneer
+          - const: sophgo,sg2042
+
+additionalProperties: true
+
+...

MAINTAINERS +0 -0

index 90f13281d297..b74d505003e2 100644

MAINTAINERS F: drivers/char/sonypi.c · line 20072

Quoted 10 lines

MAINTAINERS +6 -0

@@ -20063,6 +20063,13 @@ F:   drivers/char/sonypi.c
 F:   drivers/platform/x86/sony-laptop.c
 F:   include/linux/sony-laptop.h
 
+SOPHGO DEVICETREES
+M:   Xiaoguang Xing <[email protected]>
+M:   Chao Wei <[email protected]>
+S:   Maintained
+F:   Documentation/devicetree/bindings/riscv/sophgo.yaml
 
+F:   arch/riscv/boot/dts/sophgo/

Firstly, this directory does not exist at the time of this patch, so it should not be added here, but rather at the time that you create it.

Secondly, are Xiaoguang Xing and Chao Wei going to monitor the lists & apply patches for these files? If so, you should add a git tree here that they will apply patches to & add to linux-next. Also, I'd really like to see some on-list signs of life from these people, otherwise I'd rather see your name here instead of theirs.

Quoted 3 lines

If they don't intend reviewing/testing/applying patches, I can do it as a last resort but I would rather that someone who specifically cares for this hardware does it.

Quoted 5 lines

Please allow me to explain first. As a community volunteer, I actually had full discussions and testing with Sophgo people when submitting patches, so I added tag such "Acked-by: Xiaoguang Xing ..." to the signature part of most patches. Also if you think a formal email is required, I will talk them to send it.

No, I'm okay with the acks that are on these patches. I just want to make sure that those who are acking know why they are & am wondering why your name is not there, seeing as you're the one who has submitted these patches.

Quoted 6 lines

As for the issue of MAINTAINERS, I discussed it with the people from Sophgo. They (including me also) feel that we are not very familiar with the community process (especially as maintainer, and actually I modify the file MAINTAINERS is just to suppress warning information when running checkpatch.pl), so we sincerely hope to invite you, Mr. Conor,

Oh god, there's no need to call me "Mr. Conor". Conor will do perfectly fine!

Quoted 8 lines

to help us for a period of time on maintenance work, including checking relevant patches, merging and submitting PRs, we will learn together with you for a while, and then take over this part of the work when we become familiar with it. We know that you are also very busy at work, especially if you don't have the hardware at hand. I have the hardware here and I can take the responsibility to run testing. What do you think? I'm waiting for your reply. Thanks in advance.

That seems fine to me. In that case, you should add yourself to the MAINTAINERS entry.

Thanks,
Conor.

Quoted 82 lines · Chen Wang

Quoted 77 lines · Conor Dooley <[email protected]> 于2023年9月20日周三 16:29写道：

Quoted 5 lines · Chen Wang

Add DT binding documentation for the Sophgo SG2042 Soc [1] and the Milk-V Pioneer board [2].

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

Again, link tags please.

Quoted 48 lines

Acked-by Chao Wei <[email protected]>

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
 MAINTAINERS                                   |  7 +++++
 2 files changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml

Documentation/devicetree/bindings/riscv/sophgo.yaml new file +28 -0

new file mode 100644
index 000000000000..82468ae915db
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SoC-based boards
+
+maintainers:
+  - Chao Wei <[email protected]>
+  - Xiaoguang Xing <[email protected]>
+
+description:
+  Sophgo SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - milkv,pioneer
+          - const: sophgo,sg2042
+
+additionalProperties: true
+
+...

MAINTAINERS +0 -0

index 90f13281d297..b74d505003e2 100644

MAINTAINERS F: drivers/char/sonypi.c · line 20072

Quoted 10 lines

MAINTAINERS +6 -0

@@ -20063,6 +20063,13 @@ F:   drivers/char/sonypi.c
 F:   drivers/platform/x86/sony-laptop.c
 F:   include/linux/sony-laptop.h
 
+SOPHGO DEVICETREES
+M:   Xiaoguang Xing <[email protected]>
+M:   Chao Wei <[email protected]>
+S:   Maintained
+F:   Documentation/devicetree/bindings/riscv/sophgo.yaml
 
+F:   arch/riscv/boot/dts/sophgo/

Firstly, this directory does not exist at the time of this patch, so it should not be added here, but rather at the time that you create it.

Secondly, are Xiaoguang Xing and Chao Wei going to monitor the lists & apply patches for these files? If so, you should add a git tree here that they will apply patches to & add to linux-next. Also, I'd really like to see some on-list signs of life from these people, otherwise I'd rather see your name here instead of theirs.

Quoted 3 lines

If they don't intend reviewing/testing/applying patches, I can do it as a last resort but I would rather that someone who specifically cares for this hardware does it.

Quoted 5 lines

Please allow me to explain first. As a community volunteer, I actually had full discussions and testing with Sophgo people when submitting patches, so I added tag such "Acked-by: Xiaoguang Xing ..." to the signature part of most patches. Also if you think a formal email is required, I will talk them to send it.

No, I'm okay with the acks that are on these patches. I just want to make sure that those who are acking know why they are & am wondering why your name is not there, seeing as you're the one who has submitted these patches.

Quoted 6 lines

As for the issue of MAINTAINERS, I discussed it with the people from Sophgo. They (including me also) feel that we are not very familiar with the community process (especially as maintainer, and actually I modify the file MAINTAINERS is just to suppress warning information when running checkpatch.pl), so we sincerely hope to invite you, Mr. Conor,

Oh god, there's no need to call me "Mr. Conor". Conor will do perfectly fine!

Quoted 8 lines

to help us for a period of time on maintenance work, including checking relevant patches, merging and submitting PRs, we will learn together with you for a while, and then take over this part of the work when we become familiar with it. We know that you are also very busy at work, especially if you don't have the hardware at hand. I have the hardware here and I can take the responsibility to run testing. What do you think? I'm waiting for your reply. Thanks in advance.

That seems fine to me. In that case, you should add yourself to the MAINTAINERS entry.

Thanks,
Conor.

Conor, do you want me to add you to the MAINTAINERS entry too?

Quoted 13 lines

MAINTAINERS +5 -0

index 90f13281d297..b74d505003e2 100644
@@ -20063,6 +20063,13 @@ F:   drivers/char/sonypi.c
 F:   drivers/platform/x86/sony-laptop.c
 F:   include/linux/sony-laptop.h
 
+SOPHGO DEVICETREES
+M:   Xiaoguang Xing <[email protected]>
+M:   Chao Wei <[email protected]>
+S:   Maintained
+F:   Documentation/devicetree/bindings/riscv/sophgo.yaml

MAINTAINERS F: drivers/char/sonypi.c · line 20071

Quoted 1 line

MAINTAINERS +1 -0

+F:   arch/riscv/boot/dts/sophgo/

Firstly, this directory does not exist at the time of this patch, so it should not be added here, but rather at the time that you create it.

Secondly, are Xiaoguang Xing and Chao Wei going to monitor the lists & apply patches for these files? If so, you should add a git tree here that they will apply patches to & add to linux-next. Also, I'd really

like to see some on-list signs of life from these people, otherwise I'd rather see your name here instead of theirs.

If they don't intend reviewing/testing/applying patches, I can do it as a last resort but I would rather that someone who specifically cares for this hardware does it.

Thanks,
Conor.

Quoted 7 lines

MAINTAINERS +1 -1

+
 SOUND
 M:   Jaroslav Kysela <[email protected]>
 M:   Takashi Iwai <[email protected]>
--

2.25.1

Add DT binding documentation for the Sophgo SG2042 Soc [1] and the Milk-V Pioneer board [2].

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

Sorry, my mistake to forget adding the tag, will add in next revision.

&gt; -----原始邮件-----

&gt; 发件人: "Krzysztof Kozlowski" <[email protected]>
&gt; 发送时间: 2023-09-20 19:55:30 (星期三)
&gt; 收件人: "Chen Wang" <[email protected]>, [email protected], [email protected], [email protected], [email protected], [email protected], [email protected], [email protected], [email protected], [email protected], [email protected], [email protected], [email protected], [email protected], [email protected] &gt; 抄送: "Chen Wang" <[email protected]>
&gt; 主题: Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
&gt;
&gt; On 20/09/2023 08:37, Chen Wang wrote:
&gt; &gt; Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
&gt; &gt; Milk-V Pioneer board [2].
&gt; &gt;
&gt; &gt; [1]: https://en.sophgo.com/product/introduce/sg2042.html
&gt; &gt; [2]: https://milkv.io/pioneer
&gt;
&gt; This is a friendly reminder during the review process.
&gt;
&gt; It looks like you received a tag and forgot to add it.
&gt;
&gt; If you do not know the process, here is a short explanation:
&gt; Please add Acked-by/Reviewed-by/Tested-by tags when posting new
&gt; versions, under or above your Signed-off-by tag. Tag is "received", when
&gt; provided in a message replied to you on the mailing list. Tools like b4
&gt; can help here. However, there's no need to repost patches *only* to add
&gt; the tags. The upstream maintainer will do that for tags received on the
&gt; version they apply.
&gt;
&gt; https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
&gt;
&gt; If a tag was not added on purpose, please state why and what changed.
&gt;
&gt; Best regards,
&gt; Krzysztof

------------------------------

Best Regards

汪辰(Wang Chen)

</[email protected]></[email protected]></[email protected]>

The C920 is RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C920 core is used in the SOPHGO SG2042 SoC.

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/riscv/cpus.yaml +0 -0

index 38c0b5213736..185a0191bad6 100644

Documentation/devicetree/bindings/riscv/cpus.yaml +0 -1

           - const: riscv
       - items:
           - enum:
--

2.25.1

The C920 is RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C920 core is used in the SOPHGO SG2042 SoC.

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/riscv/cpus.yaml +1 -0

index 38c0b5213736..185a0191bad6 100644
@@ -47,6 +47,7 @@ properties:
               - sifive,u74-mc
               - thead,c906
               - thead,c910
+              - thead,c920
           - const: riscv
       - items:
           - enum:

Signature · 1 line

2.25.1

Add compatible string for SOPHGO SG2042 plic.

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +1 -1

index dc1f28e55266..16f9c4760c0f 100644
@@ -65,6 +65,7 @@ properties:
       - items:
           - enum:
               - allwinner,sun20i-d1-plic
+              - sophgo,sg2042-plic
               - thead,th1520-plic
           - const: thead,c900-plic
       - items:
--

2.25.1

Add compatible string for SOPHGO SG2042 plic.

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +1 -0

index dc1f28e55266..16f9c4760c0f 100644
@@ -65,6 +65,7 @@ properties:
       - items:
           - enum:
               - allwinner,sun20i-d1-plic
+              - sophgo,sg2042-plic
               - thead,th1520-plic
           - const: thead,c900-plic
       - items:

Signature · 1 line

2.25.1

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the fallback to avoid conflict.

Signed-off-by Inochi Amaoto <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

Documentation/devicetree/bindings/timer/sifive,clint.yaml +8 -1

index a0185e15a42f..ae69696c5c75 100644
@@ -39,6 +39,14 @@ properties:
               - allwinner,sun20i-d1-clint
               - thead,th1520-clint
           - const: thead,c900-clint
+      - items:
+          - enum:
+              - sophgo,sg2042-clint-mtimer
+          - const: thead,c900-clint-mtimer
+      - items:
+          - enum:
+              - sophgo,sg2042-clint-mswi
+          - const: thead,c900-clint-mswi
       - items:
           - const: sifive,clint0
           - const: riscv,clint0
--

2.25.1

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the fallback to avoid conflict.

Signed-off-by Inochi Amaoto <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

Documentation/devicetree/bindings/timer/sifive,clint.yaml +8 -0

index a0185e15a42f..ae69696c5c75 100644
@@ -39,6 +39,14 @@ properties:
               - allwinner,sun20i-d1-clint
               - thead,th1520-clint
           - const: thead,c900-clint
+      - items:
+          - enum:
+              - sophgo,sg2042-clint-mtimer
+          - const: thead,c900-clint-mtimer
+      - items:
+          - enum:
+              - sophgo,sg2042-clint-mswi
+          - const: thead,c900-clint-mswi
       - items:
           - const: sifive,clint0
           - const: riscv,clint0

Signature · 1 line

2.25.1

Quoted 6 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the fallback to avoid conflict.

Quoted 2 lines

Signed-off-by Inochi Amaoto <[email protected]>

Signed-off-by Chen Wang <[email protected]>

Have you ignored Krzysztof's comments on this? I don't see a response or a reaction to his comments about the compatibles on the last version. Additionally, where is the user for these? I don't see any drivers that actually make use of these.

Why do you need to have 2 compatibles (and therefore 2 devices) for the clint? I thought the clint was a single device, of which the mtimer and mswi bits were just "features"? Having split register ranges isn't a reason to have two compatibles, so I must be missing something here...

Thanks,
Conor.

Quoted 26 lines

---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

Documentation/devicetree/bindings/timer/sifive,clint.yaml +8 -1

index a0185e15a42f..ae69696c5c75 100644
@@ -39,6 +39,14 @@ properties:
               - allwinner,sun20i-d1-clint
               - thead,th1520-clint
           - const: thead,c900-clint
+      - items:
+          - enum:
+              - sophgo,sg2042-clint-mtimer
+          - const: thead,c900-clint-mtimer
+      - items:
+          - enum:
+              - sophgo,sg2042-clint-mswi
+          - const: thead,c900-clint-mswi
       - items:
           - const: sifive,clint0
           - const: riscv,clint0
--

2.25.1

Quoted 7 lines · Chen Wang

Quoted 6 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the fallback to avoid conflict.

Quoted 8 lines

Quoted 2 lines

Signed-off-by Inochi Amaoto <[email protected]>

Signed-off-by Chen Wang <[email protected]>

Have you ignored Krzysztof's comments on this? I don't see a response or a reaction to his comments about the compatibles on the last version. Additionally, where is the user for these? I don't see any drivers that actually make use of these.

Sorry for late reply and wrong message-id.

The clint is parsed by sbi.

As use the same compatible, the opensbi will
parse the device twice. This will cause a fault.

Quoted 4 lines

Why do you need to have 2 compatibles (and therefore 2 devices) for the clint? I thought the clint was a single device, of which the mtimer and mswi bits were just "features"? Having split register ranges isn't a reason to have two compatibles, so I must be missing something here...

Sorry for late reply, The clint consists of mtimer and ipi devices, which is defined in [1].

This standard shows clint(or the aclint) has two device,

but not one. In another word, there is no need to defined mtimer and ipi device on the same base address.

So we need two compatibles to allow sbi to identify them correctly.

Yo,

Quoted 16 lines · Inochi Amaoto

Quoted 15 lines · Chen Wang

Quoted 8 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the fallback to avoid conflict.

Signed-off-by Inochi Amaoto <[email protected]>

Signed-off-by Chen Wang <[email protected]>

Have you ignored Krzysztof's comments on this? I don't see a response or a reaction to his comments about the compatibles on the last version. Additionally, where is the user for these? I don't see any drivers that actually make use of these.

Quoted 3 lines

Sorry for late reply and wrong message-id.

The clint is parsed by sbi.

That needs to go in the commit message.

Quoted 3 lines

As use the same compatible, the opensbi will
parse the device twice. This will cause a fault.

Then only have one compatible with 2 register ranges? Then your SBI implementation can use those two register ranges to find out the base address for the mtimer bits and for the mswi bits.
I don't understand why this cannot be done, could you please explain.

I also don't see anything in the opensbi repo right now that is using these (nor could I easily see any patches for opensbi adding this). Is there another SBI implementation that you are using that I can take a look at to try and understand this better?

Quoted 7 lines

Quoted 4 lines

Why do you need to have 2 compatibles (and therefore 2 devices) for the clint? I thought the clint was a single device, of which the mtimer and mswi bits were just "features"? Having split register ranges isn't a reason to have two compatibles, so I must be missing something here...

Sorry for late reply, The clint consists of mtimer and ipi devices, which is defined in [1].

Yes, I have looked at the spec. I went to check it again before replying here in case there was something immediately obvious that I was missing.

Quoted 1 line

This standard shows clint(or the aclint) has two device,

The wording used here doesn't really matter. It's one interrupt controller that does mtimer and mswi.

Quoted 2 lines

but not one. In another word, there is no need to defined mtimer and ipi device on the same base address.

There's also no need to have two compatibles for the same interrupt controller, so I do not get this reasoning. What actually _requires_ them to be split?

Quoted 1 line

So we need two compatibles to allow sbi to identify them correctly.

Why is it not sufficient to identify the individual memory regions?

Thanks,
Conor.

Quoted 20 lines

Yo,

Quoted 16 lines · Inochi Amaoto

Quoted 15 lines · Chen Wang

Quoted 8 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the fallback to avoid conflict.

Signed-off-by Inochi Amaoto <[email protected]>

Signed-off-by Chen Wang <[email protected]>

Have you ignored Krzysztof's comments on this? I don't see a response or a reaction to his comments about the compatibles on the last version. Additionally, where is the user for these? I don't see any drivers that actually make use of these.

Quoted 5 lines

Quoted 3 lines

Sorry for late reply and wrong message-id.

The clint is parsed by sbi.

That needs to go in the commit message.

Yes, it will.

Quoted 7 lines

Quoted 2 lines

As use the same compatible, the opensbi will
parse the device twice. This will cause a fault.

Then only have one compatible with 2 register ranges? Then your SBI implementation can use those two register ranges to find out the base address for the mtimer bits and for the mswi bits.
I don't understand why this cannot be done, could you please explain.

That is a good idea, but now SBI use the second register ranges as mtimecmp address for aclint. And there is a aclint-mswi in the SBI. Maybe a change is needed?

Quoted 6 lines

I also don't see anything in the opensbi repo right now that is using these (nor could I easily see any patches for opensbi adding this). Is there another SBI implementation that you are using that I can take a look at to try and understand this better?

This will be sumbit in a short time.
Now we only use it is sophgo vendor SBI, which url is [1].

[1] https://github.com/sophgo/opensbi

Quoted 11 lines

Quoted 7 lines

Quoted 4 lines

Why do you need to have 2 compatibles (and therefore 2 devices) for the clint? I thought the clint was a single device, of which the mtimer and mswi bits were just "features"? Having split register ranges isn't a reason to have two compatibles, so I must be missing something here...

Sorry for late reply, The clint consists of mtimer and ipi devices, which is defined in [1].

Yes, I have looked at the spec. I went to check it again before replying here in case there was something immediately obvious that I was missing.

I think nothing missed.

Quoted 8 lines

Quoted 1 line

This standard shows clint(or the aclint) has two device,

The wording used here doesn't really matter. It's one interrupt controller that does mtimer and mswi.

Quoted 2 lines

but not one. In another word, there is no need to defined mtimer and ipi device on the same base address.

Quoted 4 lines

There's also no need to have two compatibles for the same interrupt controller, so I do not get this reasoning. What actually _requires_ them to be split?

Yes, it is one, but can be mapped into different address. So I think we need two.

Quoted 5 lines

Quoted 2 lines

So we need two compatibles to allow sbi to identify them correctly.

Why is it not sufficient to identify the individual memory regions?

FYI, Anup. As I have no idea for aclint implementation.

Quoted 3 lines

Thanks,
Conor.

Quoted 20 lines

Quoted 20 lines

Yo,

Quoted 16 lines · Inochi Amaoto

Quoted 15 lines · Chen Wang

Quoted 8 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the fallback to avoid conflict.

Signed-off-by Inochi Amaoto <[email protected]>

Signed-off-by Chen Wang <[email protected]>

Have you ignored Krzysztof's comments on this? I don't see a response or a reaction to his comments about the compatibles on the last version. Additionally, where is the user for these? I don't see any drivers that actually make use of these.

Quoted 7 lines

Quoted 5 lines

Quoted 3 lines

Sorry for late reply and wrong message-id.

The clint is parsed by sbi.

That needs to go in the commit message.

Yes, it will.

Thanks.

Quoted 11 lines

Quoted 7 lines

Quoted 2 lines

As use the same compatible, the opensbi will
parse the device twice. This will cause a fault.

Then only have one compatible with 2 register ranges? Then your SBI implementation can use those two register ranges to find out the base address for the mtimer bits and for the mswi bits.
I don't understand why this cannot be done, could you please explain.

That is a good idea, but now SBI use the second register ranges as mtimecmp address for aclint. And there is a aclint-mswi in the SBI. Maybe a change is needed?

Yeah, I don't think the model for this in OpenSBI at the moment (and since I checked, in QEMU too) is correct. I think we should re-do things correctly and it'd be great if things didn't get merged to those projects that end up being objected to by dt-binding people. I've started keeping a closer eye on QEMU recently in that regard, but I am not super attentive. I'll try to be better at that going forward!

Quoted 11 lines

Quoted 6 lines

I also don't see anything in the opensbi repo right now that is using these (nor could I easily see any patches for opensbi adding this). Is there another SBI implementation that you are using that I can take a look at to try and understand this better?

This will be sumbit in a short time.
Now we only use it is sophgo vendor SBI, which url is [1].

[1] https://github.com/sophgo/opensbi

Thanks.

Quoted 27 lines

Quoted 11 lines

Quoted 7 lines

Quoted 4 lines

Why do you need to have 2 compatibles (and therefore 2 devices) for the clint? I thought the clint was a single device, of which the mtimer and mswi bits were just "features"? Having split register ranges isn't a reason to have two compatibles, so I must be missing something here...

Sorry for late reply, The clint consists of mtimer and ipi devices, which is defined in [1].

Yes, I have looked at the spec. I went to check it again before replying here in case there was something immediately obvious that I was missing.

I think nothing missed.

Quoted 12 lines

Quoted 1 line

This standard shows clint(or the aclint) has two device,

The wording used here doesn't really matter. It's one interrupt controller that does mtimer and mswi.

Quoted 2 lines

but not one. In another word, there is no need to defined mtimer and ipi device on the same base address.

There's also no need to have two compatibles for the same interrupt controller, so I do not get this reasoning. What actually _requires_ them to be split?

Quoted 2 lines

Yes, it is one, but can be mapped into different address. So I think we need two.

Not two compatibles though, just two memory addresses that you need to locate (or maybe even 3, for SSWI?)

Quoted 11 lines

Quoted 5 lines

Quoted 2 lines

So we need two compatibles to allow sbi to identify them correctly.

Why is it not sufficient to identify the individual memory regions?

FYI, Anup. As I have no idea for aclint implementation.

Quoted 3 lines

Thanks,
Conor.

Quoted 8 lines

Quoted 8 lines

Quoted 7 lines

Quoted 2 lines

but not one. In another word, there is no need to defined mtimer and ipi device on the same base address.

There's also no need to have two compatibles for the same interrupt controller, so I do not get this reasoning. What actually _requires_ them to be split?

Quoted 6 lines

Quoted 2 lines

Yes, it is one, but can be mapped into different address. So I think we need two.

Not two compatibles though, just two memory addresses that you need to locate (or maybe even 3, for SSWI?)

We may need four (mtime, mtimecmp, mswi, sswi) if use register range.

Anyway, I will use a vendor spec implementation as a temporary solution. I hope this will be corrected in a predictable future, and we can use a standard way to resolve this at that time. :)

Quoted 12 lines

Quoted 12 lines

Quoted 11 lines

Quoted 8 lines

Quoted 3 lines

but not one. In another word, there is no need to defined mtimer and ipi device on the same base address.

There's also no need to have two compatibles for the same interrupt controller, so I do not get this reasoning. What actually _requires_ them to be split?

Yes, it is one, but can be mapped into different address. So I think we need two.

Quoted 5 lines

Quoted 3 lines

Not two compatibles though, just two memory addresses that you need to locate (or maybe even 3, for SSWI?)

We may need four (mtime, mtimecmp, mswi, sswi) if use register range.

Why would you need 4? The first two certainly could be individual reg entries, no?

Quoted 3 lines

Anyway, I will use a vendor spec implementation as a temporary solution. I hope this will be corrected in a predictable future, and we can use a standard way to resolve this at that time. :)

If the spec doesn't get frozen, there'll not be a standard way merged. Hopefully not too many others go off an implement non-frozen specs, and we will not really need to worry all that much about it.

Cheers,
Conor.

Quoted 17 lines · Inochi Amaoto

Quoted 16 lines

Quoted 15 lines

Quoted 11 lines

Quoted 8 lines

Quoted 3 lines

but not one. In another word, there is no need to defined mtimer and ipi device on the same base address.

There's also no need to have two compatibles for the same interrupt controller, so I do not get this reasoning. What actually _requires_ them to be split?

Yes, it is one, but can be mapped into different address. So I think we need two.

Not two compatibles though, just two memory addresses that you need to locate (or maybe even 3, for SSWI?)

Quoted 5 lines

Quoted 1 line

We may need four (mtime, mtimecmp, mswi, sswi) if use register range.

Why would you need 4? The first two certainly could be individual reg entries, no?

After reading the aclint doc again, I found the all of them can be mapped on the different address. (See the section 2.1 in that doc).

But for now,
the mtime and mtimecmp have the same base address in any platform.

Anyway,
the frozen spec in future will decided how many ranges we need.

Quoted 7 lines

Quoted 3 lines

Anyway, I will use a vendor spec implementation as a temporary solution. I hope this will be corrected in a predictable future, and we can use a standard way to resolve this at that time. :)

If the spec doesn't get frozen, there'll not be a standard way merged. Hopefully not too many others go off an implement non-frozen specs, and we will not really need to worry all that much about it.

Yo,

Quoted 23 lines · Inochi Amaoto

Quoted 22 lines · Inochi Amaoto

Quoted 9 lines

Quoted 9 lines

Quoted 9 lines

Quoted 8 lines

Quoted 3 lines

but not one. In another word, there is no need to defined mtimer and ipi device on the same base address.

There's also no need to have two compatibles for the same interrupt controller, so I do not get this reasoning. What actually _requires_ them to be split?

Quoted 8 lines

Quoted 6 lines

Quoted 2 lines

Yes, it is one, but can be mapped into different address. So I think we need two.

Not two compatibles though, just two memory addresses that you need to locate (or maybe even 3, for SSWI?)

We may need four (mtime, mtimecmp, mswi, sswi) if use register range.

Why would you need 4? The first two certainly could be individual reg entries, no?

Quoted 2 lines

After reading the aclint doc again, I found the all of them can be mapped on the different address. (See the section 2.1 in that doc).

Right, that's what I meant by individual reg entries. If there's some dynamic gap between them, then one reg entry would cover mtime and one would cover the base of the mtimecmp region.

Quoted 2 lines

But for now,
the mtime and mtimecmp have the same base address in any platform.

How? The mtimecmp base address would have to be offset from the mtime base address. Is what you mean that, for example, mtime is at an offset of 0x0 from the base address & mtimecmp0 is at, for example, an offset of 0x8 so a single reg entry can cover both?

Also, "any platform"? I figure you mean in this one specific platform?

Quoted 2 lines

Anyway,
the frozen spec in future will decided how many ranges we need.

Isn't the spec abandoned? There may well be no frozen spec.

Quoted 7 lines

Quoted 7 lines

Quoted 3 lines

Anyway, I will use a vendor spec implementation as a temporary solution. I hope this will be corrected in a predictable future, and we can use a standard way to resolve this at that time. :)

If the spec doesn't get frozen, there'll not be a standard way merged. Hopefully not too many others go off an implement non-frozen specs, and we will not really need to worry all that much about it.

Cheers,
Conor.

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the

Quoted 4 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the

Why?

You received comment about it, so please provide proper explanation in the commit msg.

Same device does not get two different compatibles.

You also did not respond to my comments, so you basically ignored it and send the same.

NAK

Best regards,
Krzysztof

Quoted 6 lines · Chen Wang

Quoted 4 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the

Quoted 2 lines

Why?

If use the same compatible, SBI will process this twice in both ipi and timer, use different compatible will allow SBI to treat these as different. AFAIK, the aclint in SBI use the same concepts, which make hard to use the second register range. I have explained in another response.

Quoted 6 lines

Quoted 6 lines · Chen Wang

Quoted 4 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the

Quoted 7 lines

Quoted 2 lines

Why?

If use the same compatible, SBI will process this twice in both ipi and timer, use different compatible will allow SBI to treat these as different. AFAIK, the aclint in SBI use the same concepts, which make hard to use the second register range. I have explained in another response.

What is a SBI? Linux driver? If so, why some intermediate Linux driver choice should affect bindings?
Best regards,
Krzysztof

Quoted 15 lines · Inochi Amaoto

Quoted 6 lines

Quoted 6 lines · Chen Wang

Quoted 4 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the

Quoted 7 lines

Quoted 2 lines

Why?

If use the same compatible, SBI will process this twice in both ipi and timer, use different compatible will allow SBI to treat these as different. AFAIK, the aclint in SBI use the same concepts, which make hard to use the second register range. I have explained in another response.

Quoted 5 lines

What is a SBI? Linux driver? If so, why some intermediate Linux driver choice should affect bindings?
Best regards,
Krzysztof

SBI (Supervisor Binary Interface) is defined by riscv, which is an interface between the Supervisor Execution Environment (SEE) and the supervisor. The detailed documentation can be found in [1].

The implement of SBI needs fdt info of the platform, which is provided by kernel. So we need a dt-bindings for these devices, and these will be processed by SBI.

[1] https://github.com/riscv-non-isa/riscv-sbi-doc

Quoted 29 lines · Inochi Amaoto

Quoted 15 lines · Inochi Amaoto

Quoted 6 lines

Quoted 6 lines · Chen Wang

Quoted 4 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the

Quoted 7 lines

Quoted 2 lines

Why?

If use the same compatible, SBI will process this twice in both ipi and timer, use different compatible will allow SBI to treat these as different. AFAIK, the aclint in SBI use the same concepts, which make hard to use the second register range. I have explained in another response.

Quoted 5 lines

What is a SBI? Linux driver? If so, why some intermediate Linux driver choice should affect bindings?
Best regards,
Krzysztof

SBI (Supervisor Binary Interface) is defined by riscv, which is an interface between the Supervisor Execution Environment (SEE) and the supervisor. The detailed documentation can be found in [1].

The implement of SBI needs fdt info of the platform, which is provided by kernel. So we need a dt-bindings for these devices, and these will be processed by SBI.

Quoted 1 line

[1] https://github.com/riscv-non-isa/riscv-sbi-doc

Yeah, this is the unfortunate problem of half-baked bindings (IMO) ending up in OpenSBI (which likely means they also ended up in QEMU). This T-Head stuff is coming across our (metaphorical) desks, so we are obviously going to try to do things correctly. I may end up speaking to Anup later today, if I do I will point him at this thread (if he hasn't seen it already).

Quoted 29 lines · Inochi Amaoto

Quoted 15 lines · Inochi Amaoto

Quoted 6 lines

Quoted 6 lines · Chen Wang

Quoted 4 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the

Quoted 7 lines

Quoted 2 lines

Why?

If use the same compatible, SBI will process this twice in both ipi and timer, use different compatible will allow SBI to treat these as different. AFAIK, the aclint in SBI use the same concepts, which make hard to use the second register range. I have explained in another response.

Quoted 5 lines

What is a SBI? Linux driver? If so, why some intermediate Linux driver choice should affect bindings?
Best regards,
Krzysztof

SBI (Supervisor Binary Interface) is defined by riscv, which is an interface between the Supervisor Execution Environment (SEE) and the supervisor. The detailed documentation can be found in [1].

The implement of SBI needs fdt info of the platform, which is provided by kernel. So we need a dt-bindings for these devices, and these will be processed by SBI.

Quoted 1 line

[1] https://github.com/riscv-non-isa/riscv-sbi-doc

Yeah, this is the unfortunate problem of half-baked bindings (IMO) ending up in OpenSBI (which likely means they also ended up in QEMU). This T-Head stuff is coming across our (metaphorical) desks, so we are obviously going to try to do things correctly. I may end up speaking to Anup later today, if I do I will point him at this thread (if he hasn't seen it already).

Quoted 31 lines · Conor Dooley

Quoted 29 lines · Inochi Amaoto

Quoted 15 lines · Inochi Amaoto

Quoted 6 lines

Quoted 6 lines · Chen Wang

Quoted 4 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the

Quoted 7 lines

Quoted 2 lines

Why?

If use the same compatible, SBI will process this twice in both ipi and timer, use different compatible will allow SBI to treat these as different. AFAIK, the aclint in SBI use the same concepts, which make hard to use the second register range. I have explained in another response.

Quoted 5 lines

What is a SBI? Linux driver? If so, why some intermediate Linux driver choice should affect bindings?
Best regards,
Krzysztof

SBI (Supervisor Binary Interface) is defined by riscv, which is an interface between the Supervisor Execution Environment (SEE) and the supervisor. The detailed documentation can be found in [1].

The implement of SBI needs fdt info of the platform, which is provided by kernel. So we need a dt-bindings for these devices, and these will be processed by SBI.

Quoted 8 lines

Quoted 1 line

[1] https://github.com/riscv-non-isa/riscv-sbi-doc

Yeah, this is the unfortunate problem of half-baked bindings (IMO) ending up in OpenSBI (which likely means they also ended up in QEMU). This T-Head stuff is coming across our (metaphorical) desks, so we are obviously going to try to do things correctly. I may end up speaking to Anup later today, if I do I will point him at this thread (if he hasn't seen it already).

RISC-V ACLINT is one of those unfortunate non-ISA specs (like SiFive PLIC) which is implemented by various organizations but not officially ratified by RVI.

The SiFive CLINT has flexibility related limitations which makes it not useful for multi-socket and mult-die systems. The SiFive CLINT is also not useful for systems with AIA because with AIA M-mode has a new way of doing M-mode IPIs. Due to this reasons, the RISC-V ACLINT spec breaks down traditional SiFive CLINT into two separate devices namely mtimer and mswi. This allows platforms to implement only the required set of devices. The mtimer as defined by the ACLINT specifications also allows platforms to place mtime and mtimecmp registers at different locations.

Refer, https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

We need a separate DT bindings document for ACLINT MTIMER and ACLINT MSWI because these are separate devices. The Sophgo sg2042 SoC should add their implementation specific compatible strings in this document.

Regards,
Anup

Quoted 41 lines · Conor Dooley

Quoted 31 lines · Inochi Amaoto

Quoted 29 lines

Quoted 15 lines · Inochi Amaoto

Quoted 6 lines

Quoted 6 lines · Chen Wang

Quoted 4 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the

Quoted 7 lines

Quoted 2 lines

Why?

If use the same compatible, SBI will process this twice in both ipi and timer, use different compatible will allow SBI to treat these as different. AFAIK, the aclint in SBI use the same concepts, which make hard to use the second register range. I have explained in another response.

Quoted 5 lines

What is a SBI? Linux driver? If so, why some intermediate Linux driver choice should affect bindings?
Best regards,
Krzysztof

SBI (Supervisor Binary Interface) is defined by riscv, which is an interface between the Supervisor Execution Environment (SEE) and the supervisor. The detailed documentation can be found in [1].

The implement of SBI needs fdt info of the platform, which is provided by kernel. So we need a dt-bindings for these devices, and these will be processed by SBI.

Quoted 8 lines

Quoted 1 line

[1] https://github.com/riscv-non-isa/riscv-sbi-doc

Yeah, this is the unfortunate problem of half-baked bindings (IMO) ending up in OpenSBI (which likely means they also ended up in QEMU). This T-Head stuff is coming across our (metaphorical) desks, so we are obviously going to try to do things correctly. I may end up speaking to Anup later today, if I do I will point him at this thread (if he hasn't seen it already).

Quoted 3 lines

RISC-V ACLINT is one of those unfortunate non-ISA specs (like SiFive PLIC) which is implemented by various organizations but not officially ratified by RVI.

Yeah, I brought this stuff up at the weekly pw sync call, and Paul pointed that out.

Quoted 10 lines

The SiFive CLINT has flexibility related limitations which makes it not useful for multi-socket and mult-die systems. The SiFive CLINT is also not useful for systems with AIA because with AIA M-mode has a new way of doing M-mode IPIs. Due to this reasons, the RISC-V ACLINT spec breaks down traditional SiFive CLINT into two separate devices namely mtimer and mswi. This allows platforms to implement only the required set of devices. The mtimer as defined by the ACLINT specifications also allows platforms to place mtime and mtimecmp registers at different locations.

Quoted 6 lines

Refer, https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

We need a separate DT bindings document for ACLINT MTIMER and ACLINT MSWI because these are separate devices. The Sophgo sg2042 SoC should add their implementation specific compatible strings in this document.

If the spec isn't frozen, I'm not accepting a binding for the "generic" version of it. Bindings for this specific implemtnation are okay. For sure though, squeezing this into the sifive,plic binding isn't appropriate.

What was pointed out, I think by Samuel, that the reason that this may need to be split is the fact that there are many possible MTIMER register ranges & possibly sswi stuff too that would need to be differentiated.

Quoted 3 lines

Regards,
Anup

Quoted 41 lines · Conor Dooley

Quoted 31 lines · Inochi Amaoto

Quoted 29 lines

Quoted 15 lines · Inochi Amaoto

Quoted 6 lines

Quoted 6 lines · Chen Wang

Quoted 4 lines

From: Inochi Amaoto <[email protected]>

Add two new compatible string formatted like C9xx-clint-xxx to identify the timer and ipi device separately, and do not allow c900-clint as the

Quoted 7 lines

Quoted 2 lines

Why?

If use the same compatible, SBI will process this twice in both ipi and timer, use different compatible will allow SBI to treat these as different. AFAIK, the aclint in SBI use the same concepts, which make hard to use the second register range. I have explained in another response.

Quoted 5 lines

What is a SBI? Linux driver? If so, why some intermediate Linux driver choice should affect bindings?
Best regards,
Krzysztof

SBI (Supervisor Binary Interface) is defined by riscv, which is an interface between the Supervisor Execution Environment (SEE) and the supervisor. The detailed documentation can be found in [1].

The implement of SBI needs fdt info of the platform, which is provided by kernel. So we need a dt-bindings for these devices, and these will be processed by SBI.

Quoted 8 lines

Quoted 1 line

[1] https://github.com/riscv-non-isa/riscv-sbi-doc

Yeah, this is the unfortunate problem of half-baked bindings (IMO) ending up in OpenSBI (which likely means they also ended up in QEMU). This T-Head stuff is coming across our (metaphorical) desks, so we are obviously going to try to do things correctly. I may end up speaking to Anup later today, if I do I will point him at this thread (if he hasn't seen it already).

Quoted 3 lines

RISC-V ACLINT is one of those unfortunate non-ISA specs (like SiFive PLIC) which is implemented by various organizations but not officially ratified by RVI.

Yeah, I brought this stuff up at the weekly pw sync call, and Paul pointed that out.

Quoted 10 lines

The SiFive CLINT has flexibility related limitations which makes it not useful for multi-socket and mult-die systems. The SiFive CLINT is also not useful for systems with AIA because with AIA M-mode has a new way of doing M-mode IPIs. Due to this reasons, the RISC-V ACLINT spec breaks down traditional SiFive CLINT into two separate devices namely mtimer and mswi. This allows platforms to implement only the required set of devices. The mtimer as defined by the ACLINT specifications also allows platforms to place mtime and mtimecmp registers at different locations.

Quoted 6 lines

Refer, https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

We need a separate DT bindings document for ACLINT MTIMER and ACLINT MSWI because these are separate devices. The Sophgo sg2042 SoC should add their implementation specific compatible strings in this document.

If the spec isn't frozen, I'm not accepting a binding for the "generic" version of it. Bindings for this specific implemtnation are okay. For sure though, squeezing this into the sifive,plic binding isn't appropriate.

What was pointed out, I think by Samuel, that the reason that this may need to be split is the fact that there are many possible MTIMER register ranges & possibly sswi stuff too that would need to be differentiated.

Quoted 3 lines

Regards,
Anup

Quoted 17 lines

Quoted 10 lines

The SiFive CLINT has flexibility related limitations which makes it not useful for multi-socket and mult-die systems. The SiFive CLINT is also not useful for systems with AIA because with AIA M-mode has a new way of doing M-mode IPIs. Due to this reasons, the RISC-V ACLINT spec breaks down traditional SiFive CLINT into two separate devices namely mtimer and mswi. This allows platforms to implement only the required set of devices. The mtimer as defined by the ACLINT specifications also allows platforms to place mtime and mtimecmp registers at different locations.

Quoted 6 lines

Refer, https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

We need a separate DT bindings document for ACLINT MTIMER and ACLINT MSWI because these are separate devices. The Sophgo sg2042 SoC should add their implementation specific compatible strings in this document.

Quoted 5 lines

If the spec isn't frozen, I'm not accepting a binding for the "generic" version of it. Bindings for this specific implemtnation are okay. For sure though, squeezing this into the sifive,plic binding isn't appropriate.

It seems I have missed a point. I wonder whether it is better to add a "aclint" binding firstly and then add sg2042 to it, or just use sg2042 specific binding?

If use "aclint" binding, I wonder it is OK to add
thead quirks as compatible specific properties, or left this to the SBI to handle? e.g. T-HEAD timer is not 64bit timer, and we should identify this.

Quoted 24 lines

Quoted 23 lines

Quoted 11 lines

The SiFive CLINT has flexibility related limitations which makes it not useful for multi-socket and mult-die systems. The SiFive CLINT is also not useful for systems with AIA because with AIA M-mode has a new way of doing M-mode IPIs. Due to this reasons, the RISC-V ACLINT spec breaks down traditional SiFive CLINT into two separate devices namely mtimer and mswi. This allows platforms to implement only the required set of devices. The mtimer as defined by the ACLINT specifications also allows platforms to place mtime and mtimecmp registers at different locations.

Quoted 6 lines

Refer, https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

We need a separate DT bindings document for ACLINT MTIMER and ACLINT MSWI because these are separate devices. The Sophgo sg2042 SoC should add their implementation specific compatible strings in this document.

If the spec isn't frozen, I'm not accepting a binding for the "generic" version of it. Bindings for this specific implemtnation are okay. For sure though, squeezing this into the sifive,plic binding isn't appropriate.

Quoted 3 lines

It seems I have missed a point. I wonder whether it is better to add a "aclint" binding firstly and then add sg2042 to it, or just use sg2042 specific binding?

sg2042 specific, being frozen is a requirement for merging patches related to RVI specifications.

Quoted 3 lines

If use "aclint" binding, I wonder it is OK to add
thead quirks as compatible specific properties, or left this to the SBI to handle? e.g. T-HEAD timer is not 64bit timer, and we should identify this.

The compatible string alone should be sufficient to identify the width of the timer etc.

Thanks,
Conor.

From: Emil Renner Berthing <[email protected]>

Add compatible for the uarts on the Sophgo SG2042 RISC-V SoC.

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +1 -1

index 17c553123f96..011d89e6df0f 100644
@@ -45,6 +45,7 @@ properties:
           - const: snps,dw-apb-uart
       - items:
           - enum:
+              - sophgo,sg2042-uart
               - starfive,jh7100-hsuart
               - starfive,jh7100-uart
           - const: snps,dw-apb-uart
--

2.25.1

From: Emil Renner Berthing <[email protected]>

Add compatible for the uarts on the Sophgo SG2042 RISC-V SoC.

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +1 -0

index 17c553123f96..011d89e6df0f 100644
@@ -45,6 +45,7 @@ properties:
           - const: snps,dw-apb-uart
       - items:
           - enum:
+              - sophgo,sg2042-uart
               - starfive,jh7100-hsuart
               - starfive,jh7100-uart
           - const: snps,dw-apb-uart

Signature · 1 line

2.25.1

From: Emil Renner Berthing <[email protected]>

Add quirk to skip setting the input clock rate for the uarts on the Sophgo SG2042 SoC similar to the StarFive JH7100.

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 drivers/tty/serial/8250/8250_dw.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

drivers/tty/serial/8250/8250_dw.c +1 -1

index f4cafca1a7da..6c344877a07f 100644
@@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
        .quirks = DW_UART_QUIRK_IS_DMA_FC,
 };
 
-static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
+static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
        .usr_reg = DW_UART_USR,
        .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
 };

drivers/tty/serial/8250/8250_dw.c +0 -1

        { /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, dw8250_of_match);
--

2.25.1

Quoted 25 lines · Chen Wang

From: Emil Renner Berthing <[email protected]>

Add quirk to skip setting the input clock rate for the uarts on the Sophgo SG2042 SoC similar to the StarFive JH7100.

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
  drivers/tty/serial/8250/8250_dw.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

drivers/tty/serial/8250/8250_dw.c +1 -1

index f4cafca1a7da..6c344877a07f 100644
@@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
         .quirks = DW_UART_QUIRK_IS_DMA_FC,
  };
 
-static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
+static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
         .usr_reg = DW_UART_USR,
         .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
  };

drivers/tty/serial/8250/8250_dw.c static const struct of_device_id dw8250_of_match[] = { · line 784

Quoted 6 lines

drivers/tty/serial/8250/8250_dw.c +2 -1

@@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = {
         { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
         { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
         { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
-       { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
+       { .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data },
+       { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },

Why shall we touch the jh7100 stuff in this patch?

Quoted 6 lines

drivers/tty/serial/8250/8250_dw.c +0 -1

         { /* Sentinel */ }
  };
  MODULE_DEVICE_TABLE(of, dw8250_of_match);
--

2.25.1

Ren, thanks for your review.

sg2042 and jh7100 use the same uart driver and we here just want to reuse the logic from jh7100.
We don't touch jh7100 stuff, we just rename "dw8250_starfive_jh7100_data" to "dw8250_skip_set_rate_data" and make it a common data for both sg2042 and jh7100.

Quoted 41 lines · Chen Wang

Quoted 25 lines

From: Emil Renner Berthing <[email protected]>

Add quirk to skip setting the input clock rate for the uarts on the Sophgo SG2042 SoC similar to the StarFive JH7100.

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
  drivers/tty/serial/8250/8250_dw.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

drivers/tty/serial/8250/8250_dw.c +1 -1

index f4cafca1a7da..6c344877a07f 100644
@@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
         .quirks = DW_UART_QUIRK_IS_DMA_FC,
  };
 
-static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
+static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
         .usr_reg = DW_UART_USR,
         .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
  };

drivers/tty/serial/8250/8250_dw.c static const struct of_device_id dw8250_of_match[] = { · line 784

Quoted 6 lines

drivers/tty/serial/8250/8250_dw.c +2 -1

@@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = {
         { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
         { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
         { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
-       { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
+       { .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data },
+       { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },

Why shall we touch the jh7100 stuff in this patch?

Quoted 6 lines

drivers/tty/serial/8250/8250_dw.c +0 -1

         { /* Sentinel */ }
  };
  MODULE_DEVICE_TABLE(of, dw8250_of_match);
--

2.25.1

From: Emil Renner Berthing <[email protected]>

Add quirk to skip setting the input clock rate for the uarts on the Sophgo SG2042 SoC similar to the StarFive JH7100.

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
  drivers/tty/serial/8250/8250_dw.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

drivers/tty/serial/8250/8250_dw.c +3 -2

index f4cafca1a7da..6c344877a07f 100644
@@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
  	.quirks = DW_UART_QUIRK_IS_DMA_FC,
  };
 
-static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
+static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
  	.usr_reg = DW_UART_USR,
  	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
  };

@@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = {
  	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
  	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
  	{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
-	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
+	{ .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data },
+	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
  	{ /* Sentinel */ }
  };
  MODULE_DEVICE_TABLE(of, dw8250_of_match);

Quoted 4 lines · Chen Wang

From: Emil Renner Berthing <[email protected]>

Add quirk to skip setting the input clock rate for the uarts on the Sophgo SG2042 SoC similar to the StarFive JH7100.

I'd love an actual explanation of why this is necessary here.

Quoted 7 lines · Ben Dooks

Quoted 4 lines · Chen Wang

From: Emil Renner Berthing <[email protected]>

Add quirk to skip setting the input clock rate for the uarts on the Sophgo SG2042 SoC similar to the StarFive JH7100.

I'd love an actual explanation of why this is necessary here.

Makes sense. For the JH7100 the commit message is:

On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to exactly 16 * 115200Hz and many other common bitrates. Trying this will only result in a higher input clock, but low enough that the UART's internal divisor can't come close enough to the baud rate target. So rather than try to set the input clock it's better to skip the clk_set_rate call and rely solely on the UART's internal divisor.

@Chen Wang is this also true for the SG2042?

/Emil

Quoted 7 lines · Ben Dooks

Quoted 4 lines · Chen Wang

From: Emil Renner Berthing <[email protected]>

Add quirk to skip setting the input clock rate for the uarts on the Sophgo SG2042 SoC similar to the StarFive JH7100.

I'd love an actual explanation of why this is necessary here.

Makes sense. For the JH7100 the commit message is:

On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to exactly 16 * 115200Hz and many other common bitrates. Trying this will only result in a higher input clock, but low enough that the UART's internal divisor can't come close enough to the baud rate target. So rather than try to set the input clock it's better to skip the clk_set_rate call and rely solely on the UART's internal divisor.

@Chen Wang is this also true for the SG2042?

/Emil

Milk-V Pioneer motherboard is powered by SOPHON's SG2042.

SG2042 is server grade chip with high performance, low power consumption and high data throughput.
Key features:
- 64 RISC-V cpu cores which implements IMAFDC
- 4 cores per cluster, 16 clusters on chip
- ......

More info is available at [1].

[1]: https://en.sophgo.com/product/introduce/sg2042.html

Currently only support booting into console with only uart, other features will be added soon later.

Acked-by Xiaoguang Xing <[email protected]>

Signed-off-by Xiaoguang Xing <[email protected]>

Signed-off-by Inochi Amaoto <[email protected]>

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1744 +++++++++++++++++++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi      |  439 +++++
 2 files changed, 2183 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi

arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi new file +1744 -0

new file mode 100644
index 000000000000..9fc79b1cf3bf
@@ -0,0 +1,1744 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
+ */
+
+/ {
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               timebase-frequency = <50000000>;
+
+               cpu-map {
+                       socket0 {
+                               cluster0 {
+                                        core0 {
+                                               cpu = <&cpu0>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu1>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu2>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu3>;
+                                        };
+                               };
+
+                               cluster1 {
+                                        core0 {
+                                               cpu = <&cpu4>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu5>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu6>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu7>;
+                                        };
+                               };
+
+                               cluster2 {
+                                        core0 {
+                                               cpu = <&cpu16>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu17>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu18>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu19>;
+                                        };
+                               };
+
+                               cluster3 {
+                                        core0 {
+                                               cpu = <&cpu20>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu21>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu22>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu23>;
+                                        };
+                               };
+
+                               cluster4 {
+                                        core0 {
+                                               cpu = <&cpu8>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu9>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu10>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu11>;
+                                        };
+                               };
+
+                               cluster5 {
+                                        core0 {
+                                               cpu = <&cpu12>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu13>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu14>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu15>;
+                                        };
+                               };
+
+                               cluster6 {
+                                        core0 {
+                                               cpu = <&cpu24>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu25>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu26>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu27>;
+                                        };
+                               };
+
+                               cluster7 {
+                                        core0 {
+                                               cpu = <&cpu28>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu29>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu30>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu31>;
+                                        };
+                               };
+
+                               cluster8 {
+                                        core0 {
+                                               cpu = <&cpu32>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu33>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu34>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu35>;
+                                        };
+                               };
+
+                               cluster9 {
+                                        core0 {
+                                               cpu = <&cpu36>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu37>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu38>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu39>;
+                                        };
+                               };
+
+                               cluster10 {
+                                        core0 {
+                                               cpu = <&cpu48>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu49>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu50>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu51>;
+                                        };
+                               };
+
+                               cluster11 {
+                                        core0 {
+                                               cpu = <&cpu52>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu53>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu54>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu55>;
+                                        };
+                               };
+
+                               cluster12 {
+                                        core0 {
+                                               cpu = <&cpu40>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu41>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu42>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu43>;
+                                        };
+                               };
+
+                               cluster13 {
+                                        core0 {
+                                               cpu = <&cpu44>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu45>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu46>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu47>;
+                                        };
+                               };
+
+                               cluster14 {
+                                        core0 {
+                                               cpu = <&cpu56>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu57>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu58>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu59>;
+                                        };
+                               };
+
+                               cluster15 {
+                                        core0 {
+                                               cpu = <&cpu60>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu61>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu62>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu63>;
+                                        };
+                               };
+                       };
+               };
+
+               cpu0: cpu@0 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <0>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache0>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu0_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu1: cpu@1 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <1>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache0>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu1_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu2: cpu@2 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <2>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache0>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu2_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu3: cpu@3 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <3>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache0>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu3_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu4: cpu@4 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <4>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache1>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu4_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu5: cpu@5 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <5>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache1>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu5_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu6: cpu@6 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <6>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache1>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu6_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu7: cpu@7 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <7>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache1>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu7_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu8: cpu@8 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <8>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache4>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu8_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu9: cpu@9 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <9>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache4>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu9_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu10: cpu@10 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <10>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache4>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu10_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu11: cpu@11 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <11>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache4>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu11_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu12: cpu@12 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <12>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache5>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu12_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu13: cpu@13 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <13>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache5>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu13_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu14: cpu@14 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <14>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache5>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu14_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu15: cpu@15 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <15>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache5>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu15_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu16: cpu@16 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <16>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache2>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu16_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu17: cpu@17 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <17>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache2>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu17_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu18: cpu@18 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <18>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache2>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu18_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu19: cpu@19 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <19>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache2>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu19_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu20: cpu@20 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <20>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache3>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu20_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu21: cpu@21 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <21>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache3>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu21_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu22: cpu@22 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <22>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache3>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu22_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu23: cpu@23 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <23>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache3>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu23_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu24: cpu@24 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <24>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache6>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu24_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu25: cpu@25 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <25>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache6>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu25_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu26: cpu@26 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <26>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache6>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu26_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu27: cpu@27 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <27>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache6>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu27_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu28: cpu@28 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <28>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache7>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu28_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu29: cpu@29 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <29>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache7>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu29_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu30: cpu@30 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <30>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache7>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu30_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu31: cpu@31 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <31>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache7>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu31_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu32: cpu@32 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <32>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache8>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu32_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu33: cpu@33 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <33>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache8>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu33_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu34: cpu@34 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <34>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache8>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu34_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu35: cpu@35 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <35>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache8>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu35_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu36: cpu@36 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <36>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache9>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu36_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu37: cpu@37 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <37>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache9>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu37_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu38: cpu@38 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <38>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache9>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu38_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu39: cpu@39 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <39>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache9>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu39_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu40: cpu@40 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <40>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache12>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu40_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu41: cpu@41 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <41>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache12>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu41_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu42: cpu@42 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <42>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache12>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu42_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu43: cpu@43 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <43>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache12>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu43_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu44: cpu@44 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <44>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache13>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu44_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu45: cpu@45 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <45>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache13>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu45_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu46: cpu@46 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <46>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache13>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu46_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu47: cpu@47 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <47>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache13>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu47_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu48: cpu@48 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <48>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache10>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu48_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu49: cpu@49 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <49>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache10>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu49_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu50: cpu@50 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <50>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache10>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu50_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu51: cpu@51 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <51>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache10>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu51_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu52: cpu@52 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <52>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache11>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu52_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu53: cpu@53 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <53>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache11>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu53_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu54: cpu@54 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <54>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache11>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu54_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu55: cpu@55 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <55>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache11>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu55_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu56: cpu@56 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <56>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache14>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu56_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu57: cpu@57 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <57>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache14>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu57_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu58: cpu@58 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <58>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache14>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu58_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu59: cpu@59 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <59>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache14>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu59_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu60: cpu@60 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <60>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache15>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu60_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu61: cpu@61 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <61>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache15>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu61_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu62: cpu@62 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <62>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache15>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu62_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu63: cpu@63 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       reg = <63>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache15>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu63_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               l2_cache0: l2-cache@0 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache1: l2-cache@1 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache2: l2-cache@2 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache3: l2-cache@3 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache4: l2-cache@4 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache5: l2-cache@5 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache6: l2-cache@6 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache7: l2-cache@7 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache8: l2-cache@8 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache9: l2-cache@9 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache10: l2-cache@10 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache11: l2-cache@11 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache12: l2-cache@12 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache13: l2-cache@13 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache14: l2-cache@14 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache15: l2-cache@15 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+       };
+};

arch/riscv/boot/dts/sophgo/sg2042.dtsi new file +439 -1

new file mode 100644
index 000000000000..747fd9764c95
@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "sg2042-cpus.dtsi"
+
+#define SOC_PERIPHERAL_IRQ(nr) (nr)
+
+/ {
+       compatible = "sophgo,sg2042";
+       #address-cells = <2>;
+       #size-cells = <2>;
+       dma-noncoherent;
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       /* the mem node will be updated by ZSBL. */
+       memory@0 {
+               device_type = "memory";
+               reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
+       };
+
+       memory@1 {
+               device_type = "memory";
+               reg = <0x00000000 0x00000001 0x00000000 0x00000000>;
+       };
+
+       memory@2 {
+               device_type = "memory";
+               reg = <0x00000000 0x00000002 0x00000000 0x00000000>;
+       };
+
+       memory@3 {
+               device_type = "memory";
+               reg = <0x00000000 0x00000003 0x00000000 0x00000000>;
+       };
+
+       pmu {
+               compatible = "riscv,pmu";
+               riscv,event-to-mhpmevent =
+                       <0x00003 0x00000000 0x00000010>,
+                       <0x00004 0x00000000 0x00000011>,
+                       <0x00005 0x00000000 0x00000007>,
+                       <0x00006 0x00000000 0x00000006>,
+                       <0x00008 0x00000000 0x00000027>,
+                       <0x00009 0x00000000 0x00000028>,
+                       <0x10000 0x00000000 0x0000000c>,
+                       <0x10001 0x00000000 0x0000000d>,
+                       <0x10002 0x00000000 0x0000000e>,
+                       <0x10003 0x00000000 0x0000000f>,
+                       <0x10008 0x00000000 0x00000001>,
+                       <0x10009 0x00000000 0x00000002>,
+                       <0x10010 0x00000000 0x00000010>,
+                       <0x10011 0x00000000 0x00000011>,
+                       <0x10012 0x00000000 0x00000012>,
+                       <0x10013 0x00000000 0x00000013>,
+                       <0x10019 0x00000000 0x00000004>,
+                       <0x10021 0x00000000 0x00000003>,
+                       <0x10030 0x00000000 0x0000001c>,
+                       <0x10031 0x00000000 0x0000001b>;
+               riscv,event-to-mhpmcounters =
+                       <0x00003 0x00003 0xfffffff8>,
+                       <0x00004 0x00004 0xfffffff8>,
+                       <0x00005 0x00005 0xfffffff8>,
+                       <0x00006 0x00006 0xfffffff8>,
+                       <0x00007 0x00007 0xfffffff8>,
+                       <0x00008 0x00008 0xfffffff8>,
+                       <0x00009 0x00009 0xfffffff8>,
+                       <0x0000a 0x0000a 0xfffffff8>,
+                       <0x10000 0x10000 0xfffffff8>,
+                       <0x10001 0x10001 0xfffffff8>,
+                       <0x10002 0x10002 0xfffffff8>,
+                       <0x10003 0x10003 0xfffffff8>,
+                       <0x10008 0x10008 0xfffffff8>,
+                       <0x10009 0x10009 0xfffffff8>,
+                       <0x10010 0x10010 0xfffffff8>,
+                       <0x10011 0x10011 0xfffffff8>,
+                       <0x10012 0x10012 0xfffffff8>,
+                       <0x10013 0x10013 0xfffffff8>,
+                       <0x10019 0x10019 0xfffffff8>,
+                       <0x10021 0x10021 0xfffffff8>,
+                       <0x10030 0x10030 0xfffffff8>,
+                       <0x10031 0x10031 0xfffffff8>;
+               riscv,raw-event-to-mhpmcounters =
+                       <0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>,
+                       <0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>;
+       };
+
+       soc: soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               clint_mswi: interrupt-controller@7094000000 {
+                       compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi";
+                       reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
+                       interrupts-extended = <&cpu0_intc 3>,
+                                             <&cpu1_intc 3>,
+                                             <&cpu2_intc 3>,
+                                             <&cpu3_intc 3>,
+                                             <&cpu4_intc 3>,
+                                             <&cpu5_intc 3>,
+                                             <&cpu6_intc 3>,
+                                             <&cpu7_intc 3>,
+                                             <&cpu8_intc 3>,
+                                             <&cpu9_intc 3>,
+                                             <&cpu10_intc 3>,
+                                             <&cpu11_intc 3>,
+                                             <&cpu12_intc 3>,
+                                             <&cpu13_intc 3>,
+                                             <&cpu14_intc 3>,
+                                             <&cpu15_intc 3>,
+                                             <&cpu16_intc 3>,
+                                             <&cpu17_intc 3>,
+                                             <&cpu18_intc 3>,
+                                             <&cpu19_intc 3>,
+                                             <&cpu20_intc 3>,
+                                             <&cpu21_intc 3>,
+                                             <&cpu22_intc 3>,
+                                             <&cpu23_intc 3>,
+                                             <&cpu24_intc 3>,
+                                             <&cpu25_intc 3>,
+                                             <&cpu26_intc 3>,
+                                             <&cpu27_intc 3>,
+                                             <&cpu28_intc 3>,
+                                             <&cpu29_intc 3>,
+                                             <&cpu30_intc 3>,
+                                             <&cpu31_intc 3>,
+                                             <&cpu32_intc 3>,
+                                             <&cpu33_intc 3>,
+                                             <&cpu34_intc 3>,
+                                             <&cpu35_intc 3>,
+                                             <&cpu36_intc 3>,
+                                             <&cpu37_intc 3>,
+                                             <&cpu38_intc 3>,
+                                             <&cpu39_intc 3>,
+                                             <&cpu40_intc 3>,
+                                             <&cpu41_intc 3>,
+                                             <&cpu42_intc 3>,
+                                             <&cpu43_intc 3>,
+                                             <&cpu44_intc 3>,
+                                             <&cpu45_intc 3>,
+                                             <&cpu46_intc 3>,
+                                             <&cpu47_intc 3>,
+                                             <&cpu48_intc 3>,
+                                             <&cpu49_intc 3>,
+                                             <&cpu50_intc 3>,
+                                             <&cpu51_intc 3>,
+                                             <&cpu52_intc 3>,
+                                             <&cpu53_intc 3>,
+                                             <&cpu54_intc 3>,
+                                             <&cpu55_intc 3>,
+                                             <&cpu56_intc 3>,
+                                             <&cpu57_intc 3>,
+                                             <&cpu58_intc 3>,
+                                             <&cpu59_intc 3>,
+                                             <&cpu60_intc 3>,
+                                             <&cpu61_intc 3>,
+                                             <&cpu62_intc 3>,
+                                             <&cpu63_intc 3>;
+               };
+
+               clint_mtimer0: timer@70ac000000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu0_intc 7>,
+                                             <&cpu1_intc 7>,
+                                             <&cpu2_intc 7>,
+                                             <&cpu3_intc 7>;
+               };
+
+               clint_mtimer1: timer@70ac010000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu4_intc 7>,
+                                             <&cpu5_intc 7>,
+                                             <&cpu6_intc 7>,
+                                             <&cpu7_intc 7>;
+               };
+
+               clint_mtimer2: timer@70ac020000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu8_intc 7>,
+                                             <&cpu9_intc 7>,
+                                             <&cpu10_intc 7>,
+                                             <&cpu11_intc 7>;
+               };
+
+               clint_mtimer3: timer@70ac030000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu12_intc 7>,
+                                             <&cpu13_intc 7>,
+                                             <&cpu14_intc 7>,
+                                             <&cpu15_intc 7>;
+               };
+
+               clint_mtimer4: timer@70ac040000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu16_intc 7>,
+                                             <&cpu17_intc 7>,
+                                             <&cpu18_intc 7>,
+                                             <&cpu19_intc 7>;
+               };
+
+               clint_mtimer5: timer@70ac050000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu20_intc 7>,
+                                             <&cpu21_intc 7>,
+                                             <&cpu22_intc 7>,
+                                             <&cpu23_intc 7>;
+               };
+
+               clint_mtimer6: timer@70ac060000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu24_intc 7>,
+                                             <&cpu25_intc 7>,
+                                             <&cpu26_intc 7>,
+                                             <&cpu27_intc 7>;
+               };
+
+               clint_mtimer7: timer@70ac070000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu28_intc 7>,
+                                             <&cpu29_intc 7>,
+                                             <&cpu30_intc 7>,
+                                             <&cpu31_intc 7>;
+               };
+
+               clint_mtimer8: timer@70ac080000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu32_intc 7>,
+                                             <&cpu33_intc 7>,
+                                             <&cpu34_intc 7>,
+                                             <&cpu35_intc 7>;
+               };
+
+               clint_mtimer9: timer@70ac090000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu36_intc 7>,
+                                             <&cpu37_intc 7>,
+                                             <&cpu38_intc 7>,
+                                             <&cpu39_intc 7>;
+               };
+
+               clint_mtimer10: timer@70ac0a0000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu40_intc 7>,
+                                             <&cpu41_intc 7>,
+                                             <&cpu42_intc 7>,
+                                             <&cpu43_intc 7>;
+               };
+
+               clint_mtimer11: timer@70ac0b0000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu44_intc 7>,
+                                             <&cpu45_intc 7>,
+                                             <&cpu46_intc 7>,
+                                             <&cpu47_intc 7>;
+               };
+
+               clint_mtimer12: timer@70ac0c0000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu48_intc 7>,
+                                             <&cpu49_intc 7>,
+                                             <&cpu50_intc 7>,
+                                             <&cpu51_intc 7>;
+               };
+
+               clint_mtimer13: timer@70ac0d0000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu52_intc 7>,
+                                             <&cpu53_intc 7>,
+                                             <&cpu54_intc 7>,
+                                             <&cpu55_intc 7>;
+               };
+
+               clint_mtimer14: timer@70ac0e0000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu56_intc 7>,
+                                             <&cpu57_intc 7>,
+                                             <&cpu58_intc 7>,
+                                             <&cpu59_intc 7>;
+               };
+
+               clint_mtimer15: timer@70ac0f0000 {
+                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+                       reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu60_intc 7>,
+                                             <&cpu61_intc 7>,
+                                             <&cpu62_intc 7>,
+                                             <&cpu63_intc 7>;
+               };
+
+               intc: interrupt-controller@7090000000 {
+                       compatible = "sophgo,sg2042-plic", "thead,c900-plic";
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
+                       interrupt-controller;
+                       interrupts-extended =
+                               <&cpu0_intc 0xffffffff>,  <&cpu0_intc 9>,
+                               <&cpu1_intc 0xffffffff>,  <&cpu1_intc 9>,
+                               <&cpu2_intc 0xffffffff>,  <&cpu2_intc 9>,
+                               <&cpu3_intc 0xffffffff>,  <&cpu3_intc 9>,
+                               <&cpu4_intc 0xffffffff>,  <&cpu4_intc 9>,
+                               <&cpu5_intc 0xffffffff>,  <&cpu5_intc 9>,
+                               <&cpu6_intc 0xffffffff>,  <&cpu6_intc 9>,
+                               <&cpu7_intc 0xffffffff>,  <&cpu7_intc 9>,
+                               <&cpu8_intc 0xffffffff>,  <&cpu8_intc 9>,
+                               <&cpu9_intc 0xffffffff>,  <&cpu9_intc 9>,
+                               <&cpu10_intc 0xffffffff>, <&cpu10_intc 9>,
+                               <&cpu11_intc 0xffffffff>, <&cpu11_intc 9>,
+                               <&cpu12_intc 0xffffffff>, <&cpu12_intc 9>,
+                               <&cpu13_intc 0xffffffff>, <&cpu13_intc 9>,
+                               <&cpu14_intc 0xffffffff>, <&cpu14_intc 9>,
+                               <&cpu15_intc 0xffffffff>, <&cpu15_intc 9>,
+                               <&cpu16_intc 0xffffffff>, <&cpu16_intc 9>,
+                               <&cpu17_intc 0xffffffff>, <&cpu17_intc 9>,
+                               <&cpu18_intc 0xffffffff>, <&cpu18_intc 9>,
+                               <&cpu19_intc 0xffffffff>, <&cpu19_intc 9>,
+                               <&cpu20_intc 0xffffffff>, <&cpu20_intc 9>,
+                               <&cpu21_intc 0xffffffff>, <&cpu21_intc 9>,
+                               <&cpu22_intc 0xffffffff>, <&cpu22_intc 9>,
+                               <&cpu23_intc 0xffffffff>, <&cpu23_intc 9>,
+                               <&cpu24_intc 0xffffffff>, <&cpu24_intc 9>,
+                               <&cpu25_intc 0xffffffff>, <&cpu25_intc 9>,
+                               <&cpu26_intc 0xffffffff>, <&cpu26_intc 9>,
+                               <&cpu27_intc 0xffffffff>, <&cpu27_intc 9>,
+                               <&cpu28_intc 0xffffffff>, <&cpu28_intc 9>,
+                               <&cpu29_intc 0xffffffff>, <&cpu29_intc 9>,
+                               <&cpu30_intc 0xffffffff>, <&cpu30_intc 9>,
+                               <&cpu31_intc 0xffffffff>, <&cpu31_intc 9>,
+                               <&cpu32_intc 0xffffffff>, <&cpu32_intc 9>,
+                               <&cpu33_intc 0xffffffff>, <&cpu33_intc 9>,
+                               <&cpu34_intc 0xffffffff>, <&cpu34_intc 9>,
+                               <&cpu35_intc 0xffffffff>, <&cpu35_intc 9>,
+                               <&cpu36_intc 0xffffffff>, <&cpu36_intc 9>,
+                               <&cpu37_intc 0xffffffff>, <&cpu37_intc 9>,
+                               <&cpu38_intc 0xffffffff>, <&cpu38_intc 9>,
+                               <&cpu39_intc 0xffffffff>, <&cpu39_intc 9>,
+                               <&cpu40_intc 0xffffffff>, <&cpu40_intc 9>,
+                               <&cpu41_intc 0xffffffff>, <&cpu41_intc 9>,
+                               <&cpu42_intc 0xffffffff>, <&cpu42_intc 9>,
+                               <&cpu43_intc 0xffffffff>, <&cpu43_intc 9>,
+                               <&cpu44_intc 0xffffffff>, <&cpu44_intc 9>,
+                               <&cpu45_intc 0xffffffff>, <&cpu45_intc 9>,
+                               <&cpu46_intc 0xffffffff>, <&cpu46_intc 9>,
+                               <&cpu47_intc 0xffffffff>, <&cpu47_intc 9>,
+                               <&cpu48_intc 0xffffffff>, <&cpu48_intc 9>,
+                               <&cpu49_intc 0xffffffff>, <&cpu49_intc 9>,
+                               <&cpu50_intc 0xffffffff>, <&cpu50_intc 9>,
+                               <&cpu51_intc 0xffffffff>, <&cpu51_intc 9>,
+                               <&cpu52_intc 0xffffffff>, <&cpu52_intc 9>,
+                               <&cpu53_intc 0xffffffff>, <&cpu53_intc 9>,
+                               <&cpu54_intc 0xffffffff>, <&cpu54_intc 9>,
+                               <&cpu55_intc 0xffffffff>, <&cpu55_intc 9>,
+                               <&cpu56_intc 0xffffffff>, <&cpu56_intc 9>,
+                               <&cpu57_intc 0xffffffff>, <&cpu57_intc 9>,
+                               <&cpu58_intc 0xffffffff>, <&cpu58_intc 9>,
+                               <&cpu59_intc 0xffffffff>, <&cpu59_intc 9>,
+                               <&cpu60_intc 0xffffffff>, <&cpu60_intc 9>,
+                               <&cpu61_intc 0xffffffff>, <&cpu61_intc 9>,
+                               <&cpu62_intc 0xffffffff>, <&cpu62_intc 9>,
+                               <&cpu63_intc 0xffffffff>, <&cpu63_intc 9>;
+                       riscv,ndev = <224>;
+               };
+
+               uart0: serial@7040000000 {
+                       compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart";
+                       reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(112) IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <500000000>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "disabled";
+               };
+       };
+};
--