Add Milk-V Pioneer RISC-V board support
Subsystems (6)
v3 cover Add Milk-V Pioneer RISC-V board support
Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2] in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.
Now only support basic uart drivers to boot up into a basic console.
Thanks,
Chen
---
Changes in v3:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [5].
- add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
- updated maintainers info. for sophgo devicetree
- remove the quirk changes for uart
- updated dts, such as:
- add "riscv,isa-base"/"riscv,isa-extensions" for cpus
- update l2 cache node's name
- remove memory and pmu nodes
- fixed other issues as per input from reviewers.
Changes in v2:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [4].
- Improve format for comment of commitments as per input from last review.
- Improve format of DTS as per input from last review.
- Remove numa related stuff from DTS. This part is just for optimization, may add it later if really needed.
Changes in v1:
The patch series is based on v6.6-rc1. Due to it is not sent in thread, I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or test the patches at the link [3].
[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
[v1-0/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-1/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-2/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-3/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-4/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-5/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-6/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-7/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-8/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-9/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-10/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-11/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-12/12]:https://lore.kernel.org/linux-riscv/[email protected]/
---
Chen Wang (9):
riscv: Add SOPHGO SOC family Kconfig support
dt-bindings: vendor-prefixes: add milkv/sophgo
dt-bindings: riscv: add sophgo sg2042 bindings
dt-bindings: riscv: Add T-HEAD C920 compatibles
dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
MAINTAINERS: add two files to sophgo devicetrees entry
riscv: dts: add initial Sophgo SG2042 SoC device tree
riscv: dts: sophgo: add Milk-V Pioneer board device tree
riscv: defconfig: enable SOPHGO SoC
Inochi Amaoto (2):
dt-bindings: timer: Add Sophgo sg2042 CLINT timer
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
.../sifive,plic-1.0.0.yaml | 1 + .../sophgo,sg2042-clint-mswi.yaml | 42 + .../devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/riscv/sophgo.yaml | 28 + .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 + .../devicetree/bindings/vendor-prefixes.yaml | 4 + MAINTAINERS | 9 + arch/riscv/Kconfig.socs | 5 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/sophgo/Makefile | 3 + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++ arch/riscv/configs/defconfig | 1 + 14 files changed, 2361 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml create mode 100644 arch/riscv/boot/dts/sophgo/Makefile create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
Signature · 1 line
2.25.1
PATCH v3 1/11 riscv: Add SOPHGO SOC family Kconfig support
The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V cores.
--- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+)
arch/riscv/Kconfig.socs +5 -0
@@ -22,6 +22,11 @@ config SOC_SIFIVE help This enables support for SiFive SoC platform hardware. +config ARCH_SOPHGO + bool "Sophgo SoCs" + help + This enables support for Sophgo SoC platform hardware. + config ARCH_STARFIVE def_bool SOC_STARFIVE
Signature · 1 line
2.25.1
PATCH v3 2/11 dt-bindings: vendor-prefixes: add milkv/sophgo
In reply to Chen WangAdd new vendor strings to dt bindings. These new vendor strings are used by
- SOPHGO's SG2042 SoC [1]
- Milk-V Pioneer board [2], which uses SG2042 chip.
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++ 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/vendor-prefixes.yaml +4 -0
@@ -863,6 +863,8 @@ patternProperties: description: MikroElektronika d.o.o. "^mikrotik,.*": description: MikroTik + "^milkv,.*": + description: MilkV Technology Co., Ltd "^miniand,.*": description: Miniand Tech "^minix,.*":
@@ -1273,6 +1275,8 @@ patternProperties: description: Solomon Systech Limited "^sony,.*": description: Sony Corporation + "^sophgo,.*": + description: Sophgo Technology Inc. "^sourceparts,.*": description: Source Parts Inc. "^spansion,.*":
Signature · 1 line
2.25.1
PATCH v3 3/11 dt-bindings: riscv: add sophgo sg2042 bindings
In reply to Chen WangAdd DT binding documentation for the SOPHGO's SG2042 Soc [1] and the Milk-V Pioneer board [2].
--- .../devicetree/bindings/riscv/sophgo.yaml | 28 +++++++++++++++++++ MAINTAINERS | 6 ++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
Documentation/devicetree/bindings/riscv/sophgo.yaml new file +28 -0
@@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sophgo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SoC-based boards + +maintainers: + - Chao Wei <[email protected]> + - Chen Wang <[email protected]> + +description: + Sophgo SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - milkv,pioneer + - const: sophgo,sg2042 + +additionalProperties: true + +...
MAINTAINERS +6 -0
@@ -20063,6 +20063,12 @@ F: drivers/char/sonypi.c F: drivers/platform/x86/sony-laptop.c F: include/linux/sony-laptop.h +SOPHGO DEVICETREES +M: Chao Wei <[email protected]> +M: Chen Wang <[email protected]> +S: Maintained +F: Documentation/devicetree/bindings/riscv/sophgo.yaml + SOUND M: Jaroslav Kysela <[email protected]> M: Takashi Iwai <[email protected]>
Signature · 1 line
2.25.1
PATCH v3 4/11 dt-bindings: riscv: Add T-HEAD C920 compatibles
In reply to Chen WangThe C920 is RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C920 core is used in the SOPHGO's SG2042 SoC.
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/riscv/cpus.yaml +1 -0
@@ -47,6 +47,7 @@ properties: - sifive,u74-mc - thead,c906 - thead,c910 + - thead,c920 - const: riscv - items: - enum:
Signature · 1 line
2.25.1
PATCH v3 5/11 dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
In reply to Chen WangAdd compatible string for SOPHGO SG2042 plic.
--- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +1 -0
@@ -65,6 +65,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - sophgo,sg2042-plic - thead,th1520-plic - const: thead,c900-plic - items:
Signature · 1 line
2.25.1
PATCH v3 6/11 dt-bindings: timer: Add Sophgo sg2042 CLINT timer
In reply to Chen WangFrom: Inochi Amaoto <[email protected]>
The clint of Sophgo sg2042 is incompatible with the standard sifive clint, as the timer and ipi device on the different address, and can not be handled by the sifive,clint DT.
In addition, the timers of sg2042 are mapped by per cluster, which is hard to merge with its ipi device.
To avoid conficts caused by using the same clint compatible string when this device is parsed by SBI, add a new vendor specific compatible string to identify the timer of sg2042 soc.
--- .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml new file +42 -0
@@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/sophgo,sg2042-clint-mtimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CLINT Timer + +maintainers: + - Inochi Amaoto <[email protected]> + +properties: + compatible: + oneOf: + - items: + - const: sophgo,sg2042-clint-mtimer + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + timer@ac000000 { + compatible = "sophgo,sg2042-clint-mtimer"; + interrupts-extended = <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + reg = <0xac000000 0x00010000>; + }; +...
Signature · 1 line
2.25.1
Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
Hey,
Quoted 8 lines · Chen Wang
From: Inochi Amaoto <[email protected]>
The clint of Sophgo sg2042 is incompatible with the standard sifive clint, as the timer and ipi device on the different address, and can not be handled by the sifive,clint DT.
In addition, the timers of sg2042 are mapped by per cluster, which is hard to merge with its ipi device.
I think the description here is kinda poor, it needs to be explained that this is an implementation of the not frozen & likely abandoned aclint spec.
Quoted 3 lines
To avoid conficts caused by using the same clint compatible string when this device is parsed by SBI, add a new vendor specific compatible string to identify the timer of sg2042 soc.
And this whole section about avoiding conflicts is not relevant, since the binding is specifically for the timer. It'd be better to mention why a single compatible cannot work for all elements, than bring up a situation that does not exist and would be a misuse of the binding in the first place.
Quoted 3 lines
Signed-off-by Inochi Amaoto <[email protected]>Signed-off-by Chen Wang <[email protected]>Signed-off-by Chen Wang <[email protected]>
You only need to sign this off once. The iscas one looks like it probably is the relevant signoff?
Quoted 17 lines
--- .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yamlDocumentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml new file +6
-0@@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/sophgo,sg2042-clint-mtimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +
Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml line 16
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Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml new file +10
-0+title: Sophgo CLINT Timer + +maintainers: + - Inochi Amaoto <[email protected]> + +properties: + compatible: + oneOf: + - items: + - const: sophgo,sg2042-clint-mtimer
There's only one of these, so you don't need the oneOf. Also, is the clint here not a thead IP? In which case, you need to add a second compatible IMO. That second compatible then would be the one that appears in opensbi etc.
Otherwise, this looks fine.
Thanks,
Conor.
Quoted 29 lines
Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml new file +26
-0+ + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + timer@ac000000 { + compatible = "sophgo,sg2042-clint-mtimer"; + interrupts-extended = <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + reg = <0xac000000 0x00010000>; + }; +...Signature · 1 line
2.25.1
Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
Quoted 9 lines
Hey,
Quoted 6 lines · Chen Wang
From: Inochi Amaoto <[email protected]>
The clint of Sophgo sg2042 is incompatible with the standard sifive clint, as the timer and ipi device on the different address, and can not be handled by the sifive,clint DT.
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In addition, the timers of sg2042 are mapped by per cluster, which is hard to merge with its ipi device.
I think the description here is kinda poor, it needs to be explained that this is an implementation of the not frozen & likely abandoned aclint spec.
Thanks, I will explain this.
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To avoid conficts caused by using the same clint compatible string when this device is parsed by SBI, add a new vendor specific compatible string to identify the timer of sg2042 soc.
And this whole section about avoiding conflicts is not relevant, since the binding is specifically for the timer. It'd be better to mention why a single compatible cannot work for all elements, than bring up a situation that does not exist and would be a misuse of the binding in the first place.
Thanks
Quoted 28 lines
Quoted 3 lines
Signed-off-by Inochi Amaoto <[email protected]>Signed-off-by Chen Wang <[email protected]>Signed-off-by Chen Wang <[email protected]>You only need to sign this off once. The iscas one looks like it probably is the relevant signoff?
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--- .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yamlDocumentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml new file +10
-0@@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/sophgo,sg2042-clint-mtimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CLINT Timer + +maintainers: + - Inochi Amaoto <[email protected]>
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Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml line 16
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Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml new file +6
-0+ +properties: + compatible: + oneOf: + - items: + - const: sophgo,sg2042-clint-mtimerThere's only one of these, so you don't need the oneOf.
Thanks
Quoted 1 line
Also, is the clint here not a thead IP? In which case, you need to add a
Yes, The clint is a thead IP, like that of th1520 and allwinner D1.
Quoted 3 lines
second compatible IMO. That second compatible then would be the one that appears in opensbi etc.
As this is a thead IP, maybe use thead,c900-clint-mtimer is fine? If so, whether we should replace the "thead,c900-clint" with these separate DT to describe the thead clint? The DT binding said the thead clint is not compatible with the sifive clint, so maybe this is a chance to just move them out.
Quoted 35 lines
Otherwise, this looks fine.
Thanks,
Conor.Quoted 29 lines
Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml new file +26
-1+ + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + timer@ac000000 { + compatible = "sophgo,sg2042-clint-mtimer"; + interrupts-extended = <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + reg = <0xac000000 0x00010000>; + }; +... --2.25.1
Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
Quoted 12 lines · Inochi Amaoto
Quoted 7 lines
Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml line 16
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Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml new file +5
-0+properties: + compatible: + oneOf: + - items: + - const: sophgo,sg2042-clint-mtimerThere's only one of these, so you don't need the oneOf.
Thanks
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Also, is the clint here not a thead IP? In which case, you need to add a
Quoted 7 lines
Yes, The clint is a thead IP, like that of th1520 and allwinner D1.
Quoted 3 lines
second compatible IMO. That second compatible then would be the one that appears in opensbi etc.
As this is a thead IP, maybe use thead,c900-clint-mtimer is fine?
I would suggest calling it -aclint-mtimer instead of clint-mtimer.
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If so, whether we should replace the "thead,c900-clint" with these separate DT to describe the thead clint?
No, since that's a different device, right?
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The DT binding said the thead clint is not
compatible with the sifive clint, so maybe this is a chance to just move them out.
I don't think that it really makes sense to do that.
Thanks,
Conor.
Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
Quoted 17 lines · Inochi Amaoto
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Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml line 16
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Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml new file +5
-0+properties: + compatible: + oneOf: + - items: + - const: sophgo,sg2042-clint-mtimerThere's only one of these, so you don't need the oneOf.
Thanks
Quoted 1 line
Also, is the clint here not a thead IP? In which case, you need to add a
Yes, The clint is a thead IP, like that of th1520 and allwinner D1.
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second compatible IMO. That second compatible then would be the one that appears in opensbi etc.
As this is a thead IP, maybe use thead,c900-clint-mtimer is fine?
I would suggest calling it -aclint-mtimer instead of clint-mtimer.
It is OK for me. As I describe below, now use sophgo as vendor is better. Anyway, I will add a new second one in the next patch.
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If so, whether we should replace the "thead,c900-clint" with these separate DT to describe the thead clint?
No, since that's a different device, right?
Yes. It seems sophgo defined these by themselves, but the T-HEAD. Sorry for my mistake.
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The DT binding said the thead clint is not
compatible with the sifive clint, so maybe this is a chance to just move them out.I don't think that it really makes sense to do that.
Thanks,
Conor.
Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
Quoted 29 lines · Inochi Amaoto
Quoted 17 lines · Inochi Amaoto
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Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml line 16
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Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml new file +5
-0+properties: + compatible: + oneOf: + - items: + - const: sophgo,sg2042-clint-mtimerThere's only one of these, so you don't need the oneOf.
Thanks
Quoted 1 line
Also, is the clint here not a thead IP? In which case, you need to add a
Yes, The clint is a thead IP, like that of th1520 and allwinner D1.
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second compatible IMO. That second compatible then would be the one that appears in opensbi etc.
As this is a thead IP, maybe use thead,c900-clint-mtimer is fine?
I would suggest calling it -aclint-mtimer instead of clint-mtimer.
It is OK for me. As I describe below, now use sophgo as vendor is better. Anyway, I will add a new second one in the next patch.
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If so, whether we should replace the "thead,c900-clint" with these separate DT to describe the thead clint?
No, since that's a different device, right?
Yes. It seems sophgo defined these by themselves, but the T-HEAD. Sorry for my mistake.
I'm sorry, I don't quite understand this. Do you mean that the IP is not T-Head, but rather designed by Sophgo? If the IP is made by T-Head, then I would expect to see something like
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
in the dts.
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The DT binding said the thead clint is not
compatible with the sifive clint, so maybe this is a chance to just move them out.I don't think that it really makes sense to do that.
Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
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If so, whether we should replace the "thead,c900-clint" with these separate DT to describe the thead clint?
No, since that's a different device, right?
Yes. It seems sophgo defined these by themselves, but the T-HEAD. Sorry for my mistake.
Quoted 8 lines
I'm sorry, I don't quite understand this. Do you mean that the IP is not T-Head, but rather designed by Sophgo? If the IP is made by T-Head, then I would expect to see something like
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
in the dts.
AFAIK, the clint IP is designed by T-HEAD, not Sophgo. Sophgo change this IP layout to fit its weird cpu design. But in my test, the timer and mswi of clint is compatible with the T-HEAD one. So we should treat this as T-HEAD IP, not Sophgo?
Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
Quoted 15 lines · Inochi Amaoto
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If so, whether we should replace the "thead,c900-clint" with these separate DT to describe the thead clint?
No, since that's a different device, right?
Yes. It seems sophgo defined these by themselves, but the T-HEAD. Sorry for my mistake.
I'm sorry, I don't quite understand this. Do you mean that the IP is not T-Head, but rather designed by Sophgo? If the IP is made by T-Head, then I would expect to see something like
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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in the dts.
AFAIK, the clint IP is designed by T-HEAD, not Sophgo. Sophgo change this IP layout to fit its weird cpu design. But in my test, the timer and mswi of clint is compatible with the T-HEAD one.
So we should treat this as T-HEAD IP, not Sophgo?
Yes, in the way I demonstrated above probably.
PATCH v3 7/11 dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
In reply to Chen WangFrom: Inochi Amaoto <[email protected]>
Like the timer of Sophgo sg2042 clint. The machine-level software interrupt device (mswi) of sg2042 clint have the same problem when dealing with the standard sifive clint.
To avoid the same conficts as the timer of sg2042 clint, also add the vendor specific compatible string to identify the mswi of sg2042 clint.
--- .../sophgo,sg2042-clint-mswi.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml new file +42 -0
@@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-clint-mswi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device + +maintainers: + - Inochi Amaoto <[email protected]> + +properties: + compatible: + oneOf: + - items: + - const: sophgo,sg2042-clint-mswi + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@94000000 { + compatible = "sophgo,sg2042-clint-mswi"; + interrupts-extended = <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>, + <&cpu4intc 3>; + reg = <0x94000000 0x00010000>; + }; +...
Signature · 1 line
2.25.1
Re: [PATCH v3 07/11] dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
Quoted 6 lines · Chen Wang
From: Inochi Amaoto <[email protected]>
Like the timer of Sophgo sg2042 clint. The machine-level software interrupt device (mswi) of sg2042 clint have the same problem when dealing with the standard sifive clint.
Quoted 6 lines
To avoid the same conficts as the timer of sg2042 clint, also add the vendor specific compatible string to identify the mswi of sg2042 clint.
Signed-off-by Inochi Amaoto <[email protected]>Signed-off-by Chen Wang <[email protected]>Signed-off-by Chen Wang <[email protected]>
All of the same comments apply here.
Thanks,
Conor.
Quoted 56 lines
--- .../sophgo,sg2042-clint-mswi.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yamlDocumentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml new file +42
-0@@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-clint-mswi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device + +maintainers: + - Inochi Amaoto <[email protected]> + +properties: + compatible: + oneOf: + - items: + - const: sophgo,sg2042-clint-mswi + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@94000000 { + compatible = "sophgo,sg2042-clint-mswi"; + interrupts-extended = <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>, + <&cpu4intc 3>; + reg = <0x94000000 0x00010000>; + }; +...Signature · 1 line
2.25.1
PATCH v3 8/11 MAINTAINERS: add two files to sophgo devicetrees entry
In reply to Chen WangAdd two dt-binding files which will be maintained by SOPHGO DEVICETREES.
--- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+)
MAINTAINERS +2 -0
@@ -20067,7 +20067,9 @@ SOPHGO DEVICETREES M: Chao Wei <[email protected]> M: Chen Wang <[email protected]> S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml F: Documentation/devicetree/bindings/riscv/sophgo.yaml +F: Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml SOUND M: Jaroslav Kysela <[email protected]>
Signature · 1 line
2.25.1
PATCH v3 9/11 riscv: dts: add initial Sophgo SG2042 SoC device tree
In reply to Chen WangMilk-V Pioneer motherboard is powered by SG2042.
SG2042 is server grade chip with high performance, low power consumption and high data throughput.
Key features:
- 64 RISC-V cpu cores
- 4 cores per cluster, 16 clusters on chip
- More info is available at [1].
Currently only support booting into console with only uart, other features will be added soon later.
--- MAINTAINERS | 1 + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 ++++ 3 files changed, 2206 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
MAINTAINERS +1 -0
@@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES M: Chao Wei <[email protected]> M: Chen Wang <[email protected]> S: Maintained +F: arch/riscv/boot/dts/sophgo/ F: Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml F: Documentation/devicetree/bindings/riscv/sophgo.yaml F: Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi new file +1880 -0
1,880 lines not on this page · raw message
arch/riscv/boot/dts/sophgo/sg2042.dtsi new file +325 -0
325 lines not on this page · raw message
Signature · 1 line
2.25.1
Re: [PATCH v3 09/11] riscv: dts: add initial Sophgo SG2042 SoC device tree
Hey,
Quoted 10 lines · Chen Wang
Milk-V Pioneer motherboard is powered by SG2042.
SG2042 is server grade chip with high performance, low power consumption and high data throughput.
Key features:
- 64 RISC-V cpu cores
- 4 cores per cluster, 16 clusters on chip
- More info is available at [1].
Quoted 37 lines
Currently only support booting into console with only uart, other features will be added soon later.
Reviewed-by Guo Ren <[email protected]>Acked-by Chao Wei <[email protected]>Co-developed-by Xiaoguang Xing <[email protected]>Signed-off-by Xiaoguang Xing <[email protected]>Co-developed-by Inochi Amaoto <[email protected]>Signed-off-by Inochi Amaoto <[email protected]>Signed-off-by Chen Wang <[email protected]>Signed-off-by Chen Wang <[email protected]>--- MAINTAINERS | 1 + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 ++++ 3 files changed, 2206 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsiMAINTAINERS +1
-0@@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES M: Chao Wei <[email protected]> M: Chen Wang <[email protected]> S: Maintained +F: arch/riscv/boot/dts/sophgo/ F: Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml F: Documentation/devicetree/bindings/riscv/sophgo.yaml F: Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yamlarch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi new file +0
-0
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi line 9
Quoted 9 lines
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi new file +9
-0@@ -0,0 +1,1880 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +/* + * c920 declares "rv64gcv", but the version of it's v-ext + * is 0.7.1. It's not supported by kernel so we remove "v". + */
This is incorrect, v needs to be removed because the version of vector does not match that in the ratified standard, as defined by the dt-binding. Even if the comment was correct, it'd be a statement of the obvious and should be removed.
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi line 12
Quoted 3 lines
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi new file +3
-0+#define ISA_BASE "rv64i" +#define ISA_EXTENSIONS \ + "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zihpm"
Why do these as macros but leave the riscv,isa property not as one? TBH, I'd rather these were not macros to make my life easier while grepping through stuff etc.
Cheers,
Conor.
Quoted 22 lines
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi new file +22
-0+ cpu0: cpu@0 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = ISA_BASE; + riscv,isa-extensions = ISA_EXTENSIONS; + reg = <0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + };
PATCH v3 10/11 riscv: dts: sophgo: add Milk-V Pioneer board device tree
In reply to Chen WangMilk-V Pioneer [1] is a developer motherboard based on SG2042 in a standard mATX form factor.
Currently only support booting into console with only uart enabled, other features will be added soon later.
--- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/sophgo/Makefile | 3 +++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/Makefile create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
arch/riscv/boot/dts/Makefile +1 -0
@@ -4,6 +4,7 @@ subdir-y += canaan subdir-y += microchip subdir-y += renesas subdir-y += sifive +subdir-y += sophgo subdir-y += starfive subdir-y += thead
arch/riscv/boot/dts/sophgo/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb +
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts new file +19 -0
@@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +#include "sg2042.dtsi" + +/ { + model = "Milk-V Pioneer"; + compatible = "milkv,pioneer", "sophgo,sg2042"; + + chosen { + stdout-path = "serial0"; + }; +}; + +&uart0 { + status = "okay"; +};
Signature · 1 line
2.25.1
PATCH v3 11/11 riscv: defconfig: enable SOPHGO SoC
In reply to Chen WangEnable SOPHGO SoC config in defconfig to allow the default upstream kernel to boot on Milk-V Pioneer board.
--- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+)
arch/riscv/configs/defconfig +1 -0
@@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y CONFIG_SOC_VIRT=y +CONFIG_ARCH_SOPHGO=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_PM=y
Signature · 1 line
2.25.1
Hey,
Quoted 11 lines · Chen Wang
Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2] in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.Now only support basic uart drivers to boot up into a basic console.
Thanks,
Chen---
Quoted 11 lines
Changes in v3:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [5].
- add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
- updated maintainers info. for sophgo devicetree
- remove the quirk changes for uart
- updated dts, such as:
- add "riscv,isa-base"/"riscv,isa-extensions" for cpus
- update l2 cache node's name
- remove memory and pmu nodes
- fixed other issues as per input from reviewers.
v3 looks better indeed. I had some comments on the bindings and dt patches, but none were particularly major.
Thanks,
Conor.
Quoted 78 lines
Changes in v2:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [4].
- Improve format for comment of commitments as per input from last review.
- Improve format of DTS as per input from last review.
- Remove numa related stuff from DTS. This part is just for optimization, may add it later if really needed.Changes in v1:
The patch series is based on v6.6-rc1. Due to it is not sent in thread, I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or test the patches at the link [3].[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
[v1-0/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-1/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-2/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-3/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-4/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-5/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-6/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-7/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-8/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-9/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-10/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-11/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-12/12]:https://lore.kernel.org/linux-riscv/[email protected]/---
Chen Wang (9):
riscv: Add SOPHGO SOC familyKconfigsupport
dt-bindings: vendor-prefixes: add milkv/sophgo
dt-bindings: riscv: add sophgo sg2042 bindings
dt-bindings: riscv: Add T-HEAD C920 compatibles
dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
MAINTAINERS: add two files to sophgo devicetrees entry
riscv: dts: add initial Sophgo SG2042 SoC device tree
riscv: dts: sophgo: add Milk-V Pioneer board device tree
riscv: defconfig: enable SOPHGO SoCInochi Amaoto (2):
dt-bindings: timer: Add Sophgo sg2042 CLINT timer
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi.../sifive,plic-1.0.0.yaml | 1 + .../sophgo,sg2042-clint-mswi.yaml | 42 + .../devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/riscv/sophgo.yaml | 28 + .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 + .../devicetree/bindings/vendor-prefixes.yaml | 4 + MAINTAINERS | 9 + arch/riscv/Kconfig.socs | 5 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/sophgo/Makefile | 3 + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++ arch/riscv/configs/defconfig | 1 + 14 files changed, 2361 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml create mode 100644 arch/riscv/boot/dts/sophgo/Makefile create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsibase-commit:
0bb80ecc33a8fb5a682236443c1e740d5c917d1dSignature · 1 line
2.25.1
Quoted 27 lines · Conor Dooley <[email protected]> 于2023年9月28日周四 00:09写道：
Hey,
Quoted 11 lines · Chen Wang
Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2] in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.Now only support basic uart drivers to boot up into a basic console.
Thanks,
Chen---
Quoted 11 lines
Changes in v3:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [5].
- add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
- updated maintainers info. for sophgo devicetree
- remove the quirk changes for uart
- updated dts, such as:
- add "riscv,isa-base"/"riscv,isa-extensions" for cpus
- update l2 cache node's name
- remove memory and pmu nodes
- fixed other issues as per input from reviewers.
Quoted 6 lines
v3 looks better indeed. I had some comments on the bindings and dt patches, but none were particularly major.
Thanks,
Conor.
Thanks, Conor, I will continue imrpoving according to your commnents.
Quoted 78 lines
Quoted 78 lines
Changes in v2:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [4].
- Improve format for comment of commitments as per input from last review.
- Improve format of DTS as per input from last review.
- Remove numa related stuff from DTS. This part is just for optimization, may add it later if really needed.Changes in v1:
The patch series is based on v6.6-rc1. Due to it is not sent in thread, I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or test the patches at the link [3].[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
[v1-0/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-1/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-2/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-3/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-4/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-5/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-6/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-7/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-8/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-9/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-10/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-11/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-12/12]:https://lore.kernel.org/linux-riscv/[email protected]/---
Chen Wang (9):
riscv: Add SOPHGO SOC familyKconfigsupport
dt-bindings: vendor-prefixes: add milkv/sophgo
dt-bindings: riscv: add sophgo sg2042 bindings
dt-bindings: riscv: Add T-HEAD C920 compatibles
dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
MAINTAINERS: add two files to sophgo devicetrees entry
riscv: dts: add initial Sophgo SG2042 SoC device tree
riscv: dts: sophgo: add Milk-V Pioneer board device tree
riscv: defconfig: enable SOPHGO SoCInochi Amaoto (2):
dt-bindings: timer: Add Sophgo sg2042 CLINT timer
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi.../sifive,plic-1.0.0.yaml | 1 + .../sophgo,sg2042-clint-mswi.yaml | 42 + .../devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/riscv/sophgo.yaml | 28 + .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 + .../devicetree/bindings/vendor-prefixes.yaml | 4 + MAINTAINERS | 9 + arch/riscv/Kconfig.socs | 5 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/sophgo/Makefile | 3 + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++ arch/riscv/configs/defconfig | 1 + 14 files changed, 2361 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml create mode 100644 arch/riscv/boot/dts/sophgo/Makefile create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsibase-commit:
0bb80ecc33a8fb5a682236443c1e740d5c917d1d--
2.25.1
Quoted 29 lines · Chen Wang <[email protected]> 于2023年9月28日周四 07:39写道：
Quoted 27 lines · Conor Dooley <[email protected]> 于2023年9月28日周四 00:09写道：
Hey,
Quoted 22 lines · Chen Wang
Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2] in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.Now only support basic uart drivers to boot up into a basic console.
Thanks,
Chen---
Changes in v3:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [5].
- add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
- updated maintainers info. for sophgo devicetree
- remove the quirk changes for uart
- updated dts, such as:
- add "riscv,isa-base"/"riscv,isa-extensions" for cpus
- update l2 cache node's name
- remove memory and pmu nodes
- fixed other issues as per input from reviewers.
Quoted 8 lines
Quoted 6 lines
v3 looks better indeed. I had some comments on the bindings and dt patches, but none were particularly major.
Thanks,
Conor.Thanks, Conor, I will continue imrpoving according to your commnents.
hi, Conor, one more question, what base should I take for next v4? I'm still using 6.6-rc1 and I see 6.6-rc3 has been released out.
Quoted 78 lines
Quoted 78 lines
Quoted 78 lines
Changes in v2:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [4].
- Improve format for comment of commitments as per input from last review.
- Improve format of DTS as per input from last review.
- Remove numa related stuff from DTS. This part is just for optimization, may add it later if really needed.Changes in v1:
The patch series is based on v6.6-rc1. Due to it is not sent in thread, I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or test the patches at the link [3].[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
[v1-0/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-1/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-2/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-3/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-4/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-5/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-6/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-7/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-8/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-9/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-10/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-11/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-12/12]:https://lore.kernel.org/linux-riscv/[email protected]/---
Chen Wang (9):
riscv: Add SOPHGO SOC familyKconfigsupport
dt-bindings: vendor-prefixes: add milkv/sophgo
dt-bindings: riscv: add sophgo sg2042 bindings
dt-bindings: riscv: Add T-HEAD C920 compatibles
dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
MAINTAINERS: add two files to sophgo devicetrees entry
riscv: dts: add initial Sophgo SG2042 SoC device tree
riscv: dts: sophgo: add Milk-V Pioneer board device tree
riscv: defconfig: enable SOPHGO SoCInochi Amaoto (2):
dt-bindings: timer: Add Sophgo sg2042 CLINT timer
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi.../sifive,plic-1.0.0.yaml | 1 + .../sophgo,sg2042-clint-mswi.yaml | 42 + .../devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/riscv/sophgo.yaml | 28 + .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 + .../devicetree/bindings/vendor-prefixes.yaml | 4 + MAINTAINERS | 9 + arch/riscv/Kconfig.socs | 5 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/sophgo/Makefile | 3 + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++ arch/riscv/configs/defconfig | 1 + 14 files changed, 2361 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml create mode 100644 arch/riscv/boot/dts/sophgo/Makefile create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsibase-commit:
0bb80ecc33a8fb5a682236443c1e740d5c917d1d--
2.25.1
Quoted 2 lines · Chen Wang
hi, Conor, one more question, what base should I take for next v4? I'm still using 6.6-rc1 and I see 6.6-rc3 has been released out.
-rc1 is fine :)