Add Milk-V Duo board support
Subsystems (6)
cover Add Milk-V Duo board support
Milk-V Duo[1] board is an embedded development platform based on the CV1800B[2] chip. Add minimal device tree files for the development board. Currently, now it's supported to boot to a basic shell.
NOTE: this series is based on the SG2042 upstream series for the vendor prefix and ARCH_SOPHGO option.
Jisheng Zhang (5):
dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic
dt-bindings: timer: Add SOPHGO CV1800B clint
dt-bindings: riscv: Add Milk-V Duo board compatibles
riscv: dts: sophgo: add initial CV1800B SoC device tree
riscv: dts: sophgo: add Milk-V Duo board device tree
.../sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/riscv/sophgo.yaml | 4 + .../bindings/timer/sifive,clint.yaml | 1 + arch/riscv/boot/dts/sophgo/Makefile | 2 +- .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 38 ++++++ arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++ 6 files changed, 162 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi
Signature · 1 line
2.40.1
PATCH 1/5 dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic
Add compatible string for SOPHGO CV1800B plic.
--- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +1 -0
@@ -65,6 +65,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - sophgo,cv1800-plic - sophgo,sg2042-plic - thead,th1520-plic - const: thead,c900-plic
Signature · 1 line
2.40.1
Re: [PATCH 1/5] dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic
Quoted 3 lines · Jisheng Zhang
Add compatible string for SOPHGO CV1800B plic.
Signed-off-by Jisheng Zhang <[email protected]>
Thanks,
Conor.
Quoted 19 lines
--- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +1
-0@@ -65,6 +65,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - sophgo,cv1800-plic - sophgo,sg2042-plic - thead,th1520-plic - const: thead,c900-plicSignature · 1 line
2.40.1
PATCH 2/5 dt-bindings: timer: Add SOPHGO CV1800B clint
In reply to Jisheng ZhangAdd compatible string for the SOPHGO CV1800B clint.
--- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/timer/sifive,clint.yaml +1 -0
@@ -37,6 +37,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - sophgo,cv1800-clint - thead,th1520-clint - const: thead,c900-clint - items:
Signature · 1 line
2.40.1
Re: [PATCH 2/5] dt-bindings: timer: Add SOPHGO CV1800B clint
Quoted 3 lines · Jisheng Zhang
Add compatible string for the SOPHGO CV1800B clint.
Signed-off-by Jisheng Zhang <[email protected]>
Quoted 19 lines
--- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/timer/sifive,clint.yaml +1
-0@@ -37,6 +37,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - sophgo,cv1800-clint - thead,th1520-clint - const: thead,c900-clint - items:Signature · 1 line
2.40.1
PATCH 3/5 dt-bindings: riscv: Add Milk-V Duo board compatibles
In reply to Jisheng ZhangDocument the compatible strings for the Milk-V Duo board[1] which uses the SOPHGO CV1800B SoC[2].
--- Documentation/devicetree/bindings/riscv/sophgo.yaml | 4 ++++ 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/riscv/sophgo.yaml +4 -0
@@ -18,6 +18,10 @@ properties: const: '/' compatible: oneOf: + - items: + - enum: + - milkv,duo + - const: sophgo,cv1800b - items: - enum: - milkv,pioneer
Signature · 1 line
2.40.1
Re: [PATCH 3/5] dt-bindings: riscv: Add Milk-V Duo board compatibles
Quoted 6 lines · Jisheng Zhang
Document the compatible strings for the Milk-V Duo board[1] which uses the SOPHGO CV1800B SoC[2].
Link https://milkv.io/duo [1]Signed-off-by Jisheng Zhang <[email protected]>
Thanks,
Conor.
Quoted 22 lines
--- Documentation/devicetree/bindings/riscv/sophgo.yaml | 4 ++++ 1 file changed, 4 insertions(+)Documentation/devicetree/bindings/riscv/sophgo.yaml +4
-0@@ -18,6 +18,10 @@ properties: const: '/' compatible: oneOf: + - items: + - enum: + - milkv,duo + - const: sophgo,cv1800b - items: - enum: - milkv,pioneerSignature · 1 line
2.40.1
Re: [PATCH 3/5] dt-bindings: riscv: Add Milk-V Duo board compatibles
In reply to Jisheng ZhangQuoted 15 lines · Jisheng Zhang
Document the compatible strings for the Milk-V Duo board[1] which uses the SOPHGO CV1800B SoC[2].
Link https://milkv.io/duo [1]Signed-off-by Jisheng Zhang <[email protected]>--- Documentation/devicetree/bindings/riscv/sophgo.yaml | 4 ++++ 1 file changed, 4 insertions(+)Documentation/devicetree/bindings/riscv/sophgo.yaml +0
-0
Documentation/devicetree/bindings/riscv/sophgo.yaml properties: · line 27
Quoted 10 lines
Documentation/devicetree/bindings/riscv/sophgo.yaml +4
-0@@ -18,6 +18,10 @@ properties: const: '/' compatible: oneOf: + - items: + - enum: + - milkv,duo + - const: sophgo,cv1800b - items: - enum: - milkv,pioneer
PATCH 4/5 riscv: dts: sophgo: add initial CV1800B SoC device tree
In reply to Jisheng ZhangAdd initial device tree for the CV1800B RISC-V SoC by SOPHGO.
--- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi
arch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +117 -0
@@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "sophgo,cv1800b"; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <1>; + #size-cells = <1>; + dma-noncoherent; + ranges; + + uart0: serial@04140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04140000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@04150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04150000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@04160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04160000 0x100>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@04170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04170000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@041c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x041c0000 0x100>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + }; +};
Signature · 1 line
2.40.1
PATCH 4/5 riscv: dts: sophgo: add initial CV1800B SoC device tree
Hi, Jisheng
You add the clint dt-bindings of CV1800B clint, but I don't see the clint node in this dt. The SBI needs this clint node to provide timer for linux. AFAIK, the dt of SBI comes from the linux or the bootloader, and bootloader may load the linux dt and pass it to the SBI. I think it is better to add the clint node.
In addition, please separate the peripheral node to a different file, which can be reused by both the CV1800 series and CV1810 series.
Thanks,
Inochi
Quoted 136 lines
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
Signed-off-by Jisheng Zhang <[email protected]>---
arch/riscv/boot/dts/sophgo/cv1800b.dtsi| 117 ++++++++++++++++++++++++1 file changed, 117 insertions(+)create mode 100644
arch/riscv/boot/dts/sophgo/cv1800b.dtsiarch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +117
-1@@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "sophgo,cv1800b"; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <1>; + #size-cells = <1>; + dma-noncoherent; + ranges; + + uart0: serial@04140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04140000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@04150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04150000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@04160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04160000 0x100>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@04170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04170000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@041c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x041c0000 0x100>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + }; +}; --2.40.1
Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
Quoted 5 lines · Inochi Amaoto
Hi, Jisheng
Quoted 1 line
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
Quoted 8 lines
You add the clint dt-bindings of CV1800B clint, but I don't see the clint node in this dt. The SBI needs this clint node to provide timer for linux. AFAIK, the dt of SBI comes from the linux or the bootloader, and bootloader may load the linux dt and pass it to the SBI. I think it is better to add the clint node.
In addition, please separate the peripheral node to a different file, which can be reused by both the CV1800 series and CV1810 series.
How do these SoCs differ?
Documentation seems rather lacking, but I was able to find something on github that suggests there is also a cv180zb. The difference between the three seems to, from a quick look, be their video encoding capabilities. Is that correct?
Cheers,
Conor.
Quoted 134 lines
Quoted 134 lines
Signed-off-by Jisheng Zhang <[email protected]>---
arch/riscv/boot/dts/sophgo/cv1800b.dtsi| 117 ++++++++++++++++++++++++1 file changed, 117 insertions(+)create mode 100644
arch/riscv/boot/dts/sophgo/cv1800b.dtsiarch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +117
-1@@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "sophgo,cv1800b"; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <1>; + #size-cells = <1>; + dma-noncoherent; + ranges; + + uart0: serial@04140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04140000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@04150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04150000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@04160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04160000 0x100>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@04170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04170000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@041c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x041c0000 0x100>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + }; +}; --2.40.1
Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
Quoted 12 lines · Inochi Amaoto
Quoted 10 lines
Hi, Jisheng
Quoted 1 line
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
You add the clint dt-bindings of CV1800B clint, but I don't see the clint node in this dt. The SBI needs this clint node to provide timer for linux. AFAIK, the dt of SBI comes from the linux or the bootloader, and bootloader may load the linux dt and pass it to the SBI. I think it is better to add the clint node.
Quoted 4 lines
Quoted 2 lines
In addition, please separate the peripheral node to a different file, which can be reused by both the CV1800 series and CV1810 series.
How do these SoCs differ?
AFAIK, the most peripheral of CV1800 and CV1810 are the same. there are only a few difference between CV1800 and CV1810:
1. CV1810 have mmc interrupt, but CV1800 have none
2. CV1810 have more RAM and a more powerful TPU.
3. Some models of CV1810 support I2S.
Also is some you have already mentioned, the video capabilities (including encoding, output steam number, input steam number) are different.
The only board with a CV1800 soc is Huashan Pi (CV1812H).
Quoted 5 lines
Documentation seems rather lacking, but I was able to find something on github that suggests there is also a cv180zb. The difference between the three seems to, from a quick look, be their video encoding capabilities. Is that correct?
Yes. it is correct.
It seems like you have forgot a chip called CV1801B, which has 128MB RAM. But I see no board with this soc, so at now it is not necessary to care it.
Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
Quoted 24 lines
Quoted 13 lines · Inochi Amaoto
Quoted 10 lines
Hi, Jisheng
Quoted 1 line
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
You add the clint dt-bindings of CV1800B clint, but I don't see the clint node in this dt. The SBI needs this clint node to provide timer for linux. AFAIK, the dt of SBI comes from the linux or the bootloader, and bootloader may load the linux dt and pass it to the SBI. I think it is better to add the clint node.
Quoted 4 lines
Quoted 2 lines
In addition, please separate the peripheral node to a different file, which can be reused by both the CV1800 series and CV1810 series.
How do these SoCs differ?
AFAIK, the most peripheral of CV1800 and CV1810 are the same. there are only a few difference between CV1800 and CV1810:
1. CV1810 have mmc interrupt, but CV1800 have none
2. CV1810 have more RAM and a more powerful TPU.
3. Some models of CV1810 support I2S.
Quoted 5 lines
Also is some you have already mentioned, the video capabilities (including encoding, output steam number, input steam number) are different.
The only board with a CV1800 soc is Huashan Pi (CV1812H).
A mistake, I mean CV1810 soc, not the CV1800 one.
Quoted 12 lines
Quoted 5 lines
Documentation seems rather lacking, but I was able to find something on github that suggests there is also a cv180zb. The difference between the three seems to, from a quick look, be their video encoding capabilities. Is that correct?
Yes. it is correct.
It seems like you have forgot a chip called CV1801B, which has 128MB RAM. But I see no board with this soc, so at now it is not necessary to care it.
Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
Quoted 24 lines · Inochi Amaoto
Quoted 24 lines
Quoted 13 lines · Inochi Amaoto
Quoted 10 lines
Hi, Jisheng
Quoted 1 line
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
You add the clint dt-bindings of CV1800B clint, but I don't see the clint node in this dt. The SBI needs this clint node to provide timer for linux. AFAIK, the dt of SBI comes from the linux or the bootloader, and bootloader may load the linux dt and pass it to the SBI. I think it is better to add the clint node.
Quoted 4 lines
Quoted 2 lines
In addition, please separate the peripheral node to a different file, which can be reused by both the CV1800 series and CV1810 series.
How do these SoCs differ?
AFAIK, the most peripheral of CV1800 and CV1810 are the same. there are only a few difference between CV1800 and CV1810:
1. CV1810 have mmc interrupt, but CV1800 have none
2. CV1810 have more RAM and a more powerful TPU.
3. Some models of CV1810 support I2S.
Quoted 18 lines
Quoted 5 lines
Also is some you have already mentioned, the video capabilities (including encoding, output steam number, input steam number) are different.
The only board with a CV1800 soc is Huashan Pi (CV1812H).
A mistake, I mean CV1810 soc, not the CV1800 one.
Quoted 10 lines
Quoted 5 lines
Documentation seems rather lacking, but I was able to find something on github that suggests there is also a cv180zb. The difference between the three seems to, from a quick look, be their video encoding capabilities. Is that correct?
Yes. it is correct.
It seems like you have forgot a chip called CV1801B, which has 128MB RAM. But I see no board with this soc, so at now it is not necessary to care it.
FWIW, I do not mind if the properties are left inside a CV1800B specific file, and moved out at a later date if/when someone actually upstreams support for a board with that SoC.
Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
In reply to Jisheng ZhangQuoted 51 lines · Jisheng Zhang
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
Signed-off-by Jisheng Zhang <[email protected]>--- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsiarch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +37
-0@@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "sophgo,cv1800b"; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>;
arch/riscv/boot/dts/sophgo/cv1800b.dtsi line 47
Quoted 10 lines
arch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +10
-0+ #interrupt-cells = <1>; + }; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + };
Is this a stub that will later be replaced by a real clock controller node, or is this actually a fixed oscillator? If it is the former, could you add it to the commit message if there is a respin?
Thanks,
Conor.
Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
Quoted 57 lines · Conor Dooley
Quoted 56 lines · Jisheng Zhang
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
Signed-off-by Jisheng Zhang <[email protected]>--- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsiarch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +42
-0@@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "sophgo,cv1800b"; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; +
Quoted 8 lines
arch/riscv/boot/dts/sophgo/cv1800b.dtsi line 47
Quoted 5 lines
arch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +5
-0+ osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + };Is this a stub that will later be replaced by a real clock controller node, or is this actually a fixed oscillator? If it is the former, could
Hi Conor,
This is a real 25MHZ oscillator.
Thanks
Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
In reply to Jisheng Zhangarch/riscv/boot/dts/sophgo/cv1800b.dtsi line 108
Quoted 2 lines · Jisheng Zhang
arch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +2
-0+ plic: interrupt-controller@70000000 { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
This fails dtbs_check, the compatible you added to the binding is cv1800-plic.
Quoted 7 lines
arch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +7
-0+ reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + };
Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
In reply to Jisheng ZhangQuoted 7 lines · Jisheng Zhang
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
Signed-off-by Jisheng Zhang <[email protected]>--- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+)create mode 100644
arch/riscv/boot/dts/sophgo/cv1800b.dtsi
Hi, Jisheng, as far as I know, sg2042 and cv180x are now tracked by different people and even in sophgo, they are two independent projects(sg2042 is target for HPC and cv180x is target for embeded device). To facilitate future management and review, I recommend registering the maintainer information in two entries in MAINTAINERS. The example is as follows:
``` SOPHGO CV180X DEVICETREES M: Jisheng Zhang <[email protected]> F: arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts F: arch/riscv/boot/dts/sophgo/cv1800b.dtsi SOPHGO SG2042 DEVICETREES M: Chao Wei <[email protected]> M: Chen Wang <[email protected]> S: Maintained F: arch/riscv/boot/dts/sophgo/Makefile F: arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi F: arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts F: arch/riscv/boot/dts/sophgo/sg2042.dtsi F: Documentation/devicetree/bindings/riscv/sophgo.yaml ```
For Makefile and sophgo.yaml such common files, just keep in sg2042 entry should be fine.
@Conor, what do you think?
Thanks,
Chen
Quoted 123 lines
arch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +117
-0@@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "sophgo,cv1800b"; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <1>; + #size-cells = <1>; + dma-noncoherent; + ranges; + + uart0: serial@04140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04140000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@04150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04150000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@04160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04160000 0x100>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@04170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04170000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@041c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x041c0000 0x100>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + }; +};
Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
Quoted 35 lines · Chen Wang
Quoted 7 lines · Jisheng Zhang
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
Signed-off-by Jisheng Zhang <[email protected]>--- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+)create mode 100644
arch/riscv/boot/dts/sophgo/cv1800b.dtsiHi, Jisheng, as far as I know, sg2042 and cv180x are now tracked by different people and even in sophgo, they are two independent projects(sg2042 is target for HPC and cv180x is target for embeded device). To facilitate future management and review, I recommend registering the maintainer information in two entries in
MAINTAINERS. The example is as follows:``` SOPHGO CV180X DEVICETREES M: Jisheng Zhang <[email protected]> F: arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts F: arch/riscv/boot/dts/sophgo/cv1800b.dtsi SOPHGO SG2042 DEVICETREES M: Chao Wei <[email protected]> M: Chen Wang <[email protected]> S: Maintained F: arch/riscv/boot/dts/sophgo/Makefile F: arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi F: arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts F: arch/riscv/boot/dts/sophgo/sg2042.dtsi F: Documentation/devicetree/bindings/riscv/sophgo.yaml ```
Quoted 4 lines
For
Makefileandsophgo.yamlsuch common files, just keep in sg2042 entry should be fine.@Conor, what do you think?
We do no have usually per-board maintainer entries (with few exceptions). I strongly prefer this one instead:
https://lore.kernel.org/all/[email protected]/
Best regards,
Krzysztof
Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
Quoted 39 lines · Krzysztof Kozlowski
Quoted 38 lines · Chen Wang
Quoted 7 lines · Jisheng Zhang
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
Signed-off-by Jisheng Zhang <[email protected]>--- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+)create mode 100644
arch/riscv/boot/dts/sophgo/cv1800b.dtsiHi, Jisheng, as far as I know, sg2042 and cv180x are now tracked by different people and even in sophgo, they are two independent projects(sg2042 is target for HPC and cv180x is target for embeded device). To facilitate future management and review, I recommend registering the maintainer information in two entries in
MAINTAINERS. The example is as follows:``` SOPHGO CV180X DEVICETREES M: Jisheng Zhang <[email protected]> F: arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts F: arch/riscv/boot/dts/sophgo/cv1800b.dtsi SOPHGO SG2042 DEVICETREES M: Chao Wei <[email protected]> M: Chen Wang <[email protected]> S: Maintained F: arch/riscv/boot/dts/sophgo/Makefile F: arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi F: arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts F: arch/riscv/boot/dts/sophgo/sg2042.dtsi F: Documentation/devicetree/bindings/riscv/sophgo.yaml ```For
Makefileandsophgo.yamlsuch common files, just keep in sg2042 entry should be fine.
Quoted 6 lines
Quoted 1 line
@Conor, what do you think?
We do no have usually per-board maintainer entries (with few exceptions). I strongly prefer this one instead:
I don't like the suggestion here for a different reason! While I'm fine with having some per-board SoC maintainers, esp. since the cv1800 stuff is very different to the sg2042, I want to see someone step up to apply the patches for the whole arch/riscv/boot/dts/sophgo/ directory once more comfortable with the process, not reduce the entry to cover just the 64 core SoC.
Thanks,
Conor.
Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
Quoted 50 lines · Conor Dooley
Quoted 34 lines · Krzysztof Kozlowski
Quoted 33 lines · Chen Wang
Quoted 7 lines · Jisheng Zhang
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
Signed-off-by Jisheng Zhang <[email protected]>--- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+)create mode 100644
arch/riscv/boot/dts/sophgo/cv1800b.dtsiHi, Jisheng, as far as I know, sg2042 and cv180x are now tracked by different people and even in sophgo, they are two independent projects(sg2042 is target for HPC and cv180x is target for embeded device). To facilitate future management and review, I recommend registering the maintainer information in two entries in
MAINTAINERS. The example is as follows:``` SOPHGO CV180X DEVICETREES M: Jisheng Zhang <[email protected]> F: arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts F: arch/riscv/boot/dts/sophgo/cv1800b.dtsi SOPHGO SG2042 DEVICETREES M: Chao Wei <[email protected]> M: Chen Wang <[email protected]> S: Maintained F: arch/riscv/boot/dts/sophgo/Makefile F: arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi F: arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts F: arch/riscv/boot/dts/sophgo/sg2042.dtsi F: Documentation/devicetree/bindings/riscv/sophgo.yaml ```Quoted 8 lines
Quoted 4 lines
For
Makefileandsophgo.yamlsuch common files, just keep in sg2042 entry should be fine.@Conor, what do you think?
We do no have usually per-board maintainer entries (with few exceptions). I strongly prefer this one instead:
I don't like the suggestion here for a different reason! While I'm fine with having some per-board SoC maintainers, esp. since the cv1800 stuff is very different to the sg2042, I want to see someone step up to apply the patches for the whole
arch/riscv/boot/dts/sophgo/directory once more comfortable with the process, not reduce the entry to cover just the 64 core SoC.
Quoted 2 lines
Thanks,
Conor.
Thanks, Conor and Krzystof. Agree with you, it would be better to keep only one entry for arch/riscv/boot/dts/sophgo/ directory. I will discuss with other people working on sophgo and specify a unified maintenance task to maintain files under it.
PATCH 5/5 riscv: dts: sophgo: add Milk-V Duo board device tree
In reply to Jisheng ZhangMilk-V Duo[1] board is an embedded development platform based on the CV1800B chip. Add minimal device tree files for the development board.
Support basic uart drivers, so supports booting to a basic shell.
--- arch/riscv/boot/dts/sophgo/Makefile | 2 +- .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 38 +++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
arch/riscv/boot/dts/sophgo/Makefile +1 -1
@@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb - +dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts new file +38 -0
@@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +/dts-v1/; + +#include "cv1800b.dtsi" + +/ { + model = "Milk-V Duo"; + compatible = "milkv,duo", "sophgo,cv1800b"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x3f40000>; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +};
Signature · 1 line
2.40.1
Re: [PATCH 5/5] riscv: dts: sophgo: add Milk-V Duo board device tree
Quoted 18 lines · Jisheng Zhang
Milk-V Duo[1] board is an embedded development platform based on the CV1800B chip. Add minimal device tree files for the development board.
Support basic uart drivers, so supports booting to a basic shell.
Link https://milkv.io/duo [1]Signed-off-by Jisheng Zhang <[email protected]>--- arch/riscv/boot/dts/sophgo/Makefile | 2 +- .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 38 +++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-)create mode 100644
arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dtsarch/riscv/boot/dts/sophgo/Makefile +0
-0
arch/riscv/boot/dts/sophgo/Makefile line 3
Quoted 4 lines
arch/riscv/boot/dts/sophgo/Makefile +1
-1@@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb - +dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
Please adjust it in alphabetical order.
Quoted 44 lines
arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts new file +38
-0@@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +/dts-v1/; + +#include "cv1800b.dtsi" + +/ { + model = "Milk-V Duo"; + compatible = "milkv,duo", "sophgo,cv1800b"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x3f40000>; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +};
Quoted 6 lines · Jisheng Zhang
Milk-V Duo[1] board is an embedded development platform based on the CV1800B[2] chip. Add minimal device tree files for the development board. Currently, now it's supported to boot to a basic shell.
NOTE: this series is based on the SG2042 upstream series for the vendor prefix and
ARCH_SOPHGOoption.
Missing reference to [3].
Quoted 22 lines
Link https://milkv.io/duo [1]Jisheng Zhang (5):
dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic
dt-bindings: timer: Add SOPHGO CV1800B clint
dt-bindings: riscv: Add Milk-V Duo board compatibles
riscv: dts: sophgo: add initial CV1800B SoC device tree
riscv: dts: sophgo: add Milk-V Duo board device tree.../sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/riscv/sophgo.yaml | 4 + .../bindings/timer/sifive,clint.yaml | 1 + arch/riscv/boot/dts/sophgo/Makefile | 2 +- .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 38 ++++++ arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++ 6 files changed, 162 insertions(+), 1 deletion(-)create mode 100644
arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dtscreate mode 100644arch/riscv/boot/dts/sophgo/cv1800b.dtsi
Quoted 9 lines · Chen Wang
Quoted 6 lines · Jisheng Zhang
Milk-V Duo[1] board is an embedded development platform based on the CV1800B[2] chip. Add minimal device tree files for the development board. Currently, now it's supported to boot to a basic shell.
NOTE: this series is based on the SG2042 upstream series for the vendor prefix and
ARCH_SOPHGOoption.Missing reference to [3].
Should be fine without it :)
Quoted 22 lines
Quoted 22 lines
Link https://milkv.io/duo [1]Jisheng Zhang (5):
dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic
dt-bindings: timer: Add SOPHGO CV1800B clint
dt-bindings: riscv: Add Milk-V Duo board compatibles
riscv: dts: sophgo: add initial CV1800B SoC device tree
riscv: dts: sophgo: add Milk-V Duo board device tree.../sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/riscv/sophgo.yaml | 4 + .../bindings/timer/sifive,clint.yaml | 1 + arch/riscv/boot/dts/sophgo/Makefile | 2 +- .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 38 ++++++ arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++ 6 files changed, 162 insertions(+), 1 deletion(-)create mode 100644
arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dtscreate mode 100644arch/riscv/boot/dts/sophgo/cv1800b.dtsi
Hey,
Quoted 10 lines · Jisheng Zhang
Milk-V Duo[1] board is an embedded development platform based on the CV1800B[2] chip. Add minimal device tree files for the development board. Currently, now it's supported to boot to a basic shell.
NOTE: this series is based on the SG2042 upstream series for the vendor prefix and
ARCH_SOPHGOoption.
Other than the comment I left, this seems fine to me. I'd be happy enough to pick up the pre-reqs from the other series & this one if one of the Sophgo maintainers acked these patches.
Thanks,
Conor.
Quoted 10 lines · Conor Dooley
Hey,
Quoted 7 lines · Jisheng Zhang
Milk-V Duo[1] board is an embedded development platform based on the CV1800B[2] chip. Add minimal device tree files for the development board. Currently, now it's supported to boot to a basic shell.
NOTE: this series is based on the SG2042 upstream series for the vendor prefix and
ARCH_SOPHGOoption.
Quoted 6 lines
Quoted 3 lines
Other than the comment I left, this seems fine to me. I'd be happy enough to pick up the pre-reqs from the other series & this one if one of the Sophgo maintainers acked these patches.
Conor, just FYI, sophgo maintainers are located in China, and they are in National holiday vacation these days. I think they may reply to emails later this weekend.
Thanks,
Chen
Quoted 8 lines
Thanks,
Conor._______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv
Quoted 12 lines · Chen Wang
Quoted 10 lines · Conor Dooley
Hey,
Quoted 7 lines · Jisheng Zhang
Milk-V Duo[1] board is an embedded development platform based on the CV1800B[2] chip. Add minimal device tree files for the development board. Currently, now it's supported to boot to a basic shell.
NOTE: this series is based on the SG2042 upstream series for the vendor prefix and
ARCH_SOPHGOoption.
Quoted 8 lines
Quoted 6 lines
Quoted 3 lines
Other than the comment I left, this seems fine to me. I'd be happy enough to pick up the pre-reqs from the other series & this one if one of the Sophgo maintainers acked these patches.
Conor, just FYI, sophgo maintainers are located in China, and they are in National holiday vacation these days. I think they may reply to emails later this weekend.
Firstly, there isn't some super rush here that a few days holiday will interfere with. I'm actually on holidays myself at the moment :)
Secondly, you're one of the sophgo maintainers,
right? It's the people listed in MAINTAINERS that I am talking about here, being an employee doesn't matter.
Cheers,
Conor.
Quoted 13 lines
Thanks,
Chen
Quoted 8 lines
Thanks,
Conor._______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv