PCIe RK3399 clock and reset using new helper functions

Refactor the clock handling in the Rockchip PCIe driver, introducing a more robust and efficient method for enabling and disabling clocks using clk_bulk*() API. Using the clk_bulk APIs,

the clock handling for the core clocks becomes much simpler.

- Replace devm_clk_get() with devm_clk_bulk_get_all().
- Replace clk_prepare_enable() with clk_bulk_prepare_enable().
- Replace clk_disable_unprepare() with clk_bulk_disable_unprepare().

Signed-off-by Anand Moon <[email protected]>

---
v7: Update the functional change in commmit message.
v6: None.
v5: switch to use use devm_clk_bulk_get_all()? gets rid of hardcoding the
clock names in driver.
v4: use dev_err_probe for error patch.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot.

---
 drivers/pci/controller/pcie-rockchip.c | 65 +++-----------------------
 drivers/pci/controller/pcie-rockchip.h |  7 ++-
 2 files changed, 10 insertions(+), 62 deletions(-)

drivers/pci/controller/pcie-rockchip.c +7 -58

index c07d7129f1c7..2777ef0cb599 100644
@@ -127,29 +127,9 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
 					     "failed to get ep GPIO\n");
 	}
 
-	rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
-	if (IS_ERR(rockchip->aclk_pcie)) {
-		dev_err(dev, "aclk clock not found\n");
-		return PTR_ERR(rockchip->aclk_pcie);
-	}
-
-	rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
-	if (IS_ERR(rockchip->aclk_perf_pcie)) {
-		dev_err(dev, "aclk_perf clock not found\n");
-		return PTR_ERR(rockchip->aclk_perf_pcie);
-	}
-
-	rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
-	if (IS_ERR(rockchip->hclk_pcie)) {
-		dev_err(dev, "hclk clock not found\n");
-		return PTR_ERR(rockchip->hclk_pcie);
-	}
-
-	rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
-	if (IS_ERR(rockchip->clk_pcie_pm)) {
-		dev_err(dev, "pm clock not found\n");
-		return PTR_ERR(rockchip->clk_pcie_pm);
-	}
+	rockchip->num_clks = devm_clk_bulk_get_all(dev, &rockchip->clks);
+	if (rockchip->num_clks < 0)
+		return dev_err_probe(dev, err, "failed to get clocks\n");
 
 	return 0;
 }

@@ -372,39 +352,11 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
 	struct device *dev = rockchip->dev;
 	int err;
 
-	err = clk_prepare_enable(rockchip->aclk_pcie);
-	if (err) {
-		dev_err(dev, "unable to enable aclk_pcie clock\n");
-		return err;
-	}
-
-	err = clk_prepare_enable(rockchip->aclk_perf_pcie);
-	if (err) {
-		dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
-		goto err_aclk_perf_pcie;
-	}
-
-	err = clk_prepare_enable(rockchip->hclk_pcie);
-	if (err) {
-		dev_err(dev, "unable to enable hclk_pcie clock\n");
-		goto err_hclk_pcie;
-	}
-
-	err = clk_prepare_enable(rockchip->clk_pcie_pm);
-	if (err) {
-		dev_err(dev, "unable to enable clk_pcie_pm clock\n");
-		goto err_clk_pcie_pm;
-	}
+	err = clk_bulk_prepare_enable(rockchip->num_clks, rockchip->clks);
+	if (err)
+		return dev_err_probe(dev, err, "failed to enable clocks\n");
 
 	return 0;
-
-err_clk_pcie_pm:
-	clk_disable_unprepare(rockchip->hclk_pcie);
-err_hclk_pcie:
-	clk_disable_unprepare(rockchip->aclk_perf_pcie);
-err_aclk_perf_pcie:
-	clk_disable_unprepare(rockchip->aclk_pcie);
-	return err;
 }
 EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
 

@@ -412,10 +364,7 @@ void rockchip_pcie_disable_clocks(void *data)
 {
 	struct rockchip_pcie *rockchip = data;
 
-	clk_disable_unprepare(rockchip->clk_pcie_pm);
-	clk_disable_unprepare(rockchip->hclk_pcie);
-	clk_disable_unprepare(rockchip->aclk_perf_pcie);
-	clk_disable_unprepare(rockchip->aclk_pcie);
+	clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks);
 }
 EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks);
 

drivers/pci/controller/pcie-rockchip.h +3 -4

index 6111de35f84c..bebab80c9553 100644
@@ -11,6 +11,7 @@
 #ifndef _PCIE_ROCKCHIP_H
 #define _PCIE_ROCKCHIP_H
 
+#include <linux/clk.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/pci-ecam.h>

@@ -299,10 +300,8 @@ struct rockchip_pcie {
 	struct	reset_control *pm_rst;
 	struct	reset_control *aclk_rst;
 	struct	reset_control *pclk_rst;
-	struct	clk *aclk_pcie;
-	struct	clk *aclk_perf_pcie;
-	struct	clk *hclk_pcie;
-	struct	clk *clk_pcie_pm;
+	struct  clk_bulk_data *clks;
+	int	num_clks;
 	struct	regulator *vpcie12v; /* 12V power supply */
 	struct	regulator *vpcie3v3; /* 3.3V power supply */
 	struct	regulator *vpcie1v8; /* 1.8V power supply */

Signature · 1 line

2.44.0

Quoted 3 lines · Anand Moon

Refactor the clock handling in the Rockchip PCIe driver, introducing a more robust and efficient method for enabling and disabling clocks using clk_bulk*() API. Using the clk_bulk APIs,

I think I mentioned earlier to use impreative tone in commit messages.

Quoted 1 line

the clock handling for the core clocks becomes much simpler.

Quoted 1 line

Could you please elaborate how? i.e., devm_clk_bulk_get_all() allows the driver to get all clocks defined in the DT thereby removing the hardcoded clock names in the driver.

Quoted 5 lines

- Replace devm_clk_get() with devm_clk_bulk_get_all().
- Replace clk_prepare_enable() with clk_bulk_prepare_enable().
- Replace clk_disable_unprepare() with clk_bulk_disable_unprepare().

Signed-off-by Anand Moon <[email protected]>

With above changes,

Reviewed-by Manivannan Sadhasivam <[email protected]>

- Mani

Refactor the reset control handling in the Rockchip PCIe driver, introducing a more robust and efficient method for assert and deassert reset controller using reset_control_bulk*() API. Using the reset_control_bulk APIs, the reset handling for the core clocks reset unit becomes much simpler.

Spilt the reset controller in two groups as pre the RK3399 TRM.

After power up, the software driver should de-assert the reset of PCIe PHY, then wait the PLL locked by polling the status, if PLL
has locked, then can de-assert the reset simultaneously
driver need to De-assert the reset pins simultionaly.

PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.

- replace devm_reset_control_get_exclusive() with
devm_reset_control_bulk_get_exclusive().
- replace reset_control_assert with
reset_control_bulk_assert().
- replace reset_control_deassert with
reset_control_bulk_deassert().

Signed-off-by Anand Moon <[email protected]>

---
v7: replace devm_reset_control_bulk_get_optional_exclusive()
with devm_reset_control_bulk_get_exclusive()
update the functional changes.
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: use dev_err_probe in error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning.

---
 drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
 drivers/pci/controller/pcie-rockchip.h |  26 +++--
 2 files changed, 49 insertions(+), 128 deletions(-)

drivers/pci/controller/pcie-rockchip.c +0 -0

index 2777ef0cb599..9a118e2b8cbd 100644
@@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)

drivers/pci/controller/pcie-rockchip.c +0 -17

 	for (i = 0; i < MAX_LANE_NUM; i++) {
 		err = phy_init(rockchip->phys[i]);

@@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 		}
 	}
 
-	err = reset_control_assert(rockchip->core_rst);
-	if (err) {
-		dev_err(dev, "assert core_rst err %d\n", err);
-		goto err_exit_phy;
-	}
-
-	err = reset_control_assert(rockchip->mgmt_rst);
-	if (err) {
-		dev_err(dev, "assert mgmt_rst err %d\n", err);
-		goto err_exit_phy;
-	}
-
-	err = reset_control_assert(rockchip->mgmt_sticky_rst);
-	if (err) {
-		dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
-		goto err_exit_phy;
-	}

drivers/pci/controller/pcie-rockchip.c +1 -7

 	udelay(10);
 
-	err = reset_control_deassert(rockchip->pm_rst);
-	if (err) {
-		dev_err(dev, "deassert pm_rst err %d\n", err);
-		goto err_exit_phy;
-	}
-
-	err = reset_control_deassert(rockchip->aclk_rst);
+	err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS,

drivers/pci/controller/pcie-rockchip.c +2 -11

 	 */
-	err = reset_control_deassert(rockchip->mgmt_sticky_rst);
-	if (err) {
-		dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
-		goto err_power_off_phy;
-	}
-
-	err = reset_control_deassert(rockchip->core_rst);
+	err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS,
+					  rockchip->core_rsts);
 	if (err) {
-		dev_err(dev, "deassert core_rst err %d\n", err);
-		goto err_power_off_phy;
-	}
-

Quoted 6 lines · Anand Moon

Refactor the reset control handling in the Rockchip PCIe driver, introducing a more robust and efficient method for assert and deassert reset controller using reset_control_bulk*() API. Using the reset_control_bulk APIs, the reset handling for the core clocks reset unit becomes much simpler.

Same comments as previous patch.

Quoted 1 line

Spilt the reset controller in two groups as pre the RK3399 TRM.

*per

Also please state the TRM name and section for reference.

Quoted 37 lines

After power up, the software driver should de-assert the reset of PCIe PHY, then wait the PLL locked by polling the status, if PLL
has locked, then can de-assert the reset simultaneously
driver need to De-assert the reset pins simultionaly.

PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.

- replace devm_reset_control_get_exclusive() with
devm_reset_control_bulk_get_exclusive().
- replace reset_control_assert with
reset_control_bulk_assert().
- replace reset_control_deassert with
reset_control_bulk_deassert().

Signed-off-by Anand Moon <[email protected]>

---
v7: replace devm_reset_control_bulk_get_optional_exclusive()
with devm_reset_control_bulk_get_exclusive()
update the functional changes.
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: use dev_err_probe in error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning.

---
 drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
 drivers/pci/controller/pcie-rockchip.h |  26 +++--
 2 files changed, 49 insertions(+), 128 deletions(-)

drivers/pci/controller/pcie-rockchip.c +0 -0

index 2777ef0cb599..9a118e2b8cbd 100644
@@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)

[...]

drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) · line 121

Quoted 4 lines

drivers/pci/controller/pcie-rockchip.c +4 -0

+     err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS,
+                                     rockchip->pm_rsts);
+     if (err)
+             return dev_err_probe(dev, err, "reset bulk assert pm reset\n");

'Couldn't assert PM resets'

Quoted 24 lines

      for (i = 0; i < MAX_LANE_NUM; i++) {
              err = phy_init(rockchip->phys[i]);

drivers/pci/controller/pcie-rockchip.c +0 -17

@@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
              }
      }
 
-     err = reset_control_assert(rockchip->core_rst);
-     if (err) {
-             dev_err(dev, "assert core_rst err %d\n", err);
-             goto err_exit_phy;
-     }
-
-     err = reset_control_assert(rockchip->mgmt_rst);
-     if (err) {
-             dev_err(dev, "assert mgmt_rst err %d\n", err);
-             goto err_exit_phy;
-     }
-
-     err = reset_control_assert(rockchip->mgmt_sticky_rst);
-     if (err) {
-             dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
-             goto err_exit_phy;
-     }

drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) · line 134

Quoted 10 lines

drivers/pci/controller/pcie-rockchip.c +4 -6

-
-     err = reset_control_assert(rockchip->pipe_rst);
-     if (err) {
-             dev_err(dev, "assert pipe_rst err %d\n", err);
-             goto err_exit_phy;
-     }
+     err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS,
+                                     rockchip->core_rsts);
+     if (err)
+             return dev_err_probe(dev, err, "reset bulk assert core reset\n");

'Couldn't assert Core resets'

Quoted 11 lines

drivers/pci/controller/pcie-rockchip.c +1 -7

      udelay(10);
 
-     err = reset_control_deassert(rockchip->pm_rst);
-     if (err) {
-             dev_err(dev, "deassert pm_rst err %d\n", err);
-             goto err_exit_phy;
-     }
-
-     err = reset_control_deassert(rockchip->aclk_rst);
+     err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS,

drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) · line 141

Quoted 10 lines

drivers/pci/controller/pcie-rockchip.c +2 -7

+                                       rockchip->pm_rsts);
      if (err) {
-             dev_err(dev, "deassert aclk_rst err %d\n", err);
-             goto err_exit_phy;
-     }
-
-     err = reset_control_deassert(rockchip->pclk_rst);
-     if (err) {
-             dev_err(dev, "deassert pclk_rst err %d\n", err);
+             dev_err(dev, "reset bulk deassert pm err %d\n", err);

'Couldn't deassert PM resets'

drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) · line 182

Quoted 6 lines

drivers/pci/controller/pcie-rockchip.c +0 -0

              goto err_exit_phy;
      }
 

@@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
       * Please don't reorder the deassert sequence of the following
       * four reset pins.

I don't think my earlier comment on this addressed. Why are you changing the reset order? Why can't you have the resets in below (older) order?

static const char * const rockchip_pci_core_rsts[] = {
        mgmt-sticky",
        "core",
        "mgmt",
        "pipe",
};

Also, this comment should be removed now.

Quoted 15 lines

drivers/pci/controller/pcie-rockchip.c +2 -11

       */
-     err = reset_control_deassert(rockchip->mgmt_sticky_rst);
-     if (err) {
-             dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
-             goto err_power_off_phy;
-     }
-
-     err = reset_control_deassert(rockchip->core_rst);
+     err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS,
+                                       rockchip->core_rsts);
      if (err) {
-             dev_err(dev, "deassert core_rst err %d\n", err);
-             goto err_power_off_phy;
-     }
-

drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) · line 187

Quoted 10 lines

drivers/pci/controller/pcie-rockchip.c +1 -9

-     err = reset_control_deassert(rockchip->mgmt_rst);
-     if (err) {
-             dev_err(dev, "deassert mgmt_rst err %d\n", err);
-             goto err_power_off_phy;
-     }
-
-     err = reset_control_deassert(rockchip->pipe_rst);
-     if (err) {
-             dev_err(dev, "deassert pipe_rst err %d\n", err);
+             dev_err(dev, "reset bulk deassert core err %d\n", err);

'Couldn't deassert Core resets'

- Mani

--
மணிவண்ணன் சதாசிவம்

Hi Manivannan,

Thanks for your review comments.

Quoted 11 lines · Manivannan Sadhasivam

Quoted 6 lines · Anand Moon

Refactor the reset control handling in the Rockchip PCIe driver, introducing a more robust and efficient method for assert and deassert reset controller using reset_control_bulk*() API. Using the reset_control_bulk APIs, the reset handling for the core clocks reset unit becomes much simpler.

Same comments as previous patch.

I will explain more about this.

Quoted 6 lines

Quoted 1 line

Spilt the reset controller in two groups as pre the RK3399 TRM.

*per

Also please state the TRM name and section for reference.

Yes

Quoted 36 lines

Quoted 36 lines

After power up, the software driver should de-assert the reset of PCIe PHY, then wait the PLL locked by polling the status, if PLL
has locked, then can de-assert the reset simultaneously
driver need to De-assert the reset pins simultionaly.

PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.

- replace devm_reset_control_get_exclusive() with
devm_reset_control_bulk_get_exclusive().
- replace reset_control_assert with
reset_control_bulk_assert().
- replace reset_control_deassert with
reset_control_bulk_deassert().

Signed-off-by Anand Moon <[email protected]>

---
v7: replace devm_reset_control_bulk_get_optional_exclusive()
with devm_reset_control_bulk_get_exclusive()
update the functional changes.
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: use dev_err_probe in error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning.

---
 drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
 drivers/pci/controller/pcie-rockchip.h |  26 +++--
 2 files changed, 49 insertions(+), 128 deletions(-)

drivers/pci/controller/pcie-rockchip.c +0 -0

index 2777ef0cb599..9a118e2b8cbd 100644

Quoted 7 lines

drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) · line 182

Quoted 3 lines

drivers/pci/controller/pcie-rockchip.c +0 -0

@@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
       * Please don't reorder the deassert sequence of the following
       * four reset pins.

I don't think my earlier comment on this addressed. Why are you changing the reset order? Why can't you have the resets in below (older) order?

Quoted 6 lines

static const char * const rockchip_pci_core_rsts[] = {
        mgmt-sticky",
        "core",
        "mgmt",
        "pipe",
};

I will add a comment on this above.

Quoted 61 lines · Anand Moon

Hi Manivannan,

Thanks for your review comments.

Quoted 11 lines · Manivannan Sadhasivam

Quoted 6 lines · Anand Moon

Refactor the reset control handling in the Rockchip PCIe driver, introducing a more robust and efficient method for assert and deassert reset controller using reset_control_bulk*() API. Using the reset_control_bulk APIs, the reset handling for the core clocks reset unit becomes much simpler.

Same comments as previous patch.

I will explain more about this.

Quoted 6 lines

Quoted 1 line

Spilt the reset controller in two groups as pre the RK3399 TRM.

*per

Also please state the TRM name and section for reference.

Yes

Quoted 36 lines

Quoted 36 lines

After power up, the software driver should de-assert the reset of PCIe PHY, then wait the PLL locked by polling the status, if PLL
has locked, then can de-assert the reset simultaneously
driver need to De-assert the reset pins simultionaly.

PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.

- replace devm_reset_control_get_exclusive() with
devm_reset_control_bulk_get_exclusive().
- replace reset_control_assert with
reset_control_bulk_assert().
- replace reset_control_deassert with
reset_control_bulk_deassert().

Signed-off-by Anand Moon <[email protected]>

---
v7: replace devm_reset_control_bulk_get_optional_exclusive()
with devm_reset_control_bulk_get_exclusive()
update the functional changes.
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: use dev_err_probe in error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning.

---
 drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
 drivers/pci/controller/pcie-rockchip.h |  26 +++--
 2 files changed, 49 insertions(+), 128 deletions(-)

drivers/pci/controller/pcie-rockchip.c +0 -0

index 2777ef0cb599..9a118e2b8cbd 100644

[...]

Quoted 7 lines

Quoted 7 lines

drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) · line 182

Quoted 3 lines

drivers/pci/controller/pcie-rockchip.c +0 -0

@@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
       * Please don't reorder the deassert sequence of the following
       * four reset pins.

I don't think my earlier comment on this addressed. Why are you changing the reset order? Why can't you have the resets in below (older) order?

Quoted 7 lines

Quoted 6 lines

static const char * const rockchip_pci_core_rsts[] = {
        mgmt-sticky",
        "core",
        "mgmt",
        "pipe",
};

I will add a comment on this above.

Sorry, I don't get your response. My suggestion was to keep the resets sorted as the original order (also indicated by my above snippet).

- Mani

--
மணிவண்ணன் சதாசிவம்

Hi Manivannan,

Quoted 73 lines · Manivannan Sadhasivam

Quoted 61 lines · Anand Moon

Hi Manivannan,

Thanks for your review comments.

Quoted 11 lines · Manivannan Sadhasivam

Quoted 6 lines · Anand Moon

Refactor the reset control handling in the Rockchip PCIe driver, introducing a more robust and efficient method for assert and deassert reset controller using reset_control_bulk*() API. Using the reset_control_bulk APIs, the reset handling for the core clocks reset unit becomes much simpler.

Same comments as previous patch.

I will explain more about this.

Quoted 6 lines

Quoted 1 line

Spilt the reset controller in two groups as pre the RK3399 TRM.

*per

Also please state the TRM name and section for reference.

Yes

Quoted 36 lines

Quoted 36 lines

After power up, the software driver should de-assert the reset of PCIe PHY, then wait the PLL locked by polling the status, if PLL
has locked, then can de-assert the reset simultaneously
driver need to De-assert the reset pins simultionaly.

PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.

- replace devm_reset_control_get_exclusive() with
devm_reset_control_bulk_get_exclusive().
- replace reset_control_assert with
reset_control_bulk_assert().
- replace reset_control_deassert with
reset_control_bulk_deassert().

Signed-off-by Anand Moon <[email protected]>

---
v7: replace devm_reset_control_bulk_get_optional_exclusive()
with devm_reset_control_bulk_get_exclusive()
update the functional changes.
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: use dev_err_probe in error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning.

---
 drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
 drivers/pci/controller/pcie-rockchip.h |  26 +++--
 2 files changed, 49 insertions(+), 128 deletions(-)

drivers/pci/controller/pcie-rockchip.c +0 -0

index 2777ef0cb599..9a118e2b8cbd 100644

[...]

Quoted 7 lines

Quoted 7 lines

drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) · line 182

Quoted 3 lines

drivers/pci/controller/pcie-rockchip.c +0 -0

@@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
       * Please don't reorder the deassert sequence of the following
       * four reset pins.

I don't think my earlier comment on this addressed. Why are you changing the reset order? Why can't you have the resets in below (older) order?

Quoted 7 lines

Quoted 7 lines

Quoted 6 lines

static const char * const rockchip_pci_core_rsts[] = {
        mgmt-sticky",
        "core",
        "mgmt",
        "pipe",
};

I will add a comment on this above.

I get your point, I missed your point.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-rockchip.c?h=v6.12-rc2#n275

Actually I had these changes, but it got missed out in rebase.

Quoted 3 lines

Sorry, I don't get your response. My suggestion was to keep the resets sorted as the original order (also indicated by my above snippet).

I will go through all the suggestions and modify them accordingly.

As per the RK3399 TRM
[2] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf

17.5.2.2 Reset Application
17.5.2.2.2 System Reset (describe all the core reset feature) (name as per the dts mapping)
RESET_N: - core
MGMT_RESET_N:- mgmt
MGMT_STICKY_RESET_N:- mgmt-sticky
PIPE_RESET_N: - pipe
AXI_RESET_N - aclk
APB_RESET_N: pclk
PM_RESET_N: - pm
PCIE_PHY_RESET_N: - phy reset (used in the phy driver).

This is the reason for the split of the clk and core reset.

Further down in
17.5.8 PCIe Operation
17.5.8.1 PCIe Initialization Sequence
17.5.8.1.1 PCIe as Root Complex

6. De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously

Should I follow this order ? or the above order.

static const char * const rockchip_pci_core_rsts[] = {
        "pipe",
        "mgmt-sticky",
         "mgmt",
         "core",
};

Quoted 121 lines · Anand Moon

Hi Manivannan,

Quoted 73 lines · Manivannan Sadhasivam

Quoted 61 lines · Anand Moon

Hi Manivannan,

Thanks for your review comments.

Quoted 11 lines · Manivannan Sadhasivam

Quoted 6 lines · Anand Moon

Refactor the reset control handling in the Rockchip PCIe driver, introducing a more robust and efficient method for assert and deassert reset controller using reset_control_bulk*() API. Using the reset_control_bulk APIs, the reset handling for the core clocks reset unit becomes much simpler.

Same comments as previous patch.

I will explain more about this.

Quoted 6 lines

Quoted 1 line

Spilt the reset controller in two groups as pre the RK3399 TRM.

*per

Also please state the TRM name and section for reference.

Yes

Quoted 36 lines

Quoted 36 lines

After power up, the software driver should de-assert the reset of PCIe PHY, then wait the PLL locked by polling the status, if PLL
has locked, then can de-assert the reset simultaneously
driver need to De-assert the reset pins simultionaly.

PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.

- replace devm_reset_control_get_exclusive() with
devm_reset_control_bulk_get_exclusive().
- replace reset_control_assert with
reset_control_bulk_assert().
- replace reset_control_deassert with
reset_control_bulk_deassert().

Signed-off-by Anand Moon <[email protected]>

---
v7: replace devm_reset_control_bulk_get_optional_exclusive()
with devm_reset_control_bulk_get_exclusive()
update the functional changes.
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: use dev_err_probe in error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning.

---
 drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
 drivers/pci/controller/pcie-rockchip.h |  26 +++--
 2 files changed, 49 insertions(+), 128 deletions(-)

drivers/pci/controller/pcie-rockchip.c +0 -0

index 2777ef0cb599..9a118e2b8cbd 100644

[...]

Quoted 7 lines

Quoted 7 lines

drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) · line 182

Quoted 3 lines

drivers/pci/controller/pcie-rockchip.c +0 -0

@@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
       * Please don't reorder the deassert sequence of the following
       * four reset pins.

I don't think my earlier comment on this addressed. Why are you changing the reset order? Why can't you have the resets in below (older) order?

Quoted 7 lines

Quoted 7 lines

Quoted 6 lines

static const char * const rockchip_pci_core_rsts[] = {
        mgmt-sticky",
        "core",
        "mgmt",
        "pipe",
};

I will add a comment on this above.

I get your point, I missed your point.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-rockchip.c?h=v6.12-rc2#n275

Actually I had these changes, but it got missed out in rebase.

Quoted 3 lines

Sorry, I don't get your response. My suggestion was to keep the resets sorted as the original order (also indicated by my above snippet).

I will go through all the suggestions and modify them accordingly.

As per the RK3399 TRM
[2] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf

17.5.2.2 Reset Application
17.5.2.2.2 System Reset (describe all the core reset feature) (name as per the dts mapping)
RESET_N: - core
MGMT_RESET_N:- mgmt
MGMT_STICKY_RESET_N:- mgmt-sticky
PIPE_RESET_N: - pipe
AXI_RESET_N - aclk
APB_RESET_N: pclk
PM_RESET_N: - pm
PCIE_PHY_RESET_N: - phy reset (used in the phy driver).

This is the reason for the split of the clk and core reset.

Further down in
17.5.8 PCIe Operation
17.5.8.1 PCIe Initialization Sequence
17.5.8.1.1 PCIe as Root Complex

6. De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously

Quoted 7 lines

Should I follow this order ? or the above order.

static const char * const rockchip_pci_core_rsts[] = {
        "pipe",
        "mgmt-sticky",
         "mgmt",
         "core",
};

Ok, thanks for clarifying. I was worried about the comment in the driver that warns against changing the order. But TRM rececommends a different order :/

But since no one ever reported any issue, let's go with the existing order. If you want to follow TRM, then I'd like to get an Ack from Rockchip Engineers who knows the hardware better.

- Mani

--
மணிவண்ணன் சதாசிவம்

Refactor the rockchip_pcie_disable_clocks function to accept a struct rockchip_pcie pointer instead of a void pointer. This change improves type safety and code readability by explicitly specifying the expected data type.

Reviewed-by Manivannan Sadhasivam <[email protected]>

Signed-off-by Anand Moon <[email protected]>

---
v7: None
v6: Fix the subject, add the missing () in the function name.

v5: Fix the commit message and add r-b Manivannan.
v4: None
v3: None
v2: No

---
 drivers/pci/controller/pcie-rockchip.c | 3 +--
 drivers/pci/controller/pcie-rockchip.h | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

drivers/pci/controller/pcie-rockchip.c +1 -2

index 9a118e2b8cbd..c3147111f1a7 100644
@@ -269,9 +269,8 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
 }
 EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
 
-void rockchip_pcie_disable_clocks(void *data)
+void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip)
 {
-	struct rockchip_pcie *rockchip = data;
 
 	clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks);
 }

drivers/pci/controller/pcie-rockchip.h +1 -1

index 2761699f670b..7f0f938e9195 100644
@@ -347,7 +347,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip);
 int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip);
 void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip);
 int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip);
-void rockchip_pcie_disable_clocks(void *data);
+void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip);
 void rockchip_pcie_cfg_configuration_accesses(
 		struct rockchip_pcie *rockchip, u32 type);
 

Signature · 1 line

2.44.0

Quoted 10 lines · Anand Moon

Refactor the rockchip_pcie_disable_clocks function to accept a struct rockchip_pcie pointer instead of a void pointer. This change improves type safety and code readability by explicitly specifying the expected data type.

Reviewed-by Manivannan Sadhasivam <[email protected]>

Signed-off-by Anand Moon <[email protected]>

---
v7: None
v6: Fix the subject, add the missing () in the function name.

Did you remove it in v7? Please don't do that, it just increases the burden on reviewers.

- Mani

Hi Manivannan,

Thanks for your review comments.

Quoted 13 lines · Manivannan Sadhasivam

Quoted 10 lines · Anand Moon

Refactor the rockchip_pcie_disable_clocks function to accept a struct rockchip_pcie pointer instead of a void pointer. This change improves type safety and code readability by explicitly specifying the expected data type.

Reviewed-by Manivannan Sadhasivam <[email protected]>

Signed-off-by Anand Moon <[email protected]>

---
v7: None
v6: Fix the subject, add the missing () in the function name.

Quoted 4 lines

Did you remove it in v7? Please don't do that, it just increases the burden on reviewers.

- Mani

Earlier, it was reported that function () should be used in the function name.

Quoted 19 lines · Anand Moon

Hi Manivannan,

Thanks for your review comments.

Quoted 13 lines · Manivannan Sadhasivam

Quoted 10 lines · Anand Moon

Refactor the rockchip_pcie_disable_clocks function to accept a struct rockchip_pcie pointer instead of a void pointer. This change improves type safety and code readability by explicitly specifying the expected data type.

Reviewed-by Manivannan Sadhasivam <[email protected]>

Signed-off-by Anand Moon <[email protected]>

---
v7: None
v6: Fix the subject, add the missing () in the function name.

Quoted 5 lines

Quoted 4 lines

Did you remove it in v7? Please don't do that, it just increases the burden on reviewers.

- Mani

Earlier, it was reported that function () should be used in the function name.

Hmm. Why can't you do the same for the description also?

- Mani

--
மணிவண்ணன் சதாசிவம்