PCIe RK3399 clock and reset using new helper functions
v9 cover PCIe RK3399 clock and reset using new helper functions
Following changes are used to reduce the code and used new clk_bulk()* API d reset_control_bulk()* API helper functions.
Additional to the PCie core controller changes added some new PHY changes to help improve and clean up the code.
Made lots of silly mistakes, will try to improve in the future.
Thanks
-Anand
Previous changes.
v7:
https://lore.kernel.org/all/[email protected]/
v6:
https://lore.kernel.org/r/[email protected]/
v5:
https://lore.kernel.org/all/[email protected]/
V4:
https://lore.kernel.org/all/[email protected]/
V3:
https://lore.kernel.org/all/[email protected]/
V2:
https://lore.kernel.org/all/[email protected]/
V1:
https://lore.kernel.org/all/[email protected]/
*** BLURB HERE ***
Anand Moon (3):
PCI: rockchip: Simplify clock handling by using clk_bulk*() function
PCI: rockchip: Simplify reset control handling by using
reset_control_bulk*() function
PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function
signature
drivers/pci/controller/pcie-rockchip.c | 222 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 35 ++-- 2 files changed, 60 insertions(+), 197 deletions(-)
base-commit: 2f87d0916ce0d2925cedbc9e8f5d6291ba2ac7b2
Signature · 1 line
2.44.0
PATCH v9 1/3 PCI: rockchip: Simplify clock handling by using clk_bulk*() function
Currently, the driver acquires clks and prepare enable/disable unprepare the clks individually thereby making the driver complex to read. But this can be simplified by using the clk_bulk*() APIs. Use devm_clk_bulk_get_all() API to acquire all the clks and use clk_bulk_prepare_enable() to prepare enable clks
and clk_bulk_disable_unprepare() APIs disable unprepare them in bulk.
---
v9: Re write the commmit message.
v8: Improve the description of the code changes in commit messagee.
Add Rb: Manivannan
v7: Update the functional change in commmit message.
v6: None.
v5: switch to use use devm_clk_bulk_get_all()? gets rid of hardcoding the
clock names in driver.
v4: use dev_err_probe for error patch.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot.
--- drivers/pci/controller/pcie-rockchip.c | 65 +++----------------------- drivers/pci/controller/pcie-rockchip.h | 7 ++- 2 files changed, 10 insertions(+), 62 deletions(-)
drivers/pci/controller/pcie-rockchip.c +7 -58
@@ -127,29 +127,9 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) "failed to get ep GPIO\n"); } - rockchip->aclk_pcie =devm_clk_get (dev,"aclk" ); -if (IS_ERR (rockchip->aclk_pcie)) { -dev_err (dev,"aclk clock not found\n" ); -return PTR_ERR (rockchip->aclk_pcie); - } - - rockchip->aclk_perf_pcie =devm_clk_get (dev,"aclk-perf" ); -if (IS_ERR (rockchip->aclk_perf_pcie)) { -dev_err (dev,"aclk_perf clock not found\n" ); -return PTR_ERR (rockchip->aclk_perf_pcie); - } - - rockchip->hclk_pcie =devm_clk_get (dev,"hclk" ); -if (IS_ERR (rockchip->hclk_pcie)) { -dev_err (dev,"hclk clock not found\n" ); -return PTR_ERR (rockchip->hclk_pcie); - } - - rockchip->clk_pcie_pm =devm_clk_get (dev,"pm" ); -if (IS_ERR (rockchip->clk_pcie_pm)) { -dev_err (dev,"pm clock not found\n" ); -return PTR_ERR (rockchip->clk_pcie_pm); - } + rockchip->num_clks =devm_clk_bulk_get_all (dev, &rockchip->clks); +if (rockchip->num_clks <0 ) +return dev_err_probe (dev, err,"failed to get clocks\n" );return 0 ; }
@@ -372,39 +352,11 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)struct device *dev = rockchip->dev;int err; - err =clk_prepare_enable (rockchip->aclk_pcie); -if (err) { -dev_err (dev,"unable to enable aclk_pcie clock\n" ); -return err; - } - - err =clk_prepare_enable (rockchip->aclk_perf_pcie); -if (err) { -dev_err (dev,"unable to enable aclk_perf_pcie clock\n" ); - goto err_aclk_perf_pcie; - } - - err =clk_prepare_enable (rockchip->hclk_pcie); -if (err) { -dev_err (dev,"unable to enable hclk_pcie clock\n" ); - goto err_hclk_pcie; - } - - err =clk_prepare_enable (rockchip->clk_pcie_pm); -if (err) { -dev_err (dev,"unable to enable clk_pcie_pm clock\n" ); - goto err_clk_pcie_pm; - } + err =clk_bulk_prepare_enable (rockchip->num_clks, rockchip->clks); +if (err) +return dev_err_probe (dev, err,"failed to enable clocks\n" );return 0 ; - -err_clk_pcie_pm: -clk_disable_unprepare (rockchip->hclk_pcie); -err_hclk_pcie: -clk_disable_unprepare (rockchip->aclk_perf_pcie); -err_aclk_perf_pcie: -clk_disable_unprepare (rockchip->aclk_pcie); -return err; }EXPORT_SYMBOL_GPL (rockchip_pcie_enable_clocks);
@@ -412,10 +364,7 @@ void rockchip_pcie_disable_clocks(void *data) {struct rockchip_pcie *rockchip = data; -clk_disable_unprepare (rockchip->clk_pcie_pm); -clk_disable_unprepare (rockchip->hclk_pcie); -clk_disable_unprepare (rockchip->aclk_perf_pcie); -clk_disable_unprepare (rockchip->aclk_pcie); +clk_bulk_disable_unprepare (rockchip->num_clks, rockchip->clks); }EXPORT_SYMBOL_GPL (rockchip_pcie_disable_clocks);
drivers/pci/controller/pcie-rockchip.h +3 -4
@@ -11,6 +11,7 @@#ifndef _PCIE_ROCKCHIP_H#define _PCIE_ROCKCHIP_H +#include <linux/clk.h> #include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci-ecam.h>
@@ -299,10 +300,8 @@ struct rockchip_pcie {struct reset_control *pm_rst;struct reset_control *aclk_rst;struct reset_control *pclk_rst; -struct clk *aclk_pcie; -struct clk *aclk_perf_pcie; -struct clk *hclk_pcie; -struct clk *clk_pcie_pm; +struct clk_bulk_data *clks; +int num_clks;struct regulator *vpcie12v;/* 12V power supply */ struct regulator *vpcie3v3;/* 3.3V power supply */ struct regulator *vpcie1v8;/* 1.8V power supply */
Signature · 1 line
2.44.0
PATCH v9 2/3 PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function
In reply to Anand MoonCurrently, the driver acquires and asserts/deasserts the resets individually thereby making the driver complex to read. But this can be simplified by using the reset_control_bulk APIs. Use devm_reset_control_bulk_get_exclusive() API to acquire all the resets and use reset_control_bulk_{assert/deassert}() APIs to assert/deassert them in bulk.
Following the recommendations in 'Rockchip RK3399 TRM v1.3 Part2':
1. Split the reset controls into two groups as per section '17.5.8.1.1 PCIe as Root Complex'.
2. Deassert the 'Pipe, MGMT Sticky, MGMT, Core' resets in groups as per section '17.5.8.1.1 PCIe as Root Complex'. This is accomplished using the reset_control_bulk APIs.
---
v9: Improved the commit message and try to fix few review comments.
v8: I tried to address reviews and comments from Mani.
Follow the sequence of De-assert as per the driver code. Drop the comment in the driver.
Improve the commit message with the description of the TMP section. Improve the reason for the core functional changes in the commit description.
Improve the error handling messages of the code.
v7: replace devm_reset_control_bulk_get_optional_exclusive()
with devm_reset_control_bulk_get_exclusive()
update the functional changes.
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: use dev_err_probe in error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning.
--- drivers/pci/controller/pcie-rockchip.c | 154 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 26 +++-- 2 files changed, 48 insertions(+), 132 deletions(-)
drivers/pci/controller/pcie-rockchip.c +29 -125
@@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)struct platform_device *pdev =to_platform_device (dev);struct device_node *node = dev->of_node;struct resource *regs; -int err; +int err, i;if (rockchip->is_rc) { regs = platform_get_resource_byname(pdev,
@@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)if (rockchip->link_gen <0 || rockchip->link_gen >2 ) rockchip->link_gen =2 ; - rockchip->core_rst =devm_reset_control_get_exclusive (dev,"core" ); -if (IS_ERR (rockchip->core_rst)) { -if (PTR_ERR (rockchip->core_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing core reset property in node\n" ); -return PTR_ERR (rockchip->core_rst); - } - - rockchip->mgmt_rst =devm_reset_control_get_exclusive (dev,"mgmt" ); -if (IS_ERR (rockchip->mgmt_rst)) { -if (PTR_ERR (rockchip->mgmt_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing mgmt reset property in node\n" ); -return PTR_ERR (rockchip->mgmt_rst); - } - - rockchip->mgmt_sticky_rst =devm_reset_control_get_exclusive (dev, -"mgmt-sticky" ); -if (IS_ERR (rockchip->mgmt_sticky_rst)) { -if (PTR_ERR (rockchip->mgmt_sticky_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing mgmt-sticky reset property in node\n" ); -return PTR_ERR (rockchip->mgmt_sticky_rst); - } - - rockchip->pipe_rst =devm_reset_control_get_exclusive (dev,"pipe" ); -if (IS_ERR (rockchip->pipe_rst)) { -if (PTR_ERR (rockchip->pipe_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pipe reset property in node\n" ); -return PTR_ERR (rockchip->pipe_rst); - } +for (i =0 ; i <ROCKCHIP_NUM_PM_RSTS ; i++) + rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; - rockchip->pm_rst =devm_reset_control_get_exclusive (dev,"pm" ); -if (IS_ERR (rockchip->pm_rst)) { -if (PTR_ERR (rockchip->pm_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pm reset property in node\n" ); -return PTR_ERR (rockchip->pm_rst); - } + err =devm_reset_control_bulk_get_exclusive (dev, +ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts); +if (err) +return dev_err_probe (dev, err,"Cannot get the PM reset\n" ); - rockchip->pclk_rst =devm_reset_control_get_exclusive (dev,"pclk" ); -if (IS_ERR (rockchip->pclk_rst)) { -if (PTR_ERR (rockchip->pclk_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pclk reset property in node\n" ); -return PTR_ERR (rockchip->pclk_rst); - } +for (i =0 ; i <ROCKCHIP_NUM_CORE_RSTS ; i++) + rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i]; - rockchip->aclk_rst =devm_reset_control_get_exclusive (dev,"aclk" ); -if (IS_ERR (rockchip->aclk_rst)) { -if (PTR_ERR (rockchip->aclk_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing aclk reset property in node\n" ); -return PTR_ERR (rockchip->aclk_rst); - } + err =devm_reset_control_bulk_get_exclusive (dev, +ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts); +if (err) +return dev_err_probe (dev, err,"Cannot get the CORE resets\n" );if (rockchip->is_rc) { rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",
@@ -147,23 +115,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)int err, i;u32 regs; - err =reset_control_assert (rockchip->aclk_rst); -if (err) { -dev_err (dev,"assert aclk_rst err %d\n" , err); -return err; - } - - err =reset_control_assert (rockchip->pclk_rst); -if (err) { -dev_err (dev,"assert pclk_rst err %d\n" , err); -return err; - } - - err =reset_control_assert (rockchip->pm_rst); -if (err) { -dev_err (dev,"assert pm_rst err %d\n" , err); -return err; - } + err =reset_control_bulk_assert (ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts); +if (err) +return dev_err_probe (dev, err,"Couldn't assert PM resets\n" );for (i =0 ; i <MAX_LANE_NUM ; i++) { err =phy_init (rockchip->phys[i]);
@@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) } } - err =reset_control_assert (rockchip->core_rst); -if (err) { -dev_err (dev,"assert core_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->mgmt_rst); -if (err) { -dev_err (dev,"assert mgmt_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->mgmt_sticky_rst); -if (err) { -dev_err (dev,"assert mgmt_sticky_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->pipe_rst); -if (err) { -dev_err (dev,"assert pipe_rst err %d\n" , err); - goto err_exit_phy; - } + err =reset_control_bulk_assert (ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts); +if (err) +return dev_err_probe (dev, err,"Couldn't assert Core resets\n" );udelay (10 ); - err =reset_control_deassert (rockchip->pm_rst); -if (err) { -dev_err (dev,"deassert pm_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_deassert (rockchip->aclk_rst); + err =reset_control_bulk_deassert (ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts);if (err) { -dev_err (dev,"deassert aclk_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_deassert (rockchip->pclk_rst); -if (err) { -dev_err (dev,"deassert pclk_rst err %d\n" , err); +dev_err (dev,"Couldn't deassert PM resets %d\n" , err); goto err_exit_phy; }
@@ -252,31 +177,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) goto err_power_off_phy; } -/* -* Please don't reorder the deassert sequence of the following -* four reset pins. -*/ - err =reset_control_deassert (rockchip->mgmt_sticky_rst); -if (err) { -dev_err (dev,"deassert mgmt_sticky_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->core_rst); -if (err) { -dev_err (dev,"deassert core_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->mgmt_rst); -if (err) { -dev_err (dev,"deassert mgmt_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->pipe_rst); + err =reset_control_bulk_deassert (ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts);if (err) { -dev_err (dev,"deassert pipe_rst err %d\n" , err); +dev_err (dev,"Couldn't deassert CORE %d\n" , err); goto err_power_off_phy; }
drivers/pci/controller/pcie-rockchip.h +19 -7
@@ -15,6 +15,7 @@#include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci-ecam.h> +#include <linux/reset.h> /* * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
@@ -288,18 +289,29 @@ (((c) << ((b) *8 +5 )) & \ ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) +#define ROCKCHIP_NUM_PM_RSTS ARRAY_SIZE(rockchip_pci_pm_rsts) +#define ROCKCHIP_NUM_CORE_RSTS ARRAY_SIZE(rockchip_pci_core_rsts) + +static const char *const rockchip_pci_pm_rsts[] = { +"pm" , +"pclk" , +"aclk" , +}; + +static const char *const rockchip_pci_core_rsts[] = { +"mgmt-sticky" , +"core" , +"mgmt" , +"pipe" , +}; +struct rockchip_pcie {void __iomem *reg_base;/* DT axi-base */ void __iomem *apb_base;/* DT apb-base */ bool legacy_phy;struct phy *phys[MAX_LANE_NUM ]; -struct reset_control *core_rst; -struct reset_control *mgmt_rst; -struct reset_control *mgmt_sticky_rst; -struct reset_control *pipe_rst; -struct reset_control *pm_rst; -struct reset_control *aclk_rst; -struct reset_control *pclk_rst; +struct reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS ]; +struct reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS ];struct clk_bulk_data *clks;int num_clks;struct regulator *vpcie12v;/* 12V power supply */
Signature · 1 line
2.44.0
Re: [PATCH v9 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function
Quoted 12 lines · Anand Moon
Currently, the driver acquires and asserts/deasserts the resets individually thereby making the driver complex to read. But this can be simplified by using the
reset_control_bulkAPIs. Usedevm_reset_control_bulk_get_exclusive()API to acquire all the resets and use reset_control_bulk_{assert/deassert}() APIs to assert/deassert them in bulk.Following the recommendations in 'Rockchip RK3399 TRM v1.3 Part2':
1. Split the reset controls into two groups as per section '17.5.8.1.1 PCIe as Root Complex'.
Quoted 7 lines
2. Deassert the 'Pipe, MGMT Sticky, MGMT, Core' resets in groups as per section '17.5.8.1.1 PCIe as Root Complex'. This is accomplished using the
reset_control_bulkAPIs.Signed-off-by Anand Moon <[email protected]>---
v9: Improved the commit message and try to fix few review comments.
You haven't fixed all of them... Please take a look at all of my comments.
- Mani
Quoted 276 lines
v8: I tried to address reviews and comments from Mani.
Follow the sequence of De-assert as per the driver code. Drop the comment in the driver.
Improve the commit message with the description of the TMP section. Improve the reason for the core functional changes in the commit description.
Improve the error handling messages of the code.
v7: replacedevm_reset_control_bulk_get_optional_exclusive()
withdevm_reset_control_bulk_get_exclusive()
update the functional changes.
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: usedev_err_probein error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning.--- drivers/pci/controller/pcie-rockchip.c | 154 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 26 +++-- 2 files changed, 48 insertions(+), 132 deletions(-)drivers/pci/controller/pcie-rockchip.c +29
-125@@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)struct platform_device *pdev =to_platform_device (dev);struct device_node *node = dev->of_node;struct resource *regs; -int err; +int err, i;if (rockchip->is_rc) { regs = platform_get_resource_byname(pdev,@@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)if (rockchip->link_gen <0 || rockchip->link_gen >2 ) rockchip->link_gen =2 ; - rockchip->core_rst =devm_reset_control_get_exclusive (dev,"core" ); -if (IS_ERR (rockchip->core_rst)) { -if (PTR_ERR (rockchip->core_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing core reset property in node\n" ); -return PTR_ERR (rockchip->core_rst); - } - - rockchip->mgmt_rst =devm_reset_control_get_exclusive (dev,"mgmt" ); -if (IS_ERR (rockchip->mgmt_rst)) { -if (PTR_ERR (rockchip->mgmt_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing mgmt reset property in node\n" ); -return PTR_ERR (rockchip->mgmt_rst); - } - - rockchip->mgmt_sticky_rst =devm_reset_control_get_exclusive (dev, -"mgmt-sticky" ); -if (IS_ERR (rockchip->mgmt_sticky_rst)) { -if (PTR_ERR (rockchip->mgmt_sticky_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing mgmt-sticky reset property in node\n" ); -return PTR_ERR (rockchip->mgmt_sticky_rst); - } - - rockchip->pipe_rst =devm_reset_control_get_exclusive (dev,"pipe" ); -if (IS_ERR (rockchip->pipe_rst)) { -if (PTR_ERR (rockchip->pipe_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pipe reset property in node\n" ); -return PTR_ERR (rockchip->pipe_rst); - } +for (i =0 ; i <ROCKCHIP_NUM_PM_RSTS ; i++) + rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; - rockchip->pm_rst =devm_reset_control_get_exclusive (dev,"pm" ); -if (IS_ERR (rockchip->pm_rst)) { -if (PTR_ERR (rockchip->pm_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pm reset property in node\n" ); -return PTR_ERR (rockchip->pm_rst); - } + err =devm_reset_control_bulk_get_exclusive (dev, +ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts); +if (err) +return dev_err_probe (dev, err,"Cannot get the PM reset\n" ); - rockchip->pclk_rst =devm_reset_control_get_exclusive (dev,"pclk" ); -if (IS_ERR (rockchip->pclk_rst)) { -if (PTR_ERR (rockchip->pclk_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pclk reset property in node\n" ); -return PTR_ERR (rockchip->pclk_rst); - } +for (i =0 ; i <ROCKCHIP_NUM_CORE_RSTS ; i++) + rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i]; - rockchip->aclk_rst =devm_reset_control_get_exclusive (dev,"aclk" ); -if (IS_ERR (rockchip->aclk_rst)) { -if (PTR_ERR (rockchip->aclk_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing aclk reset property in node\n" ); -return PTR_ERR (rockchip->aclk_rst); - } + err =devm_reset_control_bulk_get_exclusive (dev, +ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts); +if (err) +return dev_err_probe (dev, err,"Cannot get the CORE resets\n" );if (rockchip->is_rc) { rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",@@ -147,23 +115,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)int err, i;u32 regs; - err =reset_control_assert (rockchip->aclk_rst); -if (err) { -dev_err (dev,"assert aclk_rst err %d\n" , err); -return err; - } - - err =reset_control_assert (rockchip->pclk_rst); -if (err) { -dev_err (dev,"assert pclk_rst err %d\n" , err); -return err; - } - - err =reset_control_assert (rockchip->pm_rst); -if (err) { -dev_err (dev,"assert pm_rst err %d\n" , err); -return err; - } + err =reset_control_bulk_assert (ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts); +if (err) +return dev_err_probe (dev, err,"Couldn't assert PM resets\n" );for (i =0 ; i <MAX_LANE_NUM ; i++) { err =phy_init (rockchip->phys[i]);@@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) } } - err =reset_control_assert (rockchip->core_rst); -if (err) { -dev_err (dev,"assert core_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->mgmt_rst); -if (err) { -dev_err (dev,"assert mgmt_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->mgmt_sticky_rst); -if (err) { -dev_err (dev,"assert mgmt_sticky_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->pipe_rst); -if (err) { -dev_err (dev,"assert pipe_rst err %d\n" , err); - goto err_exit_phy; - } + err =reset_control_bulk_assert (ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts); +if (err) +return dev_err_probe (dev, err,"Couldn't assert Core resets\n" );udelay (10 ); - err =reset_control_deassert (rockchip->pm_rst); -if (err) { -dev_err (dev,"deassert pm_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_deassert (rockchip->aclk_rst); + err =reset_control_bulk_deassert (ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts);if (err) { -dev_err (dev,"deassert aclk_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_deassert (rockchip->pclk_rst); -if (err) { -dev_err (dev,"deassert pclk_rst err %d\n" , err); +dev_err (dev,"Couldn't deassert PM resets %d\n" , err); goto err_exit_phy; }@@ -252,31 +177,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) goto err_power_off_phy; } -/* -* Please don't reorder the deassert sequence of the following -* four reset pins. -*/ - err =reset_control_deassert (rockchip->mgmt_sticky_rst); -if (err) { -dev_err (dev,"deassert mgmt_sticky_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->core_rst); -if (err) { -dev_err (dev,"deassert core_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->mgmt_rst); -if (err) { -dev_err (dev,"deassert mgmt_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->pipe_rst); + err =reset_control_bulk_deassert (ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts);if (err) { -dev_err (dev,"deassert pipe_rst err %d\n" , err); +dev_err (dev,"Couldn't deassert CORE %d\n" , err); goto err_power_off_phy; }drivers/pci/controller/pcie-rockchip.h +19
-7@@ -15,6 +15,7 @@#include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci-ecam.h> +#include <linux/reset.h> /* * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16 @@ -288,18 +289,29 @@ (((c) << ((b) *8 +5 )) & \ ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) +#define ROCKCHIP_NUM_PM_RSTS ARRAY_SIZE(rockchip_pci_pm_rsts) +#define ROCKCHIP_NUM_CORE_RSTS ARRAY_SIZE(rockchip_pci_core_rsts) + +static const char *const rockchip_pci_pm_rsts[] = { +"pm" , +"pclk" , +"aclk" , +}; + +static const char *const rockchip_pci_core_rsts[] = { +"mgmt-sticky" , +"core" , +"mgmt" , +"pipe" , +}; +struct rockchip_pcie {void __iomem *reg_base;/* DT axi-base */ void __iomem *apb_base;/* DT apb-base */ bool legacy_phy;struct phy *phys[MAX_LANE_NUM ]; -struct reset_control *core_rst; -struct reset_control *mgmt_rst; -struct reset_control *mgmt_sticky_rst; -struct reset_control *pipe_rst; -struct reset_control *pm_rst; -struct reset_control *aclk_rst; -struct reset_control *pclk_rst; +struct reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS ]; +struct reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS ];struct clk_bulk_data *clks;int num_clks;struct regulator *vpcie12v;/* 12V power supply */ Signature · 1 line
2.44.0
Signature · 1 line
மணிவண்ணன் சதாசிவம்
Re: [PATCH v9 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function
Hi Manivannan,
Quoted 18 lines · Manivannan Sadhasivam
Quoted 16 lines · Anand Moon
Currently, the driver acquires and asserts/deasserts the resets individually thereby making the driver complex to read. But this can be simplified by using the
reset_control_bulkAPIs. Usedevm_reset_control_bulk_get_exclusive()API to acquire all the resets and use reset_control_bulk_{assert/deassert}() APIs to assert/deassert them in bulk.Following the recommendations in 'Rockchip RK3399 TRM v1.3 Part2':
1. Split the reset controls into two groups as per section '17.5.8.1.1 PCIe as Root Complex'.
2. Deassert the 'Pipe, MGMT Sticky, MGMT, Core' resets in groups as per section '17.5.8.1.1 PCIe as Root Complex'. This is accomplished using the
reset_control_bulkAPIs.
Quoted 5 lines
Quoted 3 lines
Signed-off-by Anand Moon <[email protected]>---
v9: Improved the commit message and try to fix few review comments.You haven't fixed all of them... Please take a look at all of my comments.
It is becoming a nightmare for me, my confidence is a the lowest. Can you fix this while applying or I will resend it with the fix?
Quoted 3 lines
- Mani
Thanks
-Anand
Quoted 213 lines
Quoted 213 lines
v8: I tried to address reviews and comments from Mani.
Follow the sequence of De-assert as per the driver code. Drop the comment in the driver.
Improve the commit message with the description of the TMP section. Improve the reason for the core functional changes in the commit description.
Improve the error handling messages of the code.
v7: replacedevm_reset_control_bulk_get_optional_exclusive()
withdevm_reset_control_bulk_get_exclusive()
update the functional changes.
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: usedev_err_probein error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning.--- drivers/pci/controller/pcie-rockchip.c | 154 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 26 +++-- 2 files changed, 48 insertions(+), 132 deletions(-)drivers/pci/controller/pcie-rockchip.c +26
-121@@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)struct platform_device *pdev =to_platform_device (dev);struct device_node *node = dev->of_node;struct resource *regs; -int err; +int err, i;if (rockchip->is_rc) { regs = platform_get_resource_byname(pdev,@@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)if (rockchip->link_gen <0 || rockchip->link_gen >2 ) rockchip->link_gen =2 ; - rockchip->core_rst =devm_reset_control_get_exclusive (dev,"core" ); -if (IS_ERR (rockchip->core_rst)) { -if (PTR_ERR (rockchip->core_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing core reset property in node\n" ); -return PTR_ERR (rockchip->core_rst); - } - - rockchip->mgmt_rst =devm_reset_control_get_exclusive (dev,"mgmt" ); -if (IS_ERR (rockchip->mgmt_rst)) { -if (PTR_ERR (rockchip->mgmt_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing mgmt reset property in node\n" ); -return PTR_ERR (rockchip->mgmt_rst); - } - - rockchip->mgmt_sticky_rst =devm_reset_control_get_exclusive (dev, -"mgmt-sticky" ); -if (IS_ERR (rockchip->mgmt_sticky_rst)) { -if (PTR_ERR (rockchip->mgmt_sticky_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing mgmt-sticky reset property in node\n" ); -return PTR_ERR (rockchip->mgmt_sticky_rst); - } - - rockchip->pipe_rst =devm_reset_control_get_exclusive (dev,"pipe" ); -if (IS_ERR (rockchip->pipe_rst)) { -if (PTR_ERR (rockchip->pipe_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pipe reset property in node\n" ); -return PTR_ERR (rockchip->pipe_rst); - } +for (i =0 ; i <ROCKCHIP_NUM_PM_RSTS ; i++) + rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; - rockchip->pm_rst =devm_reset_control_get_exclusive (dev,"pm" ); -if (IS_ERR (rockchip->pm_rst)) { -if (PTR_ERR (rockchip->pm_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pm reset property in node\n" ); -return PTR_ERR (rockchip->pm_rst); - } + err =devm_reset_control_bulk_get_exclusive (dev, +ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts); +if (err) +return dev_err_probe (dev, err,"Cannot get the PM reset\n" ); - rockchip->pclk_rst =devm_reset_control_get_exclusive (dev,"pclk" ); -if (IS_ERR (rockchip->pclk_rst)) { -if (PTR_ERR (rockchip->pclk_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pclk reset property in node\n" ); -return PTR_ERR (rockchip->pclk_rst); - } +for (i =0 ; i <ROCKCHIP_NUM_CORE_RSTS ; i++) + rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i]; - rockchip->aclk_rst =devm_reset_control_get_exclusive (dev,"aclk" ); -if (IS_ERR (rockchip->aclk_rst)) { -if (PTR_ERR (rockchip->aclk_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing aclk reset property in node\n" ); -return PTR_ERR (rockchip->aclk_rst); - } + err =devm_reset_control_bulk_get_exclusive (dev, +ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts); +if (err) +return dev_err_probe (dev, err,"Cannot get the CORE resets\n" );if (rockchip->is_rc) { rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",@@ -147,23 +115,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)int err, i;u32 regs; - err =reset_control_assert (rockchip->aclk_rst); -if (err) { -dev_err (dev,"assert aclk_rst err %d\n" , err); -return err; - } - - err =reset_control_assert (rockchip->pclk_rst); -if (err) { -dev_err (dev,"assert pclk_rst err %d\n" , err); -return err; - } - - err =reset_control_assert (rockchip->pm_rst); -if (err) { -dev_err (dev,"assert pm_rst err %d\n" , err); -return err; - } + err =reset_control_bulk_assert (ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts); +if (err) +return dev_err_probe (dev, err,"Couldn't assert PM resets\n" );for (i =0 ; i <MAX_LANE_NUM ; i++) { err =phy_init (rockchip->phys[i]);@@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) } } - err =reset_control_assert (rockchip->core_rst); -if (err) { -dev_err (dev,"assert core_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->mgmt_rst); -if (err) { -dev_err (dev,"assert mgmt_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->mgmt_sticky_rst); -if (err) { -dev_err (dev,"assert mgmt_sticky_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->pipe_rst); -if (err) { -dev_err (dev,"assert pipe_rst err %d\n" , err); - goto err_exit_phy; - } + err =reset_control_bulk_assert (ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts); +if (err) +return dev_err_probe (dev, err,"Couldn't assert Core resets\n" );udelay (10 ); - err =reset_control_deassert (rockchip->pm_rst); -if (err) { -dev_err (dev,"deassert pm_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_deassert (rockchip->aclk_rst); + err =reset_control_bulk_deassert (ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts);if (err) { -dev_err (dev,"deassert aclk_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_deassert (rockchip->pclk_rst); -if (err) { -dev_err (dev,"deassert pclk_rst err %d\n" , err); +dev_err (dev,"Couldn't deassert PM resets %d\n" , err); goto err_exit_phy; }@@ -252,31 +177,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) goto err_power_off_phy; } -/* -* Please don't reorder the deassert sequence of the following -* four reset pins. -*/ - err =reset_control_deassert (rockchip->mgmt_sticky_rst); -if (err) { -dev_err (dev,"deassert mgmt_sticky_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->core_rst); -if (err) { -dev_err (dev,"deassert core_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->mgmt_rst); -if (err) { -dev_err (dev,"deassert mgmt_rst err %d\n" , err); - goto err_power_off_phy;
Quoted 8 lines
drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) · line 183
Quoted 8 lines
drivers/pci/controller/pcie-rockchip.c +3
-4- } - - err =reset_control_deassert (rockchip->pipe_rst); + err =reset_control_bulk_deassert (ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts);if (err) { -dev_err (dev,"deassert pipe_rst err %d\n" , err); +dev_err (dev,"Couldn't deassert CORE %d\n" , err);
ok, it shipped my review process.
Quoted 58 lines
Quoted 53 lines
drivers/pci/controller/pcie-rockchip.c +0
-0goto err_power_off_phy; }drivers/pci/controller/pcie-rockchip.h +19
-8@@ -15,6 +15,7 @@#include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci-ecam.h> +#include <linux/reset.h> /* * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16 @@ -288,18 +289,29 @@ (((c) << ((b) *8 +5 )) & \ ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) +#define ROCKCHIP_NUM_PM_RSTS ARRAY_SIZE(rockchip_pci_pm_rsts) +#define ROCKCHIP_NUM_CORE_RSTS ARRAY_SIZE(rockchip_pci_core_rsts) + +static const char *const rockchip_pci_pm_rsts[] = { +"pm" , +"pclk" , +"aclk" , +}; + +static const char *const rockchip_pci_core_rsts[] = { +"mgmt-sticky" , +"core" , +"mgmt" , +"pipe" , +}; +struct rockchip_pcie {void __iomem *reg_base;/* DT axi-base */ void __iomem *apb_base;/* DT apb-base */ bool legacy_phy;struct phy *phys[MAX_LANE_NUM ]; -struct reset_control *core_rst; -struct reset_control *mgmt_rst; -struct reset_control *mgmt_sticky_rst; -struct reset_control *pipe_rst; -struct reset_control *pm_rst; -struct reset_control *aclk_rst; -struct reset_control *pclk_rst; +struct reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS ]; +struct reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS ];struct clk_bulk_data *clks;int num_clks;struct regulator *vpcie12v;/* 12V power supply */ --Quoted 2 lines
2.44.0
--
மணிவண்ணன் சதாசிவம்
Re: [PATCH v9 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function
Quoted 22 lines · Anand Moon
Hi Manivannan,
Quoted 18 lines · Manivannan Sadhasivam
Quoted 16 lines · Anand Moon
Currently, the driver acquires and asserts/deasserts the resets individually thereby making the driver complex to read. But this can be simplified by using the
reset_control_bulkAPIs. Usedevm_reset_control_bulk_get_exclusive()API to acquire all the resets and use reset_control_bulk_{assert/deassert}() APIs to assert/deassert them in bulk.Following the recommendations in 'Rockchip RK3399 TRM v1.3 Part2':
1. Split the reset controls into two groups as per section '17.5.8.1.1 PCIe as Root Complex'.
2. Deassert the 'Pipe, MGMT Sticky, MGMT, Core' resets in groups as per section '17.5.8.1.1 PCIe as Root Complex'. This is accomplished using the
reset_control_bulkAPIs.
Quoted 7 lines
Quoted 5 lines
Quoted 3 lines
Signed-off-by Anand Moon <[email protected]>---
v9: Improved the commit message and try to fix few review comments.You haven't fixed all of them... Please take a look at all of my comments.
It is becoming a nightmare for me, my confidence is a the lowest.
Me too. It makes me go crazy if the trivial comments are not addressed in multiple revisions and it results in waste of time for both of us.
Quoted 1 line
Can you fix this while applying or I will resend it with the fix?
I don't merge the dwc patches, so I cannot do that. But what's preventing you from addressing those comments. You cannot put the burden on the maintainers for your mistake, sorry.
- Mani
Quoted 286 lines
Quoted 3 lines
- Mani
Thanks
-AnandQuoted 213 lines
Quoted 213 lines
v8: I tried to address reviews and comments from Mani.
Follow the sequence of De-assert as per the driver code. Drop the comment in the driver.
Improve the commit message with the description of the TMP section. Improve the reason for the core functional changes in the commit description.
Improve the error handling messages of the code.
v7: replacedevm_reset_control_bulk_get_optional_exclusive()
withdevm_reset_control_bulk_get_exclusive()
update the functional changes.
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: usedev_err_probein error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning.--- drivers/pci/controller/pcie-rockchip.c | 154 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 26 +++-- 2 files changed, 48 insertions(+), 132 deletions(-)drivers/pci/controller/pcie-rockchip.c +26
-121@@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)struct platform_device *pdev =to_platform_device (dev);struct device_node *node = dev->of_node;struct resource *regs; -int err; +int err, i;if (rockchip->is_rc) { regs = platform_get_resource_byname(pdev,@@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)if (rockchip->link_gen <0 || rockchip->link_gen >2 ) rockchip->link_gen =2 ; - rockchip->core_rst =devm_reset_control_get_exclusive (dev,"core" ); -if (IS_ERR (rockchip->core_rst)) { -if (PTR_ERR (rockchip->core_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing core reset property in node\n" ); -return PTR_ERR (rockchip->core_rst); - } - - rockchip->mgmt_rst =devm_reset_control_get_exclusive (dev,"mgmt" ); -if (IS_ERR (rockchip->mgmt_rst)) { -if (PTR_ERR (rockchip->mgmt_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing mgmt reset property in node\n" ); -return PTR_ERR (rockchip->mgmt_rst); - } - - rockchip->mgmt_sticky_rst =devm_reset_control_get_exclusive (dev, -"mgmt-sticky" ); -if (IS_ERR (rockchip->mgmt_sticky_rst)) { -if (PTR_ERR (rockchip->mgmt_sticky_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing mgmt-sticky reset property in node\n" ); -return PTR_ERR (rockchip->mgmt_sticky_rst); - } - - rockchip->pipe_rst =devm_reset_control_get_exclusive (dev,"pipe" ); -if (IS_ERR (rockchip->pipe_rst)) { -if (PTR_ERR (rockchip->pipe_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pipe reset property in node\n" ); -return PTR_ERR (rockchip->pipe_rst); - } +for (i =0 ; i <ROCKCHIP_NUM_PM_RSTS ; i++) + rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; - rockchip->pm_rst =devm_reset_control_get_exclusive (dev,"pm" ); -if (IS_ERR (rockchip->pm_rst)) { -if (PTR_ERR (rockchip->pm_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pm reset property in node\n" ); -return PTR_ERR (rockchip->pm_rst); - } + err =devm_reset_control_bulk_get_exclusive (dev, +ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts); +if (err) +return dev_err_probe (dev, err,"Cannot get the PM reset\n" ); - rockchip->pclk_rst =devm_reset_control_get_exclusive (dev,"pclk" ); -if (IS_ERR (rockchip->pclk_rst)) { -if (PTR_ERR (rockchip->pclk_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pclk reset property in node\n" ); -return PTR_ERR (rockchip->pclk_rst); - } +for (i =0 ; i <ROCKCHIP_NUM_CORE_RSTS ; i++) + rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i]; - rockchip->aclk_rst =devm_reset_control_get_exclusive (dev,"aclk" ); -if (IS_ERR (rockchip->aclk_rst)) { -if (PTR_ERR (rockchip->aclk_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing aclk reset property in node\n" ); -return PTR_ERR (rockchip->aclk_rst); - } + err =devm_reset_control_bulk_get_exclusive (dev, +ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts); +if (err) +return dev_err_probe (dev, err,"Cannot get the CORE resets\n" );if (rockchip->is_rc) { rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",@@ -147,23 +115,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)int err, i;u32 regs; - err =reset_control_assert (rockchip->aclk_rst); -if (err) { -dev_err (dev,"assert aclk_rst err %d\n" , err); -return err; - } - - err =reset_control_assert (rockchip->pclk_rst); -if (err) { -dev_err (dev,"assert pclk_rst err %d\n" , err); -return err; - } - - err =reset_control_assert (rockchip->pm_rst); -if (err) { -dev_err (dev,"assert pm_rst err %d\n" , err); -return err; - } + err =reset_control_bulk_assert (ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts); +if (err) +return dev_err_probe (dev, err,"Couldn't assert PM resets\n" );for (i =0 ; i <MAX_LANE_NUM ; i++) { err =phy_init (rockchip->phys[i]);@@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) } } - err =reset_control_assert (rockchip->core_rst); -if (err) { -dev_err (dev,"assert core_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->mgmt_rst); -if (err) { -dev_err (dev,"assert mgmt_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->mgmt_sticky_rst); -if (err) { -dev_err (dev,"assert mgmt_sticky_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->pipe_rst); -if (err) { -dev_err (dev,"assert pipe_rst err %d\n" , err); - goto err_exit_phy; - } + err =reset_control_bulk_assert (ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts); +if (err) +return dev_err_probe (dev, err,"Couldn't assert Core resets\n" );udelay (10 ); - err =reset_control_deassert (rockchip->pm_rst); -if (err) { -dev_err (dev,"deassert pm_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_deassert (rockchip->aclk_rst); + err =reset_control_bulk_deassert (ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts);if (err) { -dev_err (dev,"deassert aclk_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_deassert (rockchip->pclk_rst); -if (err) { -dev_err (dev,"deassert pclk_rst err %d\n" , err); +dev_err (dev,"Couldn't deassert PM resets %d\n" , err); goto err_exit_phy; }@@ -252,31 +177,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) goto err_power_off_phy; } -/* -* Please don't reorder the deassert sequence of the following -* four reset pins. -*/ - err =reset_control_deassert (rockchip->mgmt_sticky_rst); -if (err) { -dev_err (dev,"deassert mgmt_sticky_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->core_rst); -if (err) { -dev_err (dev,"deassert core_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->mgmt_rst); -if (err) { -dev_err (dev,"deassert mgmt_rst err %d\n" , err); - goto err_power_off_phy;Quoted 8 lines
drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) · line 183
Quoted 8 lines
drivers/pci/controller/pcie-rockchip.c +3
-4- } - - err =reset_control_deassert (rockchip->pipe_rst); + err =reset_control_bulk_deassert (ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts);if (err) { -dev_err (dev,"deassert pipe_rst err %d\n" , err); +dev_err (dev,"Couldn't deassert CORE %d\n" , err);ok, it shipped my review process.
Quoted 58 lines
Quoted 53 lines
drivers/pci/controller/pcie-rockchip.c +0
-0goto err_power_off_phy; }drivers/pci/controller/pcie-rockchip.h +19
-8@@ -15,6 +15,7 @@#include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci-ecam.h> +#include <linux/reset.h> /* * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16 @@ -288,18 +289,29 @@ (((c) << ((b) *8 +5 )) & \ ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) +#define ROCKCHIP_NUM_PM_RSTS ARRAY_SIZE(rockchip_pci_pm_rsts) +#define ROCKCHIP_NUM_CORE_RSTS ARRAY_SIZE(rockchip_pci_core_rsts) + +static const char *const rockchip_pci_pm_rsts[] = { +"pm" , +"pclk" , +"aclk" , +}; + +static const char *const rockchip_pci_core_rsts[] = { +"mgmt-sticky" , +"core" , +"mgmt" , +"pipe" , +}; +struct rockchip_pcie {void __iomem *reg_base;/* DT axi-base */ void __iomem *apb_base;/* DT apb-base */ bool legacy_phy;struct phy *phys[MAX_LANE_NUM ]; -struct reset_control *core_rst; -struct reset_control *mgmt_rst; -struct reset_control *mgmt_sticky_rst; -struct reset_control *pipe_rst; -struct reset_control *pm_rst; -struct reset_control *aclk_rst; -struct reset_control *pclk_rst; +struct reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS ]; +struct reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS ];struct clk_bulk_data *clks;int num_clks;struct regulator *vpcie12v;/* 12V power supply */ --Quoted 2 lines
2.44.0
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மணிவண்ணன் சதாசிவம்
Signature · 1 line
மணிவண்ணன் சதாசிவம்
Re: [PATCH v9 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function
Hi
Quoted 28 lines · Manivannan Sadhasivam
Quoted 26 lines · Anand Moon
Hi Manivannan,
Quoted 22 lines · Manivannan Sadhasivam
Quoted 19 lines · Anand Moon
Currently, the driver acquires and asserts/deasserts the resets individually thereby making the driver complex to read. But this can be simplified by using the
reset_control_bulkAPIs. Usedevm_reset_control_bulk_get_exclusive()API to acquire all the resets and use reset_control_bulk_{assert/deassert}() APIs to assert/deassert them in bulk.Following the recommendations in 'Rockchip RK3399 TRM v1.3 Part2':
1. Split the reset controls into two groups as per section '17.5.8.1.1 PCIe as Root Complex'.
2. Deassert the 'Pipe, MGMT Sticky, MGMT, Core' resets in groups as per section '17.5.8.1.1 PCIe as Root Complex'. This is accomplished using the
reset_control_bulkAPIs.Signed-off-by Anand Moon <[email protected]>---
v9: Improved the commit message and try to fix few review comments.
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
You haven't fixed all of them... Please take a look at all of my comments.
It is becoming a nightmare for me, my confidence is a the lowest.
Me too. It makes me go crazy if the trivial comments are not addressed in multiple revisions and it results in waste of time for both of us.
I must apologize to you for my failure not being able to address this. I promise to tidy up from my end in the future.
Quoted 6 lines
Quoted 1 line
Can you fix this while applying or I will resend it with the fix?
I don't merge the dwc patches, so I cannot do that. But what's preventing you from addressing those comments. You cannot put the burden on the maintainers for your mistake, sorry.
Ok I understand this will try to send in the next version
Quoted 2 lines
- Mani
Thanks
-Anand
PATCH v9 3/3 PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function signature
In reply to Anand MoonRefactor the rockchip_pcie_disable_clocks() function to accept a struct rockchip_pcie pointer instead of a void pointer. This change improves type safety and code readability by explicitly specifying the expected data type.
---
v9: None
v8: add add the missing () in the function name.
v7: None
v6: Fix the subject, add the missing () in the function name.
v5: Fix the commit message and add r-b Manivannan.
v4: None
v3: None
v2: No
--- drivers/pci/controller/pcie-rockchip.c | 3 +-- drivers/pci/controller/pcie-rockchip.h | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-)
drivers/pci/controller/pcie-rockchip.c +1 -2
@@ -264,9 +264,8 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) }EXPORT_SYMBOL_GPL (rockchip_pcie_enable_clocks); -void rockchip_pcie_disable_clocks (void *data) +void rockchip_pcie_disable_clocks (struct rockchip_pcie *rockchip) { -struct rockchip_pcie *rockchip = data;clk_bulk_disable_unprepare (rockchip->num_clks, rockchip->clks); }
drivers/pci/controller/pcie-rockchip.h +1 -1
@@ -347,7 +347,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip);int rockchip_pcie_get_phys (struct rockchip_pcie *rockchip);void rockchip_pcie_deinit_phys (struct rockchip_pcie *rockchip);int rockchip_pcie_enable_clocks (struct rockchip_pcie *rockchip); -void rockchip_pcie_disable_clocks (void *data); +void rockchip_pcie_disable_clocks (struct rockchip_pcie *rockchip);void rockchip_pcie_cfg_configuration_accesses (struct rockchip_pcie *rockchip,u32 type);
Signature · 1 line
2.44.0