Add support for AM62L DSS
Subsystems (5)
v6 cover Add support for AM62L DSS
This adds support for DSS subsystem present in TI's AM62L SoC which supports single display pipeline with DPI output which is also routed to DSI Tx controller within the SoC.
Change Log:
V6:
- Move hw_id indexing logic to skip uninstantiated planes to internal functions dealing with relevant registers
V5:
- Use hw_id instead of index for places where it was missed so that we pick correct base address for vid region
V4:
- Update vid_info struct to keep hw_id and instantiate only for actually existing pipes
V3:
- Make generic infra to support truncated K3 DSS IP's
- Remove AM62A updates from AM62L DT binding updates
V2:
- Fix incorrect format of compatible string (comma instead of hyphen) for AM62L SoC
- Use separate register space and helper functions for AM62L due to minor differences in register offset/bit position differences for first plane
Rangediff:V5->V6:
- https://gist.github.com/devarsht/f64b00754794d22e57ac18ec09a7b019
V4->V5:
- https://gist.github.com/devarsht/a0e6aa7b1c19f47facd0058962e3c3c2
V3->V4:
- https://gist.github.com/devarsht/1e75c9e1ac0cdfc01703a0776e31e782
V2->V3:
- https://gist.github.com/devarsht/24fa8dd2986861efa431352d19ebbb41
V1->V2
- https://gist.github.com/devarsht/11d47f25ca9fea6976e6284330ddf443
Links to previous versions:
V5: https://lore.kernel.org/all/[email protected]/
V4: https://lore.kernel.org/all/[email protected]/
V3: https://lore.kernel.org/all/[email protected]/
V2: https://lore.kernel.org/all/[email protected]/
V1: https://lore.kernel.org/all/[email protected]/
Test logs:
https://gist.github.com/devarsht/09a5d64a507b7ccc096e857f122eda70
Devarsh Thakkar (3):
dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS drm/tidss: Update infrastructure to support K3 DSS cut-down versions drm/tidss: Add support for AM62L display subsystem
.../bindings/display/ti/ti,am65x-dss.yaml | 21 +- drivers/gpu/drm/tidss/tidss_crtc.c | 4 +- drivers/gpu/drm/tidss/tidss_dispc.c | 197 ++++++++++++++---- drivers/gpu/drm/tidss/tidss_dispc.h | 13 +- drivers/gpu/drm/tidss/tidss_drv.c | 1 + drivers/gpu/drm/tidss/tidss_kms.c | 2 +- drivers/gpu/drm/tidss/tidss_plane.c | 2 +- 7 files changed, 192 insertions(+), 48 deletions(-)
Signature · 1 line
2.39.1
PATCH v6 1/3 dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS
The DSS controller on TI's AM62L SoC is an update from that on TI's AM625/AM65x/AM62A7 SoC. The AM62L DSS [1] only supports a single display pipeline using a single overlay manager, single video port and a single video lite pipeline which does not support scaling.
The output of video port is routed to SoC boundary via DPI interface and the DPI signals from the video port are also routed to DSI Tx controller present within the SoC.
[1]: Section 11.7 (Display Subsystem and Peripherals)
---
V6: No change
V5: No change
V4: No change
V3:
- Remove AM62A references as suggested
- Add Reviewed-by
V2:
- Add Reviewed-by
- s/ti,am62l,dss/ti,am62l-dss
.../bindings/display/ti/ti,am65x-dss.yaml | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +20 -1
@@ -12,18 +12,25 @@ maintainers: - Tomi Valkeinen <[email protected]> description: | - The AM625 and AM65x TI Keystone Display SubSystem with two output + The AM625 and AM65x TI Keystone Display SubSystem has two output ports and two video planes. In AM65x DSS, the first video port supports 1 OLDI TX and in AM625 DSS, the first video port output is internally routed to 2 OLDI TXes. The second video port supports DPI format. The first plane is full video plane with all features and the second is a "lite plane" without scaling support. + The AM62L display subsystem has a single output port which supports DPI + format but it only supports single video "lite plane" which does not support + scaling. The output port is routed to SoC boundary via DPI interface and same + DPI signals are also routed internally to DSI Tx controller present within the + SoC. Due to clocking limitations only one of the interface i.e. either DSI or + DPI can be used at once. properties: compatible: enum: - ti,am625-dss - ti,am62a7-dss + - ti,am62l-dss - ti,am65x-dss reg:
@@ -91,6 +98,8 @@ properties: For AM625 DSS, the internal DPI output port node from video port 1. For AM62A7 DSS, the port is tied off inside the SoC. + For AM62L DSS, the DSS DPI output port node from video port 1 + or DSI Tx controller node connected to video port 1. port@1: $ref: /schemas/graph.yaml#/properties/port
@@ -123,6 +132,16 @@ allOf: ports: properties: port@0: false + - if: + properties: + compatible: + contains: + const: ti,am62l-dss + then: + properties: + ports: + properties: + port@1: false required: - compatible
Signature · 1 line
2.39.1
PATCH v6 2/3 drm/tidss: Update infrastructure to support K3 DSS cut-down versions
In reply to Devarsh ThakkarSoCs like AM62Lx support cut-down version of K3 DSS where although same register space is supported as in other K3 DSS supported SoCs such as AM65x, AM62x, AM62Ax but some of the resources such as planes and corresponding register spaces are truncated.
For e.g. AM62Lx has only single VIDL pipeline supported, so corresponding register spaces for other video pipelines need to be skipped.
To add a generic support for future SoCs where one or more video pipelines can get truncated from the parent register space, move the video plane related information to vid_info struct which will also have a field to indicate hardware index of each of the available video planes, so that driver only maps and programs those video pipes and skips the unavailable ones.
While at it, also change the num_planes field in the features structure to num_vid so that all places in code which use vid_info structure are highlighted in the code.
---
V6:
- Move hw_id indexing logic to skip uninstantiated planes to internal functions dealing with relevant registers
V5:
- Use separate variable for hw_id and add it in missing places to access correct VID pipeline bits in common registers
V4:
- Create vid_info struct only for instantiated planes
- s/num_planes/num_vids
- s/vid_lite/is_lite
- Add hw_id member in vid_info struct and remove is_present
V2->V3:
- No change (patch introduced in V3)
drivers/gpu/drm/tidss/tidss_crtc.c | 4 +- drivers/gpu/drm/tidss/tidss_dispc.c | 154 +++++++++++++++++++++------- drivers/gpu/drm/tidss/tidss_dispc.h | 11 +- drivers/gpu/drm/tidss/tidss_kms.c | 2 +- drivers/gpu/drm/tidss/tidss_plane.c | 2 +- 5 files changed, 127 insertions(+), 46 deletions(-)
drivers/gpu/drm/tidss/tidss_crtc.c +2 -2
@@ -130,7 +130,7 @@ static void tidss_crtc_position_planes(struct tidss_device *tidss, !to_tidss_crtc_state(cstate)->plane_pos_changed) return; -for (layer =0 ; layer < tidss->feat->num_planes; layer++) { +for (layer =0 ; layer < tidss->feat->num_vids ; layer++) {struct drm_plane_state *pstate;struct drm_plane *plane;bool layer_active = false;
@@ -271,7 +271,7 @@ static void tidss_crtc_atomic_disable(struct drm_crtc *crtc,* another videoport, the DSS will report sync lost issues. Disable all * the layers here as a work-around. */ -for (u32 layer =0 ; layer < tidss->feat->num_planes; layer++) +for (u32 layer =0 ; layer < tidss->feat->num_vids; layer++)dispc_ovr_enable_layer (tidss->dispc, tcrtc->hw_videoport, layer, false);
drivers/gpu/drm/tidss/tidss_dispc.c +115 -39
297 lines not on this page · raw message
drivers/gpu/drm/tidss/tidss_dispc.h +8 -3
@@ -46,6 +46,12 @@ struct dispc_features_scaling {u32 xinc_max; }; +struct dispc_vid_info { +const char *name;/* Should match dt reg names */ +u32 hw_id; +bool is_lite; +}; +struct dispc_errata {bool i2000;/* DSS Does Not Support YUV Pixel Data Formats */ };
@@ -82,9 +88,8 @@ struct dispc_features {const char *vpclk_name[TIDSS_MAX_PORTS ];/* Should match dt clk names */ const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS ];struct tidss_vp_feat vp_feat; -u32 num_planes; -const char *vid_name[TIDSS_MAX_PLANES ];/* Should match dt reg names */ -bool vid_lite[TIDSS_MAX_PLANES ]; +u32 num_vids; +struct dispc_vid_info vid_info[TIDSS_MAX_PLANES ];u32 vid_order[TIDSS_MAX_PLANES ]; };
drivers/gpu/drm/tidss/tidss_kms.c +1 -1
@@ -115,7 +115,7 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss)const struct dispc_features *feat = tidss->feat;u32 max_vps = feat->num_vps; -u32 max_planes = feat->num_planes; +u32 max_planes = feat->num_vids;struct pipe pipes[TIDSS_MAX_PORTS ];u32 num_pipes =0 ;
drivers/gpu/drm/tidss/tidss_plane.c +1 -1
@@ -200,7 +200,7 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,struct tidss_plane *tplane;enum drm_plane_type type;u32 possible_crtcs; -u32 num_planes = tidss->feat->num_planes; +u32 num_planes = tidss->feat->num_vids;u32 color_encodings = (BIT (DRM_COLOR_YCBCR_BT601 ) |BIT (DRM_COLOR_YCBCR_BT709 )); u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) |
Signature · 1 line
2.39.1
PATCH v6 3/3 drm/tidss: Add support for AM62L display subsystem
In reply to Devarsh ThakkarEnable display for AM62L DSS [1] which supports only a single display pipeline using a single overlay manager, single video port and a single video lite pipeline which does not support scaling.
The output of video port is routed to SoC boundary via DPI interface and the DPI signals from the video port are also routed to DSI Tx controller present within the SoC.
[1]: Section 11.7 (Display Subsystem and Peripherals)
---
v6:
- No change
V5:
- No change
V4:
- Rebase on top of previous patch to use vid_info structure
V3:
- Rebase on top of 0002-drm-tidss-Update-infra-to-support-DSS7-cut-down-vers.patch
- Use the generic "tidss_am65x_common_regs" as common reg space instead of creating a new one
V2:
- Add separate common reg space for AM62L
- Add separate irq enable/disable/read/clear helpers for AM62L
- Use separate helper function for setting overlay attributes
- Drop Reviewed-by: Tomi Valkeinen <[email protected]> due to additional changes made in V2.
drivers/gpu/drm/tidss/tidss_dispc.c | 41 +++++++++++++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++ drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 44 insertions(+)
drivers/gpu/drm/tidss/tidss_dispc.c +41 -0
@@ -440,6 +440,42 @@ const struct dispc_features dispc_am62a7_feats = { .vid_order = {1, 0}, }; +const struct dispc_features dispc_am62l_feats = { + .max_pclk_khz = { + [DISPC_VP_DPI ] =165000 , + }, + + .subrev =DISPC_AM62L , + + .common ="common" , + .common_regs = tidss_am65x_common_regs, + + .num_vps =1 , + .vp_name = {"vp1" }, + .ovr_name = {"ovr1" }, + .vpclk_name = {"vp1" }, + .vp_bus_type = {DISPC_VP_DPI }, + + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size =256 , + .gamma_type =TIDSS_GAMMA_8BIT , + }, + }, + + .num_vids =1 , + + .vid_info = { + { + .name ="vidl1" , + .is_lite = true, + .hw_id =1 , + } + }, + + .vid_order = {0 }, +}; +static const u16 *dispc_common_regmap; struct dss_vp_data {
@@ -951,6 +987,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc)return dispc_k2g_read_and_clear_irqstatus (dispc);case DISPC_AM625 :case DISPC_AM62A7 : +case DISPC_AM62L :case DISPC_AM65X :case DISPC_J721E :return dispc_k3_read_and_clear_irqstatus (dispc);
@@ -968,6 +1005,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)break ;case DISPC_AM625 :case DISPC_AM62A7 : +case DISPC_AM62L :case DISPC_AM65X :case DISPC_J721E :dispc_k3_set_irqenable (dispc, mask);
@@ -1464,6 +1502,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,break ;case DISPC_AM625 :case DISPC_AM62A7 : +case DISPC_AM62L :case DISPC_AM65X :dispc_am65x_ovr_set_plane (dispc, hw_plane, hw_videoport, x, y, layer);
@@ -2384,6 +2423,7 @@ static void dispc_plane_init(struct dispc_device *dispc)break ;case DISPC_AM625 :case DISPC_AM62A7 : +case DISPC_AM62L :case DISPC_AM65X :case DISPC_J721E :dispc_k3_plane_init (dispc);
@@ -2492,6 +2532,7 @@ static void dispc_vp_write_gamma_table(struct dispc_device *dispc,break ;case DISPC_AM625 :case DISPC_AM62A7 : +case DISPC_AM62L :case DISPC_AM65X :dispc_am65x_vp_write_gamma_table (dispc, hw_videoport);break ;
drivers/gpu/drm/tidss/tidss_dispc.h +2 -0
@@ -67,6 +67,7 @@ enum dispc_vp_bus_type {enum dispc_dss_subrevision {DISPC_K2G ,DISPC_AM625 , +DISPC_AM62L ,DISPC_AM62A7 ,DISPC_AM65X ,DISPC_J721E ,
@@ -96,6 +97,7 @@ struct dispc_features {extern const struct dispc_features dispc_k2g_feats;extern const struct dispc_features dispc_am625_feats;extern const struct dispc_features dispc_am62a7_feats; +extern const struct dispc_features dispc_am62l_feats;extern const struct dispc_features dispc_am65x_feats;extern const struct dispc_features dispc_j721e_feats;
drivers/gpu/drm/tidss/tidss_drv.c +1 -0
@@ -242,6 +242,7 @@ static const struct of_device_id tidss_of_table[] = { { .compatible = "ti,k2g-dss", .data = &dispc_k2g_feats, }, { .compatible = "ti,am625-dss", .data = &dispc_am625_feats, }, { .compatible = "ti,am62a7-dss", .data = &dispc_am62a7_feats, }, + { .compatible = "ti,am62l-dss", .data = &dispc_am62l_feats, }, { .compatible = "ti,am65x-dss", .data = &dispc_am65x_feats, }, { .compatible = "ti,j721e-dss", .data = &dispc_j721e_feats, }, { }
Signature · 1 line
2.39.1
Hi,
Quoted 3 lines · Devarsh Thakkar
This adds support for DSS subsystem present in TI's AM62L SoC which supports single display pipeline with DPI output which is also routed to DSI Tx controller within the SoC.
I think this looks fine. I did some quick tests, and didn't notice anything amiss. I'm still somewhat wary about the indexing we do wrt. planes, and the possibility to introduce hard-to-find bugs by using the wrong index. We can try to improve this on top.
I'll do a few more tests, and unless there are no other commets I'll push to drm-misc tomorrow.
Tomi