Add support for AM62L DSS
Subsystems (5)
v3 cover Add support for AM62L DSS
This adds support for DSS subsystem present in TI's AM62L SoC which supports single display pipeline with DPI output which is also routed to DSI Tx controller within the SoC.
Change Log:
V3:
- Make generic infra to support truncated K3 DSS IP's
- Remove AM62A updates from AM62L DT binding updates
V2:
- Fix incorrect format of compatible string (comma instead of hyphen) for AM62L SoC
- Use separate register space and helper functions for AM62L due to minor differences in register offset/bit position differences for first plane
Rangediff:V2->V3:
- https://gist.github.com/devarsht/24fa8dd2986861efa431352d19ebbb41
V1->V2
- https://gist.github.com/devarsht/11d47f25ca9fea6976e6284330ddf443
Links to previous versions:
V2: https://lore.kernel.org/all/[email protected]/
V1: https://lore.kernel.org/all/[email protected]/
Test logs:
https://gist.github.com/devarsht/16fe796b8fd3ea8abf5df8e2327d2311
Devarsh Thakkar (3):
dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS drm/tidss: Update infra to support DSS7 cut-down versions drm/tidss: Add support for AM62L display subsystem
.../bindings/display/ti/ti,am65x-dss.yaml | 21 +- drivers/gpu/drm/tidss/tidss_crtc.c | 7 +- drivers/gpu/drm/tidss/tidss_dispc.c | 185 +++++++++++++++--- drivers/gpu/drm/tidss/tidss_dispc.h | 12 +- drivers/gpu/drm/tidss/tidss_drv.c | 1 + drivers/gpu/drm/tidss/tidss_irq.c | 6 + drivers/gpu/drm/tidss/tidss_kms.c | 10 +- 7 files changed, 211 insertions(+), 31 deletions(-)
Signature · 1 line
2.39.1
PATCH v3 1/3 dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS
The DSS controller on TI's AM62L SoC is an update from that on TI's AM625/AM65x/AM62A7 SoC. The AM62L DSS [1] only supports a single display pipeline using a single overlay manager, single video port and a single video lite pipeline which does not support scaling.
The output of video port is routed to SoC boundary via DPI interface and the DPI signals from the video port are also routed to DSI Tx controller present within the SoC.
[1]: Section 11.7 (Display Subsystem and Peripherals)
---
V3:
- Remove AM62A references as suggested
- Add Reviewed-by
V2:
- Add Reviewed-by
- s/ti,am62l,dss/ti,am62l-dss
.../bindings/display/ti/ti,am65x-dss.yaml | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +20 -1
@@ -12,18 +12,25 @@ maintainers: - Tomi Valkeinen <[email protected]> description: | - The AM625 and AM65x TI Keystone Display SubSystem with two output + The AM625 and AM65x TI Keystone Display SubSystem has two output ports and two video planes. In AM65x DSS, the first video port supports 1 OLDI TX and in AM625 DSS, the first video port output is internally routed to 2 OLDI TXes. The second video port supports DPI format. The first plane is full video plane with all features and the second is a "lite plane" without scaling support. + The AM62L display subsystem has a single output port which supports DPI + format but it only supports single video "lite plane" which does not support + scaling. The output port is routed to SoC boundary via DPI interface and same + DPI signals are also routed internally to DSI Tx controller present within the + SoC. Due to clocking limitations only one of the interface i.e. either DSI or + DPI can be used at once. properties: compatible: enum: - ti,am625-dss - ti,am62a7-dss + - ti,am62l-dss - ti,am65x-dss reg:
@@ -91,6 +98,8 @@ properties: For AM625 DSS, the internal DPI output port node from video port 1. For AM62A7 DSS, the port is tied off inside the SoC. + For AM62L DSS, the DSS DPI output port node from video port 1 + or DSI Tx controller node connected to video port 1. port@1: $ref: /schemas/graph.yaml#/properties/port
@@ -123,6 +132,16 @@ allOf: ports: properties: port@0: false + - if: + properties: + compatible: + contains: + const: ti,am62l-dss + then: + properties: + ports: + properties: + port@1: false required: - compatible
Signature · 1 line
2.39.1
PATCH v3 2/3 drm/tidss: Update infrastructure to support K3 DSS cut-down versions
In reply to Devarsh ThakkarSoCs like AM62Lx support cut-down version of DSS7 where although same register space is supported as in other DSS7 supported SoCs such as AM65x, AM62x, AM62Ax but some of the resources such as planes and corresponding register spaces are truncated.
For e.g. AM62Lx has only single VIDL pipeline supported, so corresponding register spaces for other video pipelines need to be skipped.
To add a generic support for future SoCs whether one or more video pipelines can get truncated from the parent register space, move the plane related information to plane_info struct which will also have a flag to indicate whether that plane is actually supported or it is truncated. If the plane is truncated, then skip the access to corresponding register space while doing plane related operations.
---
V3: Patch is introduced
V2: Patch not present
drivers/gpu/drm/tidss/tidss_crtc.c | 7 +- drivers/gpu/drm/tidss/tidss_dispc.c | 133 +++++++++++++++++++++++----- drivers/gpu/drm/tidss/tidss_dispc.h | 9 +- drivers/gpu/drm/tidss/tidss_irq.c | 6 ++ drivers/gpu/drm/tidss/tidss_kms.c | 10 ++- 5 files changed, 135 insertions(+), 30 deletions(-)
drivers/gpu/drm/tidss/tidss_crtc.c +5 -2
@@ -130,7 +130,7 @@ static void tidss_crtc_position_planes(struct tidss_device *tidss, !to_tidss_crtc_state(cstate)->plane_pos_changed) return; -for (layer =0 ; layer < tidss->feat->num_planes; layer++) { +for (layer =0 ; layer < tidss->num_planes ; layer++) {struct drm_plane_state *pstate;struct drm_plane *plane;bool layer_active = false;
@@ -271,9 +271,12 @@ static void tidss_crtc_atomic_disable(struct drm_crtc *crtc,* another videoport, the DSS will report sync lost issues. Disable all * the layers here as a work-around. */ -for (u32 layer =0 ; layer < tidss->feat->num_planes; layer++) +for (u32 layer =0 ; layer < tidss->feat->num_planes; layer++) { +if (!tidss->feat->vid_info[layer].is_present) +continue ;dispc_ovr_enable_layer (tidss->dispc, tcrtc->hw_videoport, layer, false); + }dispc_vp_disable (tidss->dispc, tcrtc->hw_videoport);
drivers/gpu/drm/tidss/tidss_dispc.c +110 -23
243 lines not on this page · raw message
drivers/gpu/drm/tidss/tidss_dispc.h +7 -2
@@ -46,6 +46,12 @@ struct dispc_features_scaling {u32 xinc_max; }; +struct plane_info { +const char *vid_name;/* Should match dt reg names */ +bool vid_lite; +bool is_present; +}; +struct dispc_errata {bool i2000;/* DSS Does Not Support YUV Pixel Data Formats */ };
@@ -83,8 +89,7 @@ struct dispc_features {const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS ];struct tidss_vp_feat vp_feat;u32 num_planes; -const char *vid_name[TIDSS_MAX_PLANES ];/* Should match dt reg names */ -bool vid_lite[TIDSS_MAX_PLANES ]; +struct plane_info vid_info[TIDSS_MAX_PLANES ];u32 vid_order[TIDSS_MAX_PLANES ]; };
drivers/gpu/drm/tidss/tidss_irq.c +6 -0
@@ -83,6 +83,9 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg)struct drm_plane *plane = tidss->planes[i];struct tidss_plane *tplane =to_tidss_plane (plane); +if (!(tidss->feat->vid_info[i].is_present)) +continue ; +if (irqstatus &DSS_IRQ_PLANE_FIFO_UNDERFLOW (tplane->hw_plane_id))tidss_plane_error_irq (plane, irqstatus); }
@@ -122,6 +125,9 @@ int tidss_irq_install(struct drm_device *ddev, unsigned int irq) }for (unsigned int i =0 ; i < tidss->num_planes; ++i) { +if (!tidss->feat->vid_info[i].is_present) +continue ; +struct tidss_plane *tplane =to_tidss_plane (tidss->planes[i]); tidss->irq_mask |=DSS_IRQ_PLANE_FIFO_UNDERFLOW (tplane->hw_plane_id);
drivers/gpu/drm/tidss/tidss_kms.c +7 -3
@@ -191,6 +191,9 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss)u32 hw_plane_id = feat->vid_order[tidss->num_planes];int ret; +if (!feat->vid_info[hw_plane_id].is_present) +continue ; + tplane =tidss_plane_create (tidss, hw_plane_id,DRM_PLANE_TYPE_PRIMARY , crtc_mask, fourccs, fourccs_len);
@@ -220,15 +223,16 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss) }/* create overlay planes of the leftover planes */ - -while (tidss->num_planes < max_planes) { +for (i = tidss->num_planes; i < max_planes ; i++) {struct tidss_plane *tplane;u32 hw_plane_id = feat->vid_order[tidss->num_planes]; +if (!feat->vid_info[hw_plane_id].is_present) +continue ; + tplane =tidss_plane_create (tidss, hw_plane_id,DRM_PLANE_TYPE_OVERLAY , crtc_mask, fourccs, fourccs_len); -if (IS_ERR (tplane)) {dev_err (tidss->dev,"plane create failed\n" );return PTR_ERR (tplane);
Signature · 1 line
2.39.1
PATCH v3 3/3 drm/tidss: Add support for AM62L display subsystem
In reply to Devarsh ThakkarEnable display for AM62L DSS [1] which supports only a single display pipeline using a single overlay manager, single video port and a single video lite pipeline which does not support scaling.
The output of video port is routed to SoC boundary via DPI interface and the DPI signals from the video port are also routed to DSI Tx controller present within the SoC.
[1]: Section 11.7 (Display Subsystem and Peripherals)
---
V3:
- Rebase on top of 0002-drm-tidss-Update-infra-to-support-DSS7-cut-down-vers.patch
- Use the generic "tidss_am65x_common_regs" as common reg space instead of creating a new one.
V2:
- Add separate common reg space for AM62L
- Add separate irq enable/disable/read/clear helpers for AM62L
- Use separate helper function for setting overlay attributes
- Drop Reviewed-by: Tomi Valkeinen <[email protected]> due to additional changes made in V2.
drivers/gpu/drm/tidss/tidss_dispc.c | 46 +++++++++++++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++ drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 49 insertions(+)
drivers/gpu/drm/tidss/tidss_dispc.c +46 -0
@@ -440,6 +440,47 @@ const struct dispc_features dispc_am62a7_feats = { .vid_order = {1, 0}, }; +const struct dispc_features dispc_am62l_feats = { + .max_pclk_khz = { + [DISPC_VP_DPI ] =165000 , + }, + + .subrev =DISPC_AM62L , + + .common ="common" , + .common_regs = tidss_am65x_common_regs, + + .num_vps =1 , + .vp_name = {"vp1" }, + .ovr_name = {"ovr1" }, + .vpclk_name = {"vp1" }, + .vp_bus_type = {DISPC_VP_DPI }, + + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size =256 , + .gamma_type =TIDSS_GAMMA_8BIT , + }, + }, + + .num_planes =2 , + + .vid_info = { + { + .vid_name ="vid" , + .vid_lite = false, + .is_present = false, + }, + { + .vid_name ="vidl1" , + .vid_lite = true, + .is_present = true, + } + }, + + .vid_order = {1 ,0 }, +}; +static const u16 *dispc_common_regmap; struct dss_vp_data {
@@ -957,6 +998,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc)return dispc_k2g_read_and_clear_irqstatus (dispc);case DISPC_AM625 :case DISPC_AM62A7 : +case DISPC_AM62L :case DISPC_AM65X :case DISPC_J721E :return dispc_k3_read_and_clear_irqstatus (dispc);
@@ -974,6 +1016,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)break ;case DISPC_AM625 :case DISPC_AM62A7 : +case DISPC_AM62L :case DISPC_AM65X :case DISPC_J721E :dispc_k3_set_irqenable (dispc, mask);
@@ -1466,6 +1509,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,break ;case DISPC_AM625 :case DISPC_AM62A7 : +case DISPC_AM62L :case DISPC_AM65X :dispc_am65x_ovr_set_plane (dispc, hw_plane, hw_videoport, x, y, layer);
@@ -2392,6 +2436,7 @@ static void dispc_plane_init(struct dispc_device *dispc)break ;case DISPC_AM625 :case DISPC_AM62A7 : +case DISPC_AM62L :case DISPC_AM65X :case DISPC_J721E :dispc_k3_plane_init (dispc);
@@ -2500,6 +2545,7 @@ static void dispc_vp_write_gamma_table(struct dispc_device *dispc,break ;case DISPC_AM625 :case DISPC_AM62A7 : +case DISPC_AM62L :case DISPC_AM65X :dispc_am65x_vp_write_gamma_table (dispc, hw_videoport);break ;
drivers/gpu/drm/tidss/tidss_dispc.h +2 -0
@@ -67,6 +67,7 @@ enum dispc_vp_bus_type {enum dispc_dss_subrevision {DISPC_K2G ,DISPC_AM625 , +DISPC_AM62L ,DISPC_AM62A7 ,DISPC_AM65X ,DISPC_J721E ,
@@ -96,6 +97,7 @@ struct dispc_features {extern const struct dispc_features dispc_k2g_feats;extern const struct dispc_features dispc_am625_feats;extern const struct dispc_features dispc_am62a7_feats; +extern const struct dispc_features dispc_am62l_feats;extern const struct dispc_features dispc_am65x_feats;extern const struct dispc_features dispc_j721e_feats;
drivers/gpu/drm/tidss/tidss_drv.c +1 -0
@@ -242,6 +242,7 @@ static const struct of_device_id tidss_of_table[] = { { .compatible = "ti,k2g-dss", .data = &dispc_k2g_feats, }, { .compatible = "ti,am625-dss", .data = &dispc_am625_feats, }, { .compatible = "ti,am62a7-dss", .data = &dispc_am62a7_feats, }, + { .compatible = "ti,am62l-dss", .data = &dispc_am62l_feats, }, { .compatible = "ti,am65x-dss", .data = &dispc_am65x_feats, }, { .compatible = "ti,j721e-dss", .data = &dispc_j721e_feats, }, { }
Signature · 1 line
2.39.1
Tomi Valkeinen
maintainerRe: [PATCH v3 3/3] drm/tidss: Add support for AM62L display subsystem
Hi,
Quoted 66 lines · Devarsh Thakkar
Enable display for AM62L DSS [1] which supports only a single display pipeline using a single overlay manager, single video port and a single video lite pipeline which does not support scaling.
The output of video port is routed to SoC boundary via DPI interface and the DPI signals from the video port are also routed to DSI Tx controller present within the SoC.
[1]: Section 11.7 (Display Subsystem and Peripherals)
Signed-off-by Devarsh Thakkar <[email protected]>---
V3:
- Rebase on top of 0002-drm-tidss-Update-infra-to-support-DSS7-cut-down-vers.patch
- Use the generic "tidss_am65x_common_regs" as common reg space instead of creating a new one.V2:
- Add separate common reg space for AM62L
- Add separate irq enable/disable/read/clear helpers for AM62L
- Use separate helper function for setting overlay attributes
- Drop Reviewed-by: Tomi Valkeinen <[email protected]> due to additional changes made in V2.drivers/gpu/drm/tidss/tidss_dispc.c | 46 +++++++++++++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++ drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 49 insertions(+)drivers/gpu/drm/tidss/tidss_dispc.c +27
-0@@ -440,6 +440,47 @@ const struct dispc_features dispc_am62a7_feats = { .vid_order = {1, 0}, }; +const struct dispc_features dispc_am62l_feats = { + .max_pclk_khz = { + [DISPC_VP_DPI] = 165000, + }, + + .subrev = DISPC_AM62L, + + .common = "common", + .common_regs = tidss_am65x_common_regs, + + .num_vps = 1, + .vp_name = { "vp1" }, + .ovr_name = { "ovr1" }, + .vpclk_name = { "vp1" }, + .vp_bus_type = { DISPC_VP_DPI }, + + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size = 256, + .gamma_type = TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes = 2, + + .vid_info = { + {
drivers/gpu/drm/tidss/tidss_dispc.c const struct dispc_features dispc_am62a7_feats = { · line 479
Quoted 10 lines
drivers/gpu/drm/tidss/tidss_dispc.c +10
-0+ .vid_name = "vid", + .vid_lite = false, + .is_present = false, + }, + { + .vid_name = "vidl1", + .vid_lite = true, + .is_present = true, + } + },
I don't think this is a good idea. Now you have tidss->num_planes 1, and feat->num_planes 2. It get's very confusing.
The naming is also mixed up. You have "vid_info" field, which has "plane_info" entries...
My suggestion is to have entries in vid_info only for the instantiated vids, like this:
struct vid_info {
u32 hw_id;
const char *name; /* Should match dt reg names */
bool is_lite;
};While at it, let's change the num_planes name in the feat struct too, to num_vids. This will also highlight all the places in the code that use the vid structs.
For AM62L it would be:
.num_vids = 1,
{
.hw_id = 1,
.name = "vidl1",
.is_lite = true,
}Tomi