riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110

PATCH RESEND Applied E Shattow 5 participants 12 messages Aug 23, 2025 – Sep 4, 2025

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Device tree bindings RISC-V Memory controller drivers StarFive devicetrees

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E Shattow

author

2025-08-23 10:03 UTC #0 lore raw

v3 cover riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110

Bring in additional downstream U-Boot boot loader changes for StarFive VisionFive2 board target (and related JH7110 common boards). Create a basic dt-binding (and not any Linux driver) in support of the memory-controller dts node used in mainline U-Boot. Also add bootph-pre-ram hinting to jh7110.dtsi needed at SPL boot phase.

Changes since v2:

- patch 1/3 "add StarFive JH7110 SoC DMC": wrap at 80 col, clock-names const is 'pll'.

- patch 2/3 "add memory controller node": memory-controller node follows sorting style by reg address, between watchdog and crypto nodes. Update clock-names to 'pll'.

- patch 3/3 "bootph-pre-ram hinting needed by boot loader": add missing hints for syscrg dependencies 'gmac1_rgmii_rxin', 'gmac1_rmii_refin', and 'pllclk'.

E Shattow (3):
dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
riscv: dts: starfive: jh7110: add DMC memory controller
riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
loader

 .../starfive,jh7110-dmc.yaml                  | 74 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 24 ++++++
 2 files changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

base-commit: 481ee0fcbb9a0f0706d6d29de9570d1048aff631

Signature · 1 line

2.50.0

E Shattow

author

2025-08-23 10:03 UTC #1 lore raw

PATCH v3 1/3 dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

Describe JH7110 SoC DDR external memory interface.

Signed-off-by E Shattow <[email protected]>

---
 .../starfive,jh7110-dmc.yaml                  | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file +74 -0

new file mode 100644
index 000000000000..d65313b33a3e
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 DMC
+
+maintainers:
+  - E Shattow <[email protected]>
+
+description:
+  JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at
+  2133Mbps (up to 2800Mbps).
+
+properties:
+  compatible:
+    items:
+      - const: starfive,jh7110-dmc
+
+  reg:
+    items:
+      - description: controller registers
+      - description: phy registers
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: pll
+
+  resets:
+    items:
+      - description: axi
+      - description: osc
+      - description: apb
+
+  reset-names:
+    items:
+      - const: axi
+      - const: osc
+      - const: apb
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive,jh7110-crg.h>
+    #include <dt-bindings/reset/starfive,jh7110-crg.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      memory-controller@15700000 {
+        compatible = "starfive,jh7110-dmc";
+        reg = <0x0 0x15700000 0x0 0x10000>,
+              <0x0 0x13000000 0x0 0x10000>;
+        clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+        clock-names = "pll";
+        resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+                 <&syscrg JH7110_SYSRST_DDR_OSC>,
+                 <&syscrg JH7110_SYSRST_DDR_APB>;
+        reset-names = "axi", "osc", "apb";
+      };
+    };

Signature · 1 line

2.50.0

E Shattow

author

2025-08-23 20:41 UTC #2 lore raw

Re: [PATCH v3 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

Quoted 10 lines · Krzysztof Kozlowski

Quoted 3 lines · E Shattow
Describe JH7110 SoC DDR external memory interface.
Signed-off-by E Shattow <[email protected]>
Don't send the same patch multiple times. To which one people should respond?
Best regards,
Krzysztof

Respond to v3 RESEND (this thread), or I may collect responses from either thread they are the same content. I'd missed a linux-riscv list CC line on a patch and that confused patchwork, and then I missed 'RESEND' in subject for the re-send series after the cover letter. Patchwork sees the RESEND series now, and sorry for the added noise. -E

Krzysztof Kozlowski

maintainer Reviewed-by on v3 1/3

2025-08-24 09:25 UTC #3 lore raw

Re: [PATCH v3 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

In reply to E Shattow

Quoted 7 lines · E Shattow

Describe JH7110 SoC DDR external memory interface.
Signed-off-by E Shattow <[email protected]>
---
 .../starfive,jh7110-dmc.yaml                  | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

Reviewed-by Krzysztof Kozlowski <[email protected]>

There is no memory controllers driver change, so I am fine if this goes via SoC/DTS tree. If you want me to pick it up, please ping on IRC.

Best regards,
Krzysztof

Conor Dooley

maintainer

2025-08-25 16:25 UTC #4 lore raw

Re: [PATCH v3 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

Quoted 9 lines · Krzysztof Kozlowski

Quoted 7 lines · E Shattow
Describe JH7110 SoC DDR external memory interface.
Signed-off-by E Shattow <[email protected]>
---
 .../starfive,jh7110-dmc.yaml                  | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

Quoted 4 lines

Reviewed-by Krzysztof Kozlowski <[email protected]>
There is no memory controllers driver change, so I am fine if this goes via SoC/DTS tree. If you want me to pick it up, please ping on IRC.

That's cool, I will take it with the dts changes. Thanks.

E Shattow

author

2025-08-23 10:03 UTC #5 lore raw

PATCH v3 2/3 riscv: dts: starfive: jh7110: add DMC memory controller

In reply to E Shattow

Add JH7110 SoC DDR external memory controller.

Signed-off-by E Shattow <[email protected]>

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/riscv/boot/dts/starfive/jh7110.dtsi +12 -0

index 0ba74ef04679..f3876660c07f 100644
@@ -931,6 +931,18 @@ watchdog@13070000 {
 				 <&syscrg JH7110_SYSRST_WDT_CORE>;
 		};
 
+		memory-controller@15700000 {
+			compatible = "starfive,jh7110-dmc";
+			reg = <0x0 0x15700000 0x0 0x10000>,
+			      <0x0 0x13000000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+			clock-names = "pll";
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				 <&syscrg JH7110_SYSRST_DDR_OSC>,
+				 <&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+		};
+
 		crypto: crypto@16000000 {
 			compatible = "starfive,jh7110-crypto";
 			reg = <0x0 0x16000000 0x0 0x4000>;

Signature · 1 line

2.50.0

Hal Feng

Reviewed-by on v3 2/3

2025-08-23 19:06 UTC #6 lore raw

RE: [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller

Quoted 5 lines · E Shattow

Add JH7110 SoC DDR external memory controller.
Signed-off-by E Shattow <[email protected]>

Reviewed-by Hal Feng <[email protected]>

Best regards,
Hal

Quoted 30 lines

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/riscv/boot/dts/starfive/jh7110.dtsi +12 -1

index 0ba74ef04679..f3876660c07f 100644
@@ -931,6 +931,18 @@ watchdog@13070000 {
 				 <&syscrg JH7110_SYSRST_WDT_CORE>;
 		};
 
+		memory-controller@15700000 {
+			compatible = "starfive,jh7110-dmc";
+			reg = <0x0 0x15700000 0x0 0x10000>,
+			      <0x0 0x13000000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+			clock-names = "pll";
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				 <&syscrg JH7110_SYSRST_DDR_OSC>,
+				 <&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+		};
+
 		crypto: crypto@16000000 {
 			compatible = "starfive,jh7110-crypto";
 			reg = <0x0 0x16000000 0x0 0x4000>;
--

2.50.0

E Shattow

author

2025-08-23 10:03 UTC #7 lore raw

PATCH v3 3/3 riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

In reply to E Shattow

Add bootph-pre-ram hinting to jh7110.dtsi:
- CPU interrupt controller(s)
- gmac1_rgmii_rxin fixed-clock (dependency of syscrg)
- gmac1_rmii_refin fixed-clock (dependency of syscrg)
- oscillator
- core local interrupt timer
- syscrg clock-controller
- pllclk clock-controller (dependency of syscrg)
- DDR memory controller

Signed-off-by E Shattow <[email protected]>

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/riscv/boot/dts/starfive/jh7110.dtsi +12 -0

index f3876660c07f..6e56e9d20bb0 100644
@@ -35,6 +35,7 @@ S7_0: cpu@0 {
 
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -68,6 +69,7 @@ U74_1: cpu@1 {
 
 			cpu1_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -101,6 +103,7 @@ U74_2: cpu@2 {
 
 			cpu2_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -134,6 +137,7 @@ U74_3: cpu@3 {
 
 			cpu3_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -167,6 +171,7 @@ U74_4: cpu@4 {
 
 			cpu4_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -273,12 +278,14 @@ gmac0_rmii_refin: gmac0-rmii-refin-clock {
 
 	gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
 		compatible = "fixed-clock";
+		bootph-pre-ram;
 		clock-output-names = "gmac1_rgmii_rxin";
 		#clock-cells = <0>;
 	};
 
 	gmac1_rmii_refin: gmac1-rmii-refin-clock {
 		compatible = "fixed-clock";
+		bootph-pre-ram;
 		clock-output-names = "gmac1_rmii_refin";
 		#clock-cells = <0>;
 	};

@@ -321,6 +328,7 @@ mclk_ext: mclk-ext-clock {
 
 	osc: oscillator {
 		compatible = "fixed-clock";
+		bootph-pre-ram;
 		clock-output-names = "osc";
 		#clock-cells = <0>;
 	};

@@ -354,6 +362,7 @@ soc {
 		clint: timer@2000000 {
 			compatible = "starfive,jh7110-clint", "sifive,clint0";
 			reg = <0x0 0x2000000 0x0 0x10000>;
+			bootph-pre-ram;
 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 					      <&cpu1_intc 3>, <&cpu1_intc 7>,
 					      <&cpu2_intc 3>, <&cpu2_intc 7>,

@@ -880,6 +889,7 @@ qspi: spi@13010000 {
 		syscrg: clock-controller@13020000 {
 			compatible = "starfive,jh7110-syscrg";
 			reg = <0x0 0x13020000 0x0 0x10000>;
+			bootph-pre-ram;
 			clocks = <&osc>, <&gmac1_rmii_refin>,
 				 <&gmac1_rgmii_rxin>,
 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,

@@ -904,6 +914,7 @@ sys_syscon: syscon@13030000 {
 
 			pllclk: clock-controller {
 				compatible = "starfive,jh7110-pll";
+				bootph-pre-ram;
 				clocks = <&osc>;
 				#clock-cells = <1>;
 			};

@@ -935,6 +946,7 @@ memory-controller@15700000 {
 			compatible = "starfive,jh7110-dmc";
 			reg = <0x0 0x15700000 0x0 0x10000>,
 			      <0x0 0x13000000 0x0 0x10000>;
+			bootph-pre-ram;
 			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
 			clock-names = "pll";
 			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,

Signature · 1 line

2.50.0

Hal Feng

Reviewed-by on v3 3/3

2025-08-23 17:50 UTC #8 lore raw

RE: [PATCH v3 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

Quoted 11 lines · E Shattow

Add bootph-pre-ram hinting to jh7110.dtsi:
- CPU interrupt controller(s)
- gmac1_rgmii_rxin fixed-clock (dependency of syscrg)
- gmac1_rmii_refin fixed-clock (dependency of syscrg)
- oscillator
- core local interrupt timer
- syscrg clock-controller
- pllclk clock-controller (dependency of syscrg)
- DDR memory controller

Quoted 1 line

Signed-off-by E Shattow <[email protected]>

Reviewed-by Hal Feng <[email protected]>

Best regards,
Hal

Quoted 107 lines

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/riscv/boot/dts/starfive/jh7110.dtsi +9 -0

index f3876660c07f..6e56e9d20bb0 100644
@@ -35,6 +35,7 @@ S7_0: cpu@0 {
 
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -68,6 +69,7 @@ U74_1: cpu@1 {
 
 			cpu1_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -101,6 +103,7 @@ U74_2: cpu@2 {
 
 			cpu2_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -134,6 +137,7 @@ U74_3: cpu@3 {
 
 			cpu3_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -167,6 +171,7 @@ U74_4: cpu@4 {
 
 			cpu4_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -273,12 +278,14 @@ gmac0_rmii_refin: gmac0-rmii-refin-clock {
 
 	gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
 		compatible = "fixed-clock";
+		bootph-pre-ram;
 		clock-output-names = "gmac1_rgmii_rxin";
 		#clock-cells = <0>;
 	};
 
 	gmac1_rmii_refin: gmac1-rmii-refin-clock {
 		compatible = "fixed-clock";
+		bootph-pre-ram;
 		clock-output-names = "gmac1_rmii_refin";
 		#clock-cells = <0>;
 	};

@@ -321,6 +328,7 @@ mclk_ext: mclk-ext-clock {
 
 	osc: oscillator {
 		compatible = "fixed-clock";
+		bootph-pre-ram;
 		clock-output-names = "osc";
 		#clock-cells = <0>;
 	};

@@ -354,6 +362,7 @@ soc {
 		clint: timer@2000000 {
 			compatible = "starfive,jh7110-clint", "sifive,clint0";
 			reg = <0x0 0x2000000 0x0 0x10000>;
+			bootph-pre-ram;
 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc
 7>,
 					      <&cpu1_intc 3>, <&cpu1_intc 7>,

arch/riscv/boot/dts/starfive/jh7110.dtsi +1 -0

 					      <&cpu2_intc 3>, <&cpu2_intc 7>,

@@ -880,6 +889,7 @@ qspi: spi@13010000 {
 		syscrg: clock-controller@13020000 {
 			compatible = "starfive,jh7110-syscrg";
 			reg = <0x0 0x13020000 0x0 0x10000>;
+			bootph-pre-ram;
 			clocks = <&osc>, <&gmac1_rmii_refin>,
 				 <&gmac1_rgmii_rxin>,
 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, @@ -

904,6 +914,7 @@ sys_syscon: syscon@13030000 {

arch/riscv/boot/dts/starfive/jh7110.dtsi +2 -1

 			pllclk: clock-controller {
 				compatible = "starfive,jh7110-pll";
+				bootph-pre-ram;
 				clocks = <&osc>;
 				#clock-cells = <1>;
 			};

@@ -935,6 +946,7 @@ memory-controller@15700000 {
 			compatible = "starfive,jh7110-dmc";
 			reg = <0x0 0x15700000 0x0 0x10000>,
 			      <0x0 0x13000000 0x0 0x10000>;
+			bootph-pre-ram;
 			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
 			clock-names = "pll";
 			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
--

2.50.0

Conor Dooley

maintainer

2025-08-27 17:28 UTC #9 lore raw

In reply to E Shattow

Quoted 5 lines · E Shattow

Bring in additional downstream U-Boot boot loader changes for StarFive VisionFive2 board target (and related JH7110 common boards). Create a basic dt-binding (and not any Linux driver) in support of the memory-controller dts node used in mainline U-Boot. Also add bootph-pre-ram hinting to jh7110.dtsi needed at SPL boot phase.

Emil, could you take a look at this please?

Emil Renner Berthing

Reviewed-by on the v3 series

2025-09-04 09:02 UTC #10 lore raw

In reply to E Shattow

Quoted 25 lines · E Shattow

Bring in additional downstream U-Boot boot loader changes for StarFive VisionFive2 board target (and related JH7110 common boards). Create a basic dt-binding (and not any Linux driver) in support of the memory-controller dts node used in mainline U-Boot. Also add bootph-pre-ram hinting to jh7110.dtsi needed at SPL boot phase.
Changes since v2:
- patch 1/3 "add StarFive JH7110 SoC DMC": wrap at 80 col, clock-names const is 'pll'.
- patch 2/3 "add memory controller node": memory-controller node follows sorting style by reg address, between watchdog and crypto nodes. Update clock-names to 'pll'.
- patch 3/3 "bootph-pre-ram hinting needed by boot loader": add missing hints for syscrg dependencies 'gmac1_rgmii_rxin', 'gmac1_rmii_refin', and 'pllclk'.
E Shattow (3):
dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
riscv: dts: starfive: jh7110: add DMC memory controller
riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
loader

Quoted 4 lines

 .../starfive,jh7110-dmc.yaml                  | 74 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 24 ++++++
 2 files changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

Thank you!

For the whole series:

Reviewed-by Emil Renner Berthing <[email protected]>

Conor Dooley

maintainer Applied

2025-09-04 17:58 UTC #11 lore raw

In reply to E Shattow

From: Conor Dooley <[email protected]>

Quoted 9 lines · E Shattow

Bring in additional downstream U-Boot boot loader changes for StarFive VisionFive2 board target (and related JH7110 common boards). Create a basic dt-binding (and not any Linux driver) in support of the memory-controller dts node used in mainline U-Boot. Also add bootph-pre-ram hinting to jh7110.dtsi needed at SPL boot phase.
Changes since v2:
[...]

Applied to riscv-dt-for-next, thanks!

[1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

      https://git.kernel.org/conor/c/f5e36ecc9e4a
[2/3] riscv: dts: starfive: jh7110: add DMC memory controller
      https://git.kernel.org/conor/c/7114969021ec
[3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader
      https://git.kernel.org/conor/c/8181cc2f3f21

Thanks,
Conor.