arm64: allwinner: a523: Enable MCU PRCM and NPU

From: Chen-Yu Tsai <[email protected]>

The main clock controller on the A523/T527 has the NPU's module clock. It was missing from the original submission, likely because that was based on the A523 user manual; the A523 is marketed without the NPU.

Also, merge the private header back into the driver code itself. The header only contains a macro containing the total number of clocks. This has to be updated every time a missing clock gets added. Having it in a separate file doesn't help the process. Instead just drop the macro, and thus the header no longer has any reason to exist.

Also move the .num value to after the list of clks to make it obvious that it should be updated when new clks are added.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
Changes since v1:
- Move .num to after list of clks

---
 drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 21 ++++++++++++++++++---
 drivers/clk/sunxi-ng/ccu-sun55i-a523.h | 14 --------------
 2 files changed, 18 insertions(+), 17 deletions(-)
 delete mode 100644 drivers/clk/sunxi-ng/ccu-sun55i-a523.h

drivers/clk/sunxi-ng/ccu-sun55i-a523.c +18 -3

index 1a9a1cb869e2..acb532f8361b 100644
@@ -11,6 +11,9 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
+#include <dt-bindings/clock/sun55i-a523-ccu.h>
+#include <dt-bindings/reset/sun55i-a523-ccu.h>
+
 #include "../clk.h"
 
 #include "ccu_common.h"

@@ -25,8 +28,6 @@
 #include "ccu_nkmp.h"
 #include "ccu_nm.h"
 
-#include "ccu-sun55i-a523.h"
-
 /*
  * The 24 MHz oscillator, the root of most of the clock tree.
  * .fw_name is the string used in the DT "clock-names" property, used to

@@ -486,6 +487,18 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
 
 static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws, 0x69c, BIT(0), 0);
 
+static const struct clk_hw *npu_parents[] = {
+	&pll_periph0_480M_clk.common.hw,
+	&pll_periph0_600M_clk.hw,
+	&pll_periph0_800M_clk.common.hw,
+	&pll_npu_2x_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0x6e0,
+				    0, 5,	/* M */
+				    24, 3,	/* mux */
+				    BIT(31),	/* gate */
+				    CLK_SET_RATE_PARENT);
+
 static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws, 0x70c, BIT(0), 0);
 
 static SUNXI_CCU_GATE_HWS(bus_msgbox_clk, "bus-msgbox", ahb_hws, 0x71c,

@@ -1217,6 +1230,7 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
 	&bus_ce_sys_clk.common,
 	&ve_clk.common,
 	&bus_ve_clk.common,
+	&npu_clk.common,
 	&bus_dma_clk.common,
 	&bus_msgbox_clk.common,
 	&bus_spinlock_clk.common,

@@ -1343,7 +1357,6 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
 };
 
 static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
-	.num	= CLK_NUMBER,
 	.hws	= {
 		[CLK_PLL_DDR0]		= &pll_ddr_clk.common.hw,
 		[CLK_PLL_PERIPH0_4X]	= &pll_periph0_4x_clk.common.hw,

@@ -1524,7 +1537,9 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
 		[CLK_FANOUT0]		= &fanout0_clk.common.hw,
 		[CLK_FANOUT1]		= &fanout1_clk.common.hw,
 		[CLK_FANOUT2]		= &fanout2_clk.common.hw,
+		[CLK_NPU]		= &npu_clk.common.hw,
 	},
+	.num	= CLK_NPU + 1,
 };
 
 static struct ccu_reset_map sun55i_a523_ccu_resets[] = {

drivers/clk/sunxi-ng/ccu-sun55i-a523.h deleted +0 -14

deleted file mode 100644
index fc8dd42f1b47..000000000000
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2024 Arm Ltd.
- */
-
-#ifndef _CCU_SUN55I_A523_H
-#define _CCU_SUN55I_A523_H
-
-#include <dt-bindings/clock/sun55i-a523-ccu.h>
-#include <dt-bindings/reset/sun55i-a523-ccu.h>
-
-#define CLK_NUMBER	(CLK_FANOUT2 + 1)
-
-#endif /* _CCU_SUN55I_A523_H */

From: Chen-Yu Tsai <[email protected]>

The main clock controller on the A523/T527 has the NPU's module clock. It was missing from the original submission, likely because that was based on the A523 user manual; the A523 is marketed without the NPU.

Also, merge the private header back into the driver code itself. The header only contains a macro containing the total number of clocks. This has to be updated every time a missing clock gets added. Having it in a separate file doesn't help the process. Instead just drop the macro, and thus the header no longer has any reason to exist.

Also move the .num value to after the list of clks to make it obvious that it should be updated when new clks are added.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
Changes since v1:
- Move .num to after list of clks

---
 drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 21 ++++++++++++++++++---
 drivers/clk/sunxi-ng/ccu-sun55i-a523.h | 14 --------------
 2 files changed, 18 insertions(+), 17 deletions(-)
 delete mode 100644 drivers/clk/sunxi-ng/ccu-sun55i-a523.h

drivers/clk/sunxi-ng/ccu-sun55i-a523.c +18 -3

index 1a9a1cb869e2..acb532f8361b 100644
@@ -11,6 +11,9 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
+#include <dt-bindings/clock/sun55i-a523-ccu.h>
+#include <dt-bindings/reset/sun55i-a523-ccu.h>
+
 #include "../clk.h"
 
 #include "ccu_common.h"

@@ -25,8 +28,6 @@
 #include "ccu_nkmp.h"
 #include "ccu_nm.h"
 
-#include "ccu-sun55i-a523.h"
-
 /*
  * The 24 MHz oscillator, the root of most of the clock tree.
  * .fw_name is the string used in the DT "clock-names" property, used to

@@ -486,6 +487,18 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
 
 static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws, 0x69c, BIT(0), 0);
 
+static const struct clk_hw *npu_parents[] = {
+	&pll_periph0_480M_clk.common.hw,
+	&pll_periph0_600M_clk.hw,
+	&pll_periph0_800M_clk.common.hw,
+	&pll_npu_2x_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0x6e0,
+				    0, 5,	/* M */
+				    24, 3,	/* mux */
+				    BIT(31),	/* gate */
+				    CLK_SET_RATE_PARENT);
+
 static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws, 0x70c, BIT(0), 0);
 
 static SUNXI_CCU_GATE_HWS(bus_msgbox_clk, "bus-msgbox", ahb_hws, 0x71c,

@@ -1217,6 +1230,7 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
 	&bus_ce_sys_clk.common,
 	&ve_clk.common,
 	&bus_ve_clk.common,
+	&npu_clk.common,
 	&bus_dma_clk.common,
 	&bus_msgbox_clk.common,
 	&bus_spinlock_clk.common,

@@ -1343,7 +1357,6 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
 };
 
 static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
-	.num	= CLK_NUMBER,
 	.hws	= {
 		[CLK_PLL_DDR0]		= &pll_ddr_clk.common.hw,
 		[CLK_PLL_PERIPH0_4X]	= &pll_periph0_4x_clk.common.hw,

@@ -1524,7 +1537,9 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
 		[CLK_FANOUT0]		= &fanout0_clk.common.hw,
 		[CLK_FANOUT1]		= &fanout1_clk.common.hw,
 		[CLK_FANOUT2]		= &fanout2_clk.common.hw,
+		[CLK_NPU]		= &npu_clk.common.hw,
 	},
+	.num	= CLK_NPU + 1,
 };
 
 static struct ccu_reset_map sun55i_a523_ccu_resets[] = {

drivers/clk/sunxi-ng/ccu-sun55i-a523.h deleted +0 -14

deleted file mode 100644
index fc8dd42f1b47..000000000000
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2024 Arm Ltd.
- */
-
-#ifndef _CCU_SUN55I_A523_H
-#define _CCU_SUN55I_A523_H
-
-#include <dt-bindings/clock/sun55i-a523-ccu.h>
-#include <dt-bindings/reset/sun55i-a523-ccu.h>
-
-#define CLK_NUMBER	(CLK_FANOUT2 + 1)
-
-#endif /* _CCU_SUN55I_A523_H */

From: Chen-Yu Tsai <[email protected]>

Some clocks (for timers) on the A523 are mux-divider-gate types with the divider being values of power-of-two.

Add a macro for these types of clocks so that we can use the divider types instead of the M-P types without an M divider.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 drivers/clk/sunxi-ng/ccu_div.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

drivers/clk/sunxi-ng/ccu_div.h +18 -0

index 90d49ee8e0cc..be00b3277e97 100644
@@ -274,6 +274,24 @@ struct ccu_div {
 	SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg,	\
 				  _mshift, _mwidth, 0, _flags)
 
+#define SUNXI_CCU_P_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg,	\
+				       _mshift, _mwidth,		\
+				       _muxshift, _muxwidth,		\
+				       _gate, _flags)			\
+	struct ccu_div _struct = {					\
+		.enable	= _gate,					\
+		.div	= _SUNXI_CCU_DIV_FLAGS(_mshift, _mwidth,	\
+					       CLK_DIVIDER_POWER_OF_TWO), \
+		.mux	= _SUNXI_CCU_MUX(_muxshift, _muxwidth),		\
+		.common	= {						\
+			.reg		= _reg,				\
+			.hw.init	= CLK_HW_INIT_PARENTS_DATA(_name, \
+								   _parents, \
+								   &ccu_div_ops, \
+								   _flags), \
+		},							\
+	}
+
 static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw)
 {
 	struct ccu_common *common = hw_to_ccu_common(hw);

From: Chen-Yu Tsai <[email protected]>

The A523/T527 SoCs have a new MCU PRCM, which has more clocks and reset controls for the RISC-V MCU and other peripherals. There is a second audio PLL, but no bus clock dividers. The BSP driver uses the 24MHz main oscillator as the parent for all the bus clocks. But the diagram suggests busses from the other PRCM are used in this block as well.

Add a driver to support this part. Unlike the BSP driver, the SoC's main MBUS clock is chosen as the parent for the MCU MBUS clock, and the latter then serves as the parent of the MCU DMA controller's MBUS clock. The bus gate clocks also use their respective bus clocks as parents according to the system bus tree diagram. In cases where a block does not appear in that diagram, an educated guess is made.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
Changes since v1:
- Added comment for "fixed" dividers in audio PLL clock
- Corrected variable names for audio PLL divider clocks
- Added comment for the reversed order of some of the DSP clock's parents when compared to the manual
- Added comments for clocks and resets only found in the BSP driver
- Corrected register offset for i2s3-asrc and bus-mcu-pwm0 clocks
- Made "r-ahb" and new "r-apb0" external bus clocks the parents of the bus gate clocks, with comments if guessed which one applies
- Moved .num_clks to after the list of clocks, making it obvious that the value needs to be added if more clocks are added to the list

From: Chen-Yu Tsai <[email protected]>

Add a device node for the third supported clock controller found in the A523 / T527 SoCs. This controller has clocks and resets for the RISC-V MCU, and others peripherals possibly meant to operate in low power mode driven by the MCU, such as audio interfaces, an audio DSP, and the NPU.

Reviewed-by Andre Przywara <[email protected]>

Signed-off-by Chen-Yu Tsai <[email protected]>

---
Changes since v1:
- Enlarged MCU PRCM register range to 0x200
- Moved "r-ahb" clock to the end of the list and added "r-apb0" clock

---
 .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +27 -0

index 79bd9ce08c7c..f93376372aba 100644
@@ -4,8 +4,10 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/sun6i-rtc.h>
 #include <dt-bindings/clock/sun55i-a523-ccu.h>
+#include <dt-bindings/clock/sun55i-a523-mcu-ccu.h>
 #include <dt-bindings/clock/sun55i-a523-r-ccu.h>
 #include <dt-bindings/reset/sun55i-a523-ccu.h>
+#include <dt-bindings/reset/sun55i-a523-mcu-ccu.h>
 #include <dt-bindings/reset/sun55i-a523-r-ccu.h>
 #include <dt-bindings/power/allwinner,sun55i-a523-ppu.h>
 #include <dt-bindings/power/allwinner,sun55i-a523-pck-600.h>

@@ -825,6 +827,31 @@ rtc: rtc@7090000 {
 			clock-names = "bus", "hosc", "ahb";
 			#clock-cells = <1>;
 		};
+
+		mcu_ccu: clock-controller@7102000 {
+			compatible = "allwinner,sun55i-a523-mcu-ccu";
+			reg = <0x7102000 0x200>;
+			clocks = <&osc24M>,
+				 <&rtc CLK_OSC32K>,
+				 <&rtc CLK_IOSC>,
+				 <&ccu CLK_PLL_AUDIO0_4X>,
+				 <&ccu CLK_PLL_PERIPH0_300M>,
+				 <&ccu CLK_DSP>,
+				 <&ccu CLK_MBUS>,
+				 <&r_ccu CLK_R_AHB>,
+				 <&r_ccu CLK_R_APB0>;
+			clock-names = "hosc",
+				      "losc",
+				      "iosc",
+				      "pll-audio0-4x",
+				      "pll-periph0-300m",
+				      "dsp",
+				      "mbus",
+				      "r-ahb",
+				      "r-apb0";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
 	};
 
 	thermal-zones {

From: Chen-Yu Tsai <[email protected]>

The Allwinner T527 SoC has an NPU built in. Based on identifiers found in the BSP, it is a Vivante IP block. After enabling it, the etnaviv driver reports it as a GC9000 revision 9003.

The standard bindings are used as everything matches directly. There is no option for DVFS at the moment. That might require some more work, perhaps on the efuse side to map speed bins.

It is unclear whether the NPU block is fused out at the hardware level or the BSP limits use of the NPU through software, as the author only has boards with the T527.

Reviewed-by Andre Przywara <[email protected]>

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +12 -0

index f93376372aba..9676caf9bd4e 100644
@@ -852,6 +852,18 @@ mcu_ccu: clock-controller@7102000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
+
+		npu: npu@7122000 {
+			compatible = "vivante,gc";
+			reg = <0x07122000 0x1000>;
+			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>,
+				 <&ccu CLK_NPU>,
+				 <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>;
+			clock-names = "bus", "core", "reg";
+			resets = <&mcu_ccu RST_BUS_MCU_NPU>;
+			power-domains = <&ppu PD_NPU>;
+		};
 	};
 
 	thermal-zones {

This is v2 of my A523 MCU PRCM and NPU support series.

Changes since v1:
- Dropped dual divider clock rate read-back fix that is already merged
- DT binding
- Moved "r-ahb" clock to the end of the list and added "r-apb0" clock
- Add NPU clk
- Move .num to after list of clks
- MCU CCU clk driver
- Added comment for "fixed" dividers in audio PLL clock
- Corrected variable names for audio PLL divider clocks
- Added comment for the reversed order of some of the DSP clock's parents when compared to the manual
- Added comments for clocks and resets only found in the BSP driver
- Corrected register offset for i2s3-asrc and bus-mcu-pwm0 clocks
- Made "r-ahb" and new "r-apb0" external bus clocks the parents of the bus gate clocks, with comments if guessed which one applies
- Moved .num_clks to after the list of clocks, making it obvious that the value needs to be added if more clocks are added to the list
- MCU CCU DT node
- Enlarged MCU PRCM register range to 0x200
- Moved "r-ahb" clock to the end of the list and added "r-apb0" clock
- Link to v1
https://lore.kernel.org/all/[email protected]/

[...]

This is v2 of my A523 MCU PRCM and NPU support series.

Changes since v1:
- Dropped dual divider clock rate read-back fix that is already merged
- DT binding
- Moved "r-ahb" clock to the end of the list and added "r-apb0" clock
- Add NPU clk
- Move .num to after list of clks
- MCU CCU clk driver
- Added comment for "fixed" dividers in audio PLL clock
- Corrected variable names for audio PLL divider clocks
- Added comment for the reversed order of some of the DSP clock's parents when compared to the manual
- Added comments for clocks and resets only found in the BSP driver
- Corrected register offset for i2s3-asrc and bus-mcu-pwm0 clocks
- Made "r-ahb" and new "r-apb0" external bus clocks the parents of the bus gate clocks, with comments if guessed which one applies
- Moved .num_clks to after the list of clocks, making it obvious that the value needs to be added if more clocks are added to the list
- MCU CCU DT node
- Enlarged MCU PRCM register range to 0x200
- Moved "r-ahb" clock to the end of the list and added "r-apb0" clock
- Link to v1
https://lore.kernel.org/all/[email protected]/

[...]

From: Chen-Yu Tsai <[email protected]>

Hi folks,

This is v2 of my A523 MCU PRCM and NPU support series.

Changes since v1:
- Dropped dual divider clock rate read-back fix that is already merged
- DT binding
- Moved "r-ahb" clock to the end of the list and added "r-apb0" clock
- Add NPU clk
- Move .num to after list of clks
- MCU CCU clk driver
- Added comment for "fixed" dividers in audio PLL clock
- Corrected variable names for audio PLL divider clocks
- Added comment for the reversed order of some of the DSP clock's parents when compared to the manual
- Added comments for clocks and resets only found in the BSP driver
- Corrected register offset for i2s3-asrc and bus-mcu-pwm0 clocks
- Made "r-ahb" and new "r-apb0" external bus clocks the parents of the bus gate clocks, with comments if guessed which one applies
- Moved .num_clks to after the list of clocks, making it obvious that the value needs to be added if more clocks are added to the list
- MCU CCU DT node
- Enlarged MCU PRCM register range to 0x200
- Moved "r-ahb" clock to the end of the list and added "r-apb0" clock
- Link to v1
https://lore.kernel.org/all/[email protected]/

[...]