drm/panthor: initial mt8196 support
Subsystems (6)
v2 cover drm/panthor: initial mt8196 support
MediaTek MT8196 has Mali-G925-Immortalis, for which panthor gained support recently. But the soc also requires custom ASN hash to be enabled. This series introduces panthor_soc_data for per-soc data and uses it to enable custom ASN hash on MT8196.
The clk/regulator provider on MT8196 is GPUEB, whose driver[1] needs to be cleaned up and upstreamed separately.
This initial support also lacks support for some hw configs. On some configs, panthor is expected to query a mask from efuse to mask out unavailable shader cores from ptdev->gpu_info.shader_present. This requires extending panthor_soc_data with a callback to read the mask.
This is an RFC because the dependent drivers are not ready yet. But I would like to gather opinions on having panthor_soc_data for soc-specific data and having CONFIG_DRM_PANTHOR_SOC_MT8196 for soc-specific code.
[1] https://gitlab.freedesktop.org/olv/kernel/-/commit/170d5fc90f817dc90bde54b32872c59cf5c77779
---
v2:
- drop RFC as this series works with the downstream GPUEB driver, and should work with Nicolas's GPUEB driver posted to
https://lore.kernel.org/lkml/[email protected]/
with no change.
- remove CONFIG_DRM_PANTHOR_SOC_MT8196 and panthor_soc*.[ch], as this initial support is just about ASN hash.
Chia-I Wu (2):
dt-bindings: gpu: mali-valhall-csf: add MediaTek MT8196 compatible drm/panthor: add custom ASN_HASH support for mt8196
.../bindings/gpu/arm,mali-valhall-csf.yaml | 1 + drivers/gpu/drm/panthor/panthor_device.c | 2 ++ drivers/gpu/drm/panthor/panthor_device.h | 14 +++++++++++ drivers/gpu/drm/panthor/panthor_drv.c | 6 +++++ drivers/gpu/drm/panthor/panthor_gpu.c | 25 ++++++++++++++++++- drivers/gpu/drm/panthor/panthor_regs.h | 4 +++ 6 files changed, 51 insertions(+), 1 deletion(-)
Signature · 1 line
2.51.0.384.g4c02a37b29-goog
PATCH v2 1/2 dt-bindings: gpu: mali-valhall-csf: add MediaTek MT8196 compatible
MediaTek MT8196 has Mali-G925-Immortalis GPU. panthor drm driver gained support for it recently.
---
v2: update commit message
--- Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +1 -0
@@ -18,6 +18,7 @@ properties: oneOf: - items: - enum: + - mediatek,mt8196-mali - rockchip,rk3588-mali - const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable
Signature · 1 line
2.51.0.384.g4c02a37b29-goog
Re: [PATCH v2 1/2] dt-bindings: gpu: mali-valhall-csf: add MediaTek MT8196 compatible
Re: [PATCH v2 1/2] dt-bindings: gpu: mali-valhall-csf: add MediaTek MT8196 compatible
Quoted 1 line · Conor Dooley
Acked-by Conor Dooley <[email protected]>
Hmm, actually there seems to be a more complete binding proposed here:
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]/
Re: [PATCH v2 1/2] dt-bindings: gpu: mali-valhall-csf: add MediaTek MT8196 compatible
Quoted 6 lines · Conor Dooley
Quoted 1 line · Conor Dooley
Acked-by Conor Dooley <[email protected]>Hmm, actually there seems to be a more complete binding proposed here:
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]/
Right. I tried to add the compatible to the binding (this patch) before adding it to the driver (next patch).
If this patch is not a prerequisite for the driver change, I can drop this. Or perhaps there is a better way?
Re: [PATCH v2 1/2] dt-bindings: gpu: mali-valhall-csf: add MediaTek MT8196 compatible
Quoted 5 lines · On Tuesday, 16 September 2025 06:21:10 Central European Summer Time Chia-I Wu…
Quoted 4 lines · Conor Dooley
Quoted 1 line · Conor Dooley
Acked-by Conor Dooley <[email protected]>
Quoted 8 lines
Quoted 2 lines
Hmm, actually there seems to be a more complete binding proposed here:
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]/Right. I tried to add the compatible to the binding (this patch) before adding it to the driver (next patch).
If this patch is not a prerequisite for the driver change, I can drop this. Or perhaps there is a better way?
Depends on what you want to do with the driver change; I could pull it into my patch series (I need it as a prerequisite now anyway, as v3 will get rid of the clocks for MT8196 in the binding, which means it needs to have a flag for this in the soc_data struct you've added)
I think that would be the easiest solution so that we don't step on each other's toes, as long as you think the driver change is basically in its final form right now and does not need major revisions you'd still like to make yourself without having to coordinate submission through me.
Or, the most roundabout option: I split the bindings I submitted into a separate series, and then we can both declare them as deps for our driver changes. That might thoroughly confuse maintainers though. But then you can declare a dep on the bindings series and I can declare a dep on the bindings series and your patch.
Kind regards,
Nicolas Frattaroli
Boris Brezillon
maintainerRe: [PATCH v2 1/2] dt-bindings: gpu: mali-valhall-csf: add MediaTek MT8196 compatible
Quoted 26 lines · On Tue, 16 Sep 2025 10:58:40 +0200 Nicolas Frattaroli…
Quoted 5 lines · On Tuesday, 16 September 2025 06:21:10 Central European Summer Time Chia-I Wu…
Quoted 4 lines · Conor Dooley
Quoted 1 line · Conor Dooley
Acked-by Conor Dooley <[email protected]>Quoted 8 lines
Quoted 2 lines
Hmm, actually there seems to be a more complete binding proposed here:
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]/Right. I tried to add the compatible to the binding (this patch) before adding it to the driver (next patch).
If this patch is not a prerequisite for the driver change, I can drop this. Or perhaps there is a better way?
Depends on what you want to do with the driver change; I could pull it into my patch series (I need it as a prerequisite now anyway, as v3 will get rid of the clocks for MT8196 in the binding, which means it needs to have a flag for this in the
soc_datastruct you've added)I think that would be the easiest solution so that we don't step on each other's toes, as long as you think the driver change is basically in its final form right now and does not need major revisions you'd still like to make yourself without having to coordinate submission through me.
Quoted 5 lines
Or, the most roundabout option: I split the bindings I submitted into a separate series, and then we can both declare them as deps for our driver changes. That might thoroughly confuse maintainers though. But then you can declare a dep on the bindings series and I can declare a dep on the bindings series and your patch.
The simplest option is probably to merge this series in drm-misc-next and rebase your GPUEB changes on drm-misc-next.
PATCH v2 2/2 drm/panthor: add custom ASN_HASH support for mt8196
In reply to Chia-I WuAdd panthor_soc_data to control custom ASN_HASH. Add compatible string for "mediatek,mt8196-mali" and enable custom ASN_HASH for the soc.
Without custom ASN_HASH, FW fails to boot
panthor 48000000.gpu: [drm] *ERROR* Unhandled Page fault in AS0 at VA 0x0000000000000000 panthor 48000000.gpu: [drm] *ERROR* Failed to boot MCU (status=fatal) panthor 48000000.gpu: probe with driver panthor failed with error -110
With custom ASN_HASH, panthor probes fine and userspace boots to ui just fine as well
panthor 48000000.gpu: [drm] clock rate = 0
panthor 48000000.gpu: EM: created perf domain
panthor 48000000.gpu: [drm] Mali-G925-Immortalis id 0xd830 major 0x0 minor 0x1 status 0x5 panthor 48000000.gpu: [drm] Features: L2:0x8130306 Tiler:0x809 Mem:0x301 MMU:0x2830 AS:0xff panthor 48000000.gpu: [drm] shader_present=0xee0077 l2_present=0x1 tiler_present=0x1 panthor 48000000.gpu: [drm] Firmware protected mode entry not be supported, ignoring panthor 48000000.gpu: [drm] Firmware git sha: 27713280172c742d467a4b7d11180930094092ec panthor 48000000.gpu: [drm] CSF FW using interface v3.13.0, Features 0x10 Instrumentation features 0x71 [drm] Initialized panthor 1.5.0 for 48000000.gpu on minor 1
Note that the clock and the regulator drivers are not upstreamed yet. They might as well take a different form when upstreamed.
---
v2:
- remove CONFIG_DRM_PANTHOR_SOC_MT8196 and panthor_soc*.[ch]
- update commit message
--- drivers/gpu/drm/panthor/panthor_device.c | 2 ++ drivers/gpu/drm/panthor/panthor_device.h | 14 +++++++++++++ drivers/gpu/drm/panthor/panthor_drv.c | 6 ++++++ drivers/gpu/drm/panthor/panthor_gpu.c | 25 +++++++++++++++++++++++- drivers/gpu/drm/panthor/panthor_regs.h | 4 ++++ 5 files changed, 50 insertions(+), 1 deletion(-)
drivers/gpu/drm/panthor/panthor_device.c +2 -0
@@ -172,6 +172,8 @@ int panthor_device_init(struct panthor_device *ptdev)struct page *p;int ret; + ptdev->soc_data =of_device_get_match_data (ptdev->base.dev); +init_completion (&ptdev->unplug.done); ret =drmm_mutex_init (&ptdev->base, &ptdev->unplug.lock);if (ret)
drivers/gpu/drm/panthor/panthor_device.h +14 -0
@@ -31,6 +31,17 @@ struct panthor_perfcnt;struct panthor_vm ;struct panthor_vm_pool ; +/** +* struct panthor_soc_data - Panthor SoC Data +*/ +struct panthor_soc_data { +/** @asn_hash_enable: True if GPU_L2_CONFIG_ASN_HASH_ENABLE must be set. */ +bool asn_hash_enable; + +/** @asn_hash: ASN_HASH values when asn_hash_enable is true. */ +u32 asn_hash[3 ]; +}; +/** * enum panthor_device_pm_state - PM state */
@@ -93,6 +104,9 @@ struct panthor_device {/** @base: Base drm_device. */ struct drm_device base; +/** @soc_data: Optional SoC data. */ +const struct panthor_soc_data *soc_data; +/** @phys_addr: Physical address of the iomem region. */ phys_addr_t phys_addr;
drivers/gpu/drm/panthor/panthor_drv.c +6 -0
@@ -1682,7 +1682,13 @@ static struct attribute *panthor_attrs[] = {ATTRIBUTE_GROUPS (panthor); +static const struct panthor_soc_data soc_data_mediatek_mt8196 = { + .asn_hash_enable = true, + .asn_hash = {0xb ,0xe ,0x0 , }, +}; +static const struct of_device_id dt_match[] = { + { .compatible ="mediatek,mt8196-mali" , .data = &soc_data_mediatek_mt8196, }, { .compatible ="rockchip,rk3588-mali" }, { .compatible ="arm,mali-valhall-csf" }, {}
drivers/gpu/drm/panthor/panthor_gpu.c +24 -1
@@ -52,6 +52,28 @@ static void panthor_gpu_coherency_set(struct panthor_device *ptdev) ptdev->coherent ? GPU_COHERENCY_PROT_BIT(ACE_LITE) : GPU_COHERENCY_NONE); } +static void panthor_gpu_l2_config_set (struct panthor_device *ptdev) +{ +const struct panthor_soc_data *data = ptdev->soc_data; +u32 l2_config; +u32 i; + +if (!data || !data->asn_hash_enable) +return ; + +if (GPU_ARCH_MAJOR (ptdev->gpu_info.gpu_id) <11 ) { +drm_err (&ptdev->base,"Custom ASN hash not supported by the device" ); +return ; + } + +for (i =0 ; i <ARRAY_SIZE (data->asn_hash); i++) +gpu_write (ptdev,GPU_ASN_HASH (i), data->asn_hash[i]); + + l2_config =gpu_read (ptdev,GPU_L2_CONFIG ); + l2_config |=GPU_L2_CONFIG_ASN_HASH_ENABLE ; +gpu_write (ptdev,GPU_L2_CONFIG , l2_config); +} +static void panthor_gpu_irq_handler (struct panthor_device *ptdev,u32 status) {gpu_write (ptdev,GPU_INT_CLEAR , status);
@@ -241,8 +263,9 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptdev) hweight64(ptdev->gpu_info.shader_present)); } -/* Set the desired coherency mode before the power up of L2 */ +/* Set the desired coherency mode and L2 config before the power up of L2 */ panthor_gpu_coherency_set (ptdev); +panthor_gpu_l2_config_set (ptdev);return panthor_gpu_power_on (ptdev,L2 ,1 ,20000 ); }
drivers/gpu/drm/panthor/panthor_regs.h +4 -0
@@ -64,6 +64,8 @@#define GPU_FAULT_STATUS 0x3C#define GPU_FAULT_ADDR 0x40 +#define GPU_L2_CONFIG 0x48 +#define GPU_L2_CONFIG_ASN_HASH_ENABLE BIT(24)#define GPU_PWR_KEY 0x50#define GPU_PWR_KEY_UNLOCK 0x2968A819
@@ -110,6 +112,8 @@#define GPU_REVID 0x280 +#define GPU_ASN_HASH (n) (0x2C0 + ((n) * 4)) +#define GPU_COHERENCY_FEATURES 0x300#define GPU_COHERENCY_PROT_BIT (name) BIT(GPU_COHERENCY_ ## name)
Signature · 1 line
2.51.0.384.g4c02a37b29-goog
Re: [PATCH v2 2/2] drm/panthor: add custom ASN_HASH support for mt8196
Quoted 22 lines · On Fri, 12 Sep 2025 17:21:55 -0700 Chia-I Wu <[email protected]> wrote:
Add
panthor_soc_datato control customASN_HASH. Add compatible string for "mediatek,mt8196-mali" and enable customASN_HASHfor the soc.Without custom
ASN_HASH, FW fails to bootpanthor 48000000.gpu: [drm] *ERROR* Unhandled Page fault in AS0 at VA
0x0000000000000000panthor 48000000.gpu: [drm] *ERROR* Failed to boot MCU (status=fatal) panthor 48000000.gpu: probe with driver panthor failed with error -110With custom
ASN_HASH, panthor probes fine and userspace boots to ui just fine as wellpanthor 48000000.gpu: [drm] clock rate = 0
panthor 48000000.gpu: EM: created perf domain
panthor 48000000.gpu: [drm] Mali-G925-Immortalis id0xd830major0x0minor0x1status0x5panthor 48000000.gpu: [drm] Features: L2:0x8130306 Tiler:0x809 Mem:0x301 MMU:0x2830 AS:0xff panthor 48000000.gpu: [drm] shader_present=0xee0077 l2_present=0x1 tiler_present=0x1 panthor 48000000.gpu: [drm] Firmware protected mode entry not be supported, ignoring panthor 48000000.gpu: [drm] Firmware git sha:27713280172c742d467a4b7d11180930094092ecpanthor 48000000.gpu: [drm] CSF FW using interface v3.13.0, Features0x10Instrumentation features0x71[drm] Initialized panthor 1.5.0 for 48000000.gpu on minor 1
Quoted 4 lines
Note that the clock and the regulator drivers are not upstreamed yet. They might as well take a different form when upstreamed.
Signed-off-by Chia-I Wu <[email protected]>
Quoted 142 lines
---
v2:
- removeCONFIG_DRM_PANTHOR_SOC_MT8196and panthor_soc*.[ch]
- update commit message--- drivers/gpu/drm/panthor/panthor_device.c | 2 ++ drivers/gpu/drm/panthor/panthor_device.h | 14 +++++++++++++ drivers/gpu/drm/panthor/panthor_drv.c | 6 ++++++ drivers/gpu/drm/panthor/panthor_gpu.c | 25 +++++++++++++++++++++++- drivers/gpu/drm/panthor/panthor_regs.h | 4 ++++ 5 files changed, 50 insertions(+), 1 deletion(-)drivers/gpu/drm/panthor/panthor_device.c +2
-0@@ -172,6 +172,8 @@ int panthor_device_init(struct panthor_device *ptdev)struct page *p;int ret; + ptdev->soc_data =of_device_get_match_data (ptdev->base.dev); +init_completion (&ptdev->unplug.done); ret =drmm_mutex_init (&ptdev->base, &ptdev->unplug.lock);if (ret)drivers/gpu/drm/panthor/panthor_device.h +14
-0@@ -31,6 +31,17 @@ struct panthor_perfcnt;struct panthor_vm ;struct panthor_vm_pool ; +/** +* struct panthor_soc_data - Panthor SoC Data +*/ +struct panthor_soc_data { +/** @asn_hash_enable: True if GPU_L2_CONFIG_ASN_HASH_ENABLE must be set. */ +bool asn_hash_enable; + +/** @asn_hash: ASN_HASH values when asn_hash_enable is true. */ +u32 asn_hash[3 ]; +}; +/** * enum panthor_device_pm_state - PM state */ @@ -93,6 +104,9 @@ struct panthor_device {/** @base: Base drm_device. */ struct drm_device base; +/** @soc_data: Optional SoC data. */ +const struct panthor_soc_data *soc_data; +/** @phys_addr: Physical address of the iomem region. */ phys_addr_t phys_addr;drivers/gpu/drm/panthor/panthor_drv.c +6
-0@@ -1682,7 +1682,13 @@ static struct attribute *panthor_attrs[] = {ATTRIBUTE_GROUPS (panthor); +static const struct panthor_soc_data soc_data_mediatek_mt8196 = { + .asn_hash_enable = true, + .asn_hash = {0xb ,0xe ,0x0 , }, +}; +static const struct of_device_id dt_match[] = { + { .compatible ="mediatek,mt8196-mali" , .data = &soc_data_mediatek_mt8196, }, { .compatible ="rockchip,rk3588-mali" }, { .compatible ="arm,mali-valhall-csf" }, {}drivers/gpu/drm/panthor/panthor_gpu.c +24
-1@@ -52,6 +52,28 @@ static void panthor_gpu_coherency_set(struct panthor_device *ptdev) ptdev->coherent ? GPU_COHERENCY_PROT_BIT(ACE_LITE) : GPU_COHERENCY_NONE); } +static void panthor_gpu_l2_config_set (struct panthor_device *ptdev) +{ +const struct panthor_soc_data *data = ptdev->soc_data; +u32 l2_config; +u32 i; + +if (!data || !data->asn_hash_enable) +return ; + +if (GPU_ARCH_MAJOR (ptdev->gpu_info.gpu_id) <11 ) { +drm_err (&ptdev->base,"Custom ASN hash not supported by the device" ); +return ; + } + +for (i =0 ; i <ARRAY_SIZE (data->asn_hash); i++) +gpu_write (ptdev,GPU_ASN_HASH (i), data->asn_hash[i]); + + l2_config =gpu_read (ptdev,GPU_L2_CONFIG ); + l2_config |=GPU_L2_CONFIG_ASN_HASH_ENABLE ; +gpu_write (ptdev,GPU_L2_CONFIG , l2_config); +} +static void panthor_gpu_irq_handler (struct panthor_device *ptdev,u32 status) {gpu_write (ptdev,GPU_INT_CLEAR , status);@@ -241,8 +263,9 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptdev) hweight64(ptdev->gpu_info.shader_present)); } -/* Set the desired coherency mode before the power up of L2 */ +/* Set the desired coherency mode and L2 config before the power up of L2 */ panthor_gpu_coherency_set (ptdev); +panthor_gpu_l2_config_set (ptdev);return panthor_gpu_power_on (ptdev,L2 ,1 ,20000 ); }drivers/gpu/drm/panthor/panthor_regs.h +4
-0@@ -64,6 +64,8 @@#define GPU_FAULT_STATUS 0x3C#define GPU_FAULT_ADDR 0x40 +#define GPU_L2_CONFIG 0x48 +#define GPU_L2_CONFIG_ASN_HASH_ENABLE BIT(24)#define GPU_PWR_KEY 0x50#define GPU_PWR_KEY_UNLOCK 0x2968A819@@ -110,6 +112,8 @@#define GPU_REVID 0x280 +#define GPU_ASN_HASH (n) (0x2C0 + ((n) * 4)) +#define GPU_COHERENCY_FEATURES 0x300#define GPU_COHERENCY_PROT_BIT (name) BIT(GPU_COHERENCY_ ## name)
Re: [PATCH v2 2/2] drm/panthor: add custom ASN_HASH support for mt8196
In reply to Chia-I WuQuoted 22 lines · Chia-I Wu
Add
panthor_soc_datato control customASN_HASH. Add compatible string for "mediatek,mt8196-mali" and enable customASN_HASHfor the soc.Without custom
ASN_HASH, FW fails to bootpanthor 48000000.gpu: [drm] *ERROR* Unhandled Page fault in AS0 at VA
0x0000000000000000panthor 48000000.gpu: [drm] *ERROR* Failed to boot MCU (status=fatal) panthor 48000000.gpu: probe with driver panthor failed with error -110With custom
ASN_HASH, panthor probes fine and userspace boots to ui just fine as wellpanthor 48000000.gpu: [drm] clock rate = 0
panthor 48000000.gpu: EM: created perf domain
panthor 48000000.gpu: [drm] Mali-G925-Immortalis id0xd830major0x0minor0x1status0x5panthor 48000000.gpu: [drm] Features: L2:0x8130306 Tiler:0x809 Mem:0x301 MMU:0x2830 AS:0xff panthor 48000000.gpu: [drm] shader_present=0xee0077 l2_present=0x1 tiler_present=0x1 panthor 48000000.gpu: [drm] Firmware protected mode entry not be supported, ignoring panthor 48000000.gpu: [drm] Firmware git sha:27713280172c742d467a4b7d11180930094092ecpanthor 48000000.gpu: [drm] CSF FW using interface v3.13.0, Features0x10Instrumentation features0x71[drm] Initialized panthor 1.5.0 for 48000000.gpu on minor 1
Quoted 4 lines
Note that the clock and the regulator drivers are not upstreamed yet. They might as well take a different form when upstreamed.
Signed-off-by Chia-I Wu <[email protected]>
Quoted 142 lines
---
v2:
- removeCONFIG_DRM_PANTHOR_SOC_MT8196and panthor_soc*.[ch]
- update commit message--- drivers/gpu/drm/panthor/panthor_device.c | 2 ++ drivers/gpu/drm/panthor/panthor_device.h | 14 +++++++++++++ drivers/gpu/drm/panthor/panthor_drv.c | 6 ++++++ drivers/gpu/drm/panthor/panthor_gpu.c | 25 +++++++++++++++++++++++- drivers/gpu/drm/panthor/panthor_regs.h | 4 ++++ 5 files changed, 50 insertions(+), 1 deletion(-)drivers/gpu/drm/panthor/panthor_device.c +2
-0@@ -172,6 +172,8 @@ int panthor_device_init(struct panthor_device *ptdev)struct page *p;int ret; + ptdev->soc_data =of_device_get_match_data (ptdev->base.dev); +init_completion (&ptdev->unplug.done); ret =drmm_mutex_init (&ptdev->base, &ptdev->unplug.lock);if (ret)drivers/gpu/drm/panthor/panthor_device.h +14
-0@@ -31,6 +31,17 @@ struct panthor_perfcnt;struct panthor_vm ;struct panthor_vm_pool ; +/** +* struct panthor_soc_data - Panthor SoC Data +*/ +struct panthor_soc_data { +/** @asn_hash_enable: True if GPU_L2_CONFIG_ASN_HASH_ENABLE must be set. */ +bool asn_hash_enable; + +/** @asn_hash: ASN_HASH values when asn_hash_enable is true. */ +u32 asn_hash[3 ]; +}; +/** * enum panthor_device_pm_state - PM state */ @@ -93,6 +104,9 @@ struct panthor_device {/** @base: Base drm_device. */ struct drm_device base; +/** @soc_data: Optional SoC data. */ +const struct panthor_soc_data *soc_data; +/** @phys_addr: Physical address of the iomem region. */ phys_addr_t phys_addr;drivers/gpu/drm/panthor/panthor_drv.c +6
-0@@ -1682,7 +1682,13 @@ static struct attribute *panthor_attrs[] = {ATTRIBUTE_GROUPS (panthor); +static const struct panthor_soc_data soc_data_mediatek_mt8196 = { + .asn_hash_enable = true, + .asn_hash = {0xb ,0xe ,0x0 , }, +}; +static const struct of_device_id dt_match[] = { + { .compatible ="mediatek,mt8196-mali" , .data = &soc_data_mediatek_mt8196, }, { .compatible ="rockchip,rk3588-mali" }, { .compatible ="arm,mali-valhall-csf" }, {}drivers/gpu/drm/panthor/panthor_gpu.c +24
-1@@ -52,6 +52,28 @@ static void panthor_gpu_coherency_set(struct panthor_device *ptdev) ptdev->coherent ? GPU_COHERENCY_PROT_BIT(ACE_LITE) : GPU_COHERENCY_NONE); } +static void panthor_gpu_l2_config_set (struct panthor_device *ptdev) +{ +const struct panthor_soc_data *data = ptdev->soc_data; +u32 l2_config; +u32 i; + +if (!data || !data->asn_hash_enable) +return ; + +if (GPU_ARCH_MAJOR (ptdev->gpu_info.gpu_id) <11 ) { +drm_err (&ptdev->base,"Custom ASN hash not supported by the device" ); +return ; + } + +for (i =0 ; i <ARRAY_SIZE (data->asn_hash); i++) +gpu_write (ptdev,GPU_ASN_HASH (i), data->asn_hash[i]); + + l2_config =gpu_read (ptdev,GPU_L2_CONFIG ); + l2_config |=GPU_L2_CONFIG_ASN_HASH_ENABLE ; +gpu_write (ptdev,GPU_L2_CONFIG , l2_config); +} +static void panthor_gpu_irq_handler (struct panthor_device *ptdev,u32 status) {gpu_write (ptdev,GPU_INT_CLEAR , status);@@ -241,8 +263,9 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptdev) hweight64(ptdev->gpu_info.shader_present)); } -/* Set the desired coherency mode before the power up of L2 */ +/* Set the desired coherency mode and L2 config before the power up of L2 */ panthor_gpu_coherency_set (ptdev); +panthor_gpu_l2_config_set (ptdev);return panthor_gpu_power_on (ptdev,L2 ,1 ,20000 ); }drivers/gpu/drm/panthor/panthor_regs.h +4
-0@@ -64,6 +64,8 @@#define GPU_FAULT_STATUS 0x3C#define GPU_FAULT_ADDR 0x40 +#define GPU_L2_CONFIG 0x48 +#define GPU_L2_CONFIG_ASN_HASH_ENABLE BIT(24)#define GPU_PWR_KEY 0x50#define GPU_PWR_KEY_UNLOCK 0x2968A819@@ -110,6 +112,8 @@#define GPU_REVID 0x280 +#define GPU_ASN_HASH (n) (0x2C0 + ((n) * 4)) +#define GPU_COHERENCY_FEATURES 0x300#define GPU_COHERENCY_PROT_BIT (name) BIT(GPU_COHERENCY_ ## name)
Quoted 13 lines · Chia-I Wu
MediaTek MT8196 has Mali-G925-Immortalis, for which panthor gained support recently. But the soc also requires custom ASN hash to be enabled. This series introduces
panthor_soc_datafor per-soc data and uses it to enable custom ASN hash on MT8196.The clk/regulator provider on MT8196 is GPUEB, whose driver[1] needs to be cleaned up and upstreamed separately.
This initial support also lacks support for some hw configs. On some configs, panthor is expected to query a mask from efuse to mask out unavailable shader cores from
ptdev->gpu_info.shader_present. This requires extendingpanthor_soc_datawith a callback to read the mask.
Quoted 6 lines
This is an RFC because the dependent drivers are not ready yet. But I would like to gather opinions on having
panthor_soc_datafor soc-specific data and havingCONFIG_DRM_PANTHOR_SOC_MT8196for soc-specific code.[1] https://gitlab.freedesktop.org/olv/kernel/-/commit/170d5fc90f817dc90bde54b32872c59cf5c77779
Applied to drm-misc-next.
Thanks,
Steve
Quoted 23 lines
---
v2:- drop RFC as this series works with the downstream GPUEB driver, and should work with Nicolas's GPUEB driver posted to
https://lore.kernel.org/lkml/[email protected]/
with no change.
- removeCONFIG_DRM_PANTHOR_SOC_MT8196and panthor_soc*.[ch], as this initial support is just about ASN hash.Chia-I Wu (2):
dt-bindings: gpu: mali-valhall-csf: add MediaTek MT8196 compatible drm/panthor: add customASN_HASHsupport for mt8196.../bindings/gpu/arm,mali-valhall-csf.yaml | 1 + drivers/gpu/drm/panthor/panthor_device.c | 2 ++ drivers/gpu/drm/panthor/panthor_device.h | 14 +++++++++++ drivers/gpu/drm/panthor/panthor_drv.c | 6 +++++ drivers/gpu/drm/panthor/panthor_gpu.c | 25 ++++++++++++++++++- drivers/gpu/drm/panthor/panthor_regs.h | 4 +++ 6 files changed, 51 insertions(+), 1 deletion(-)