Skip to contentSkip to conversation

Add driver support for Eswin EIC7700 SoC SATA Controller and PHY

PATCH Superseded Yulin Lu 2 participants 6 messages Sep 15, 2025 – Sep 23, 2025

Subsystems (3)

v4 of 9 Superseded Latest is v9 →

lore
Share & tools
lore

Yulin Lu

author
#0 lore raw

v4 cover Add driver support for Eswin EIC7700 SoC SATA Controller and PHY

This series depends on the config option patch [1].

[1] https://lore.kernel.org/all/[email protected]/

Updates:
v4 -> v3:
- eswin,eic7700-ahci.yaml
- Fix grammatical errors in patch subject and commit message
- Add an explanation in the commit message of patch 1 for retaining the "ports-implemented" field, which Rob Herring suggested to remove
in the review comments on v2.
Link to Rob Herring's review:
https://lore.kernel.org/lkml/CAL_JsqKFotNLZZXwiy7S6K8qXLdGRAnsa-1zvZRDQBE39Gf5kg@mail.gmail.com/
Link to my question and Niklas Cassel's reply:
https://lore.kernel.org/lkml/[email protected]/
In this reply, Niklas Cassel mentioned his view:
If the ports-implemented register gets reset from ahci_platform_assert_rsts(), then it seems acceptable to
retain the ports-implemented property in the device tree.
This aligns with our design.
Link to my reply:
https://lore.kernel.org/lkml/[email protected]/
Link to Niklas Cassel's question and my further explanation:
https://lore.kernel.org/lkml/aLlYkZWBaI5Yz6fo@ryzen/
https://lore.kernel.org/lkml/[email protected]/
- eswin,eic7700-sata-phy.yaml
- Fix grammatical errors in patch subject and commit message
- Adjust the position of reg in the properties and required arrays
- Add reviewed-by tag of Krzysztof Kozlowski
- phy-eic7700-sata.c
- Correct the loop condition in wait_for_phy_ready() to use the current jiffies instead of the fixed start time
- Change the return value from -EFAULT to -ETIMEDOUT to correctly
indicate a timeout condition
- Remove redundant clock disable handling in probe error path, as SATA_SYS_CLK_EN is managed in phy_init() and phy_exit()
- Use dev_err_probe return in probe
- Reorder local variables to follow reverse Xmas tree order
- Wrap each line in the extended comments to 80 columns before splitting lines
- Adjust the position of #include <linux/io.h> for proper ordering
- Link to v3: https://lore.kernel.org/lkml/[email protected]/

v2 -> v3:
- Use full name in "From" and "Signed-off-by" fields information
- eswin,eic7700-ahci.yaml
- Remove the introduction to the reg, interrupts, phys, and phy-names fields
- Modify the usage of the clocks field in the examples
- Correct the order of dt properties
- phy-eic7700-sata.c
- Register operations use the GENMASK macro and FIELD_PREP instead of
the original bit offset method, and add "#include <linux/bitfield.h>"
- Modify some macro definition names.
- Remove the redundant initialization assignments for "ret" and "val"
- Delete ".suppress_bind_attrs = true"
- Modify the driver name
- Add "#include <linux/io.h>" to fix the robot test issue
- Link to v2: https://lore.kernel.org/lkml/[email protected]/

v2 -> v1:
- Delete the original controller driver and use ahci_dwc.c instead
- Add eswin,eic7700-ahci.yaml
- Correct the descriptions of reset, interrupt and other
hardware resources for the sata controller on EIC7700 SoC
- The clocks for both sata controller and sata PHY are controlled
via a register bit in the HSP bus and are not registered in the
clock tree. Clock are managed within the PHY driver, therefore
it is not described in this document
- Add $ref: snps,dwc-ahci-common.yaml#.
- Add eswin,eic7700-sata-phy.yaml
- Add this file to include the description of the PHY on EIC7700 SoC
- Add an eswin directory under the PHY driver path, and include the SATA
PHY driver code for EIC7700 SoC
- Link to v1: https://lore.kernel.org/all/[email protected]/

Yulin Lu (3):
Document the EIC7700 SoC sata ahci
dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver

 .../bindings/ata/eswin,eic7700-ahci.yaml      |  79 +++++++
 .../bindings/phy/eswin,eic7700-sata-phy.yaml  |  36 ++++
 drivers/phy/Kconfig                           |   1 +
 drivers/phy/Makefile                          |   1 +
 drivers/phy/eswin/Kconfig                     |  14 ++
 drivers/phy/eswin/Makefile                    |   2 +
 drivers/phy/eswin/phy-eic7700-sata.c          | 192 ++++++++++++++++++
 7 files changed, 325 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
 create mode 100644 drivers/phy/eswin/Kconfig
 create mode 100644 drivers/phy/eswin/Makefile
 create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c
Signature · 1 line
2.25.1
author
#1 lore raw

PATCH v4 1/3 Document the EIC7700 SoC sata ahci

Document the SATA AHCI controller on the EIC7700 SoC platform, including descriptions of its hardware configurations.

Retains the "ports-implemented" property in the DTS, because removing it and relying only on the firmware register causes problems. If the property is not present and we remove the module using rmmod, a reset is triggered that clears the register. As a result, inserting module again using insmod will lead to errors.

The detailed reasons are that the ports-implemented register is configured by the firmware (U-Boot on the HiFive Premier P550 board) before kernel entry and correctly set to 0x1. During probe, ahci_platform_enable_resources() -> ahci_platform_deassert_rsts() is called, and when the driver is removed, ahci_platform_disable_resources() -> ahci_platform_assert_rsts() is called. This reset clears the register, which is defined by the IP databook to reset to 0.

---
 .../bindings/ata/eswin,eic7700-ahci.yaml      | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml
Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml new file +79 -0
new file mode 100644
index 000000000000..40c44f0705ba
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/eswin,eic7700-ahci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 SoC SATA Controller
+
+maintainers:
+  - Yulin Lu <[email protected]>
+  - Huan He <[email protected]>
+
+description:
+  AHCI SATA controller embedded into the EIC7700 SoC
+  is based on the DWC AHCI SATA v5.00a IP core.
+
+select:
+  properties:
+    compatible:
+      const: eswin,eic7700-ahci
+  required:
+    - compatible
+
+allOf:
+  - $ref: snps,dwc-ahci-common.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: eswin,eic7700-ahci
+      - const: snps,dwc-ahci
+
+  clocks:
+    minItems: 2
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: pclk
+      - const: aclk
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    const: arst
+
+  ports-implemented:
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - phys
+  - phy-names
+  - ports-implemented
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    sata@50420000 {
+        compatible = "eswin,eic7700-ahci", "snps,dwc-ahci";
+        reg = <0x50420000 0x10000>;
+        interrupt-parent = <&plic>;
+        interrupts = <58>;
+        clocks = <&clock 171>, <&clock 186>;
+        clock-names = "pclk", "aclk";
+        phys = <&sata_phy>;
+        phy-names = "sata-phy";
+        ports-implemented = <0x1>;
+        resets = <&reset 96>;
+        reset-names = "arst";
+    };
Signature · 7 lines
2.25.1


-- 
linux-phy mailing list
[email protected]
https://lists.infradead.org/mailman/listinfo/linux-phy
maintainer
#2 lore raw

Re: [PATCH v4 1/3] Document the EIC7700 SoC sata ahci

Quoted 2 lines · Yulin Lu

Document the SATA AHCI controller on the EIC7700 SoC platform, including descriptions of its hardware configurations.

Please fix the subject: "dt-bindings: ata: ..."

Quoted 34 lines

Retains the "ports-implemented" property in the DTS, because removing it and relying only on the firmware register causes problems. If the property is not present and we remove the module using rmmod, a reset is triggered that clears the register. As a result, inserting module again using insmod will lead to errors.

The detailed reasons are that the ports-implemented register is configured by the firmware (U-Boot on the HiFive Premier P550 board) before kernel entry and correctly set to 0x1. During probe, ahci_platform_enable_resources() -> ahci_platform_deassert_rsts() is called, and when the driver is removed, ahci_platform_disable_resources() -> ahci_platform_assert_rsts() is called. This reset clears the register, which is defined by the IP databook to reset to 0.

---
 .../bindings/ata/eswin,eic7700-ahci.yaml      | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml
Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml new file +5 -0
new file mode 100644
index 000000000000..40c44f0705ba
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/eswin,eic7700-ahci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml line 15

Quoted 10 lines
Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml new file +10 -0
+
+title: Eswin EIC7700 SoC SATA Controller
+
+maintainers:
+  - Yulin Lu <[email protected]>
+  - Huan He <[email protected]>
+
+description:
+  AHCI SATA controller embedded into the EIC7700 SoC
+  is based on the DWC AHCI SATA v5.00a IP core.

Wrap at 80 chars.

Quoted 67 lines
Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml new file +64 -0
+
+select:
+  properties:
+    compatible:
+      const: eswin,eic7700-ahci
+  required:
+    - compatible
+
+allOf:
+  - $ref: snps,dwc-ahci-common.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: eswin,eic7700-ahci
+      - const: snps,dwc-ahci
+
+  clocks:
+    minItems: 2
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: pclk
+      - const: aclk
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    const: arst
+
+  ports-implemented:
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - phys
+  - phy-names
+  - ports-implemented
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    sata@50420000 {
+        compatible = "eswin,eic7700-ahci", "snps,dwc-ahci";
+        reg = <0x50420000 0x10000>;
+        interrupt-parent = <&plic>;
+        interrupts = <58>;
+        clocks = <&clock 171>, <&clock 186>;
+        clock-names = "pclk", "aclk";
+        phys = <&sata_phy>;
+        phy-names = "sata-phy";
+        ports-implemented = <0x1>;
+        resets = <&reset 96>;
+        reset-names = "arst";
+    };
Signature · 1 line
2.25.1
#3 lore raw

Re: Re: [PATCH v4 1/3] Document the EIC7700 SoC sata ahci

Hi, Rob Herring

Thank you for your review and comments.

Quoted 7 lines · Yulin Lu
Quoted 2 lines

Document the SATA AHCI controller on the EIC7700 SoC platform, including descriptions of its hardware configurations.

Please fix the subject: "dt-bindings: ata: ..."

I previously noticed this subject issue, then resubmitted v4 and explained the reason in the cover letter.
The links to these patches are:
https://lore.kernel.org/lkml/[email protected]/

Quoted 1 line
Quoted 1 line

...

Quoted 6 lines

Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml line 15

Quoted 3 lines
Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml new file +3 -0
+description:
+  AHCI SATA controller embedded into the EIC7700 SoC
+  is based on the DWC AHCI SATA v5.00a IP core.

Wrap at 80 chars.

Thanks, I will fix it in the next patch.

Quoted 1 line
Quoted 1 line

+

...

Quoted 3 lines
Quoted 3 lines
Signature · 1 line
2.25.1

Best regards,
Yulin Lu

Signature · 3 lines
linux-phy mailing list
[email protected]
https://lists.infradead.org/mailman/listinfo/linux-phy
author
#4 lore raw

PATCH v4 2/3 dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY

In reply to Yulin Lu

Document the SATA PHY on the EIC7700 SoC platform, describing its usage.

---
 .../bindings/phy/eswin,eic7700-sata-phy.yaml  | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml new file +36 -0
new file mode 100644
index 000000000000..439633827153
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/eswin,eic7700-sata-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 SoC SATA PHY
+
+maintainers:
+  - Yulin Lu <[email protected]>
+  - Huan He <[email protected]>
+
+properties:
+  compatible:
+    const: eswin,eic7700-sata-phy
+
+  reg:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    sata-phy@50440300 {
+        compatible = "eswin,eic7700-sata-phy";
+        reg = <0x50440300 0x40>;
+        #phy-cells = <0>;
+    };
Signature · 7 lines
2.25.1


-- 
linux-phy mailing list
[email protected]
https://lists.infradead.org/mailman/listinfo/linux-phy
author
#5 lore raw

PATCH v4 3/3 phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver

In reply to Yulin Lu

Created the eswin phy driver directory and added support for the SATA phy driver on the EIC7700 SoC platform.

---
 drivers/phy/Kconfig                  |   1 +
 drivers/phy/Makefile                 |   1 +
 drivers/phy/eswin/Kconfig            |  14 ++
 drivers/phy/eswin/Makefile           |   2 +
 drivers/phy/eswin/phy-eic7700-sata.c | 192 +++++++++++++++++++++++++++
 5 files changed, 210 insertions(+)
 create mode 100644 drivers/phy/eswin/Kconfig
 create mode 100644 drivers/phy/eswin/Makefile
 create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c
drivers/phy/Kconfig +1 -0
index 58c911e1b2d2..e82ebcfe534a 100644
@@ -105,6 +105,7 @@ source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
 source "drivers/phy/cadence/Kconfig"
+source "drivers/phy/eswin/Kconfig"
 source "drivers/phy/freescale/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
 source "drivers/phy/ingenic/Kconfig"
drivers/phy/Makefile +1 -0
index c670a8dac468..ed7444949259 100644
@@ -17,6 +17,7 @@ obj-y					+= allwinner/	\
 					   amlogic/	\
 					   broadcom/	\
 					   cadence/	\
+					   eswin/	\
 					   freescale/	\
 					   hisilicon/	\
 					   ingenic/	\
drivers/phy/eswin/Kconfig new file +14 -0
new file mode 100644
index 000000000000..3fcd76582c3b
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Phy drivers for Eswin platforms
+#
+config PHY_EIC7700_SATA
+	tristate "eic7700 Sata SerDes/PHY driver"
+	depends on ARCH_ESWIN || COMPILE_TEST
+	depends on HAS_IOMEM
+	select GENERIC_PHY
+	help
+	  Enable this to support SerDes/Phy found on ESWIN's
+	  EIC7700 SoC.This Phy supports SATA 1.5 Gb/s,
+	  SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.
+	  It supports one SATA host port to accept one SATA device.
drivers/phy/eswin/Makefile new file +2 -0
new file mode 100644
index 000000000000..db08c66be812
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_PHY_EIC7700_SATA)	+= phy-eic7700-sata.o
drivers/phy/eswin/phy-eic7700-sata.c new file +192 -0

192 lines not on this page · raw message

Signature · 7 lines
2.25.1


-- 
linux-phy mailing list
[email protected]
https://lists.infradead.org/mailman/listinfo/linux-phy