arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2

PATCH Applied Chaoyi Chen 4 participants 4 messages Sep 18, 2025 – Oct 14, 2025

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Chaoyi Chen

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2025-09-18 06:29 UTC #0 lore raw

PATCH v2 1/1 arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2

From: Chaoyi Chen <[email protected]>

The rk3588 evb2 board has a full size DisplayPort connector, enable for it.

Signed-off-by Chaoyi Chen <[email protected]>

---

Changes in v2:

- Link to V1: https://lore.kernel.org/all/[email protected]/
- Fix invalid DP connector type
- Add more comment about dclk_vp2 parent clock

 .../boot/dts/rockchip/rk3588-evb2-v10.dts     | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)

arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts +48 -0

index 91fe810d38d8..60ba6ac55b23 100644
@@ -25,6 +25,18 @@ chosen {
 		stdout-path = "serial2:1500000n8";
 	};
 
+	dp-con {
+		compatible = "dp-connector";
+		label = "DP OUT";
+		type = "full-size";
+
+		port {
+			dp_con_in: endpoint {
+				remote-endpoint = <&dp0_out_con>;
+			};
+		};
+	};
+
 	hdmi-con {
 		compatible = "hdmi-connector";
 		type = "a";

@@ -106,6 +118,24 @@ vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
 	};
 };
 
+&dp0 {
+	pinctrl-0 = <&dp0m0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&dp0_in {
+	dp0_in_vp2: endpoint {
+		remote-endpoint = <&vp2_out_dp0>;
+	};
+};
+
+&dp0_out {
+	dp0_out_con: endpoint {
+		remote-endpoint = <&dp_con_in>;
+	};
+};
+
 &gpu {
 	mali-supply = <&vdd_gpu_s0>;
 	sram-supply = <&vdd_gpu_mem_s0>;

@@ -916,6 +946,17 @@ &usb_host1_xhci {
 };
 
 &vop {
+	/*
+	 * If no dedicated PLL was specified, the GPLL would be automatically
+	 * assigned as the PLL source for dclk_vop2. As the frequency of GPLL
+	 * is 1188 MHz, we can only get typical clock frequencies such as
+	 * 74.25MHz, 148.5MHz, 297MHz, 594MHz.
+	 *
+	 * So here we set the parent clock of VP2 to V0PLL so that we can get
+	 * any frequency.
+	 */
+	assigned-clocks = <&cru DCLK_VOP2_SRC>;
+	assigned-clock-parents = <&cru PLL_V0PLL>;
 	status = "okay";
 };

@@ -929,3 +970,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
 		remote-endpoint = <&hdmi0_in_vp0>;
 	};
 };
+
+&vp2 {
+	vp2_out_dp0: endpoint@a {
+		reg = <ROCKCHIP_VOP2_EP_DP0>;
+		remote-endpoint = <&dp0_in_vp2>;
+	};
+};

Signature · 7 lines

2.49.0


_______________________________________________
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Quentin Schulz

2025-09-18 10:39 UTC #1 lore raw

Hi Chaoyi Chen,

Quoted 70 lines · Chaoyi Chen

From: Chaoyi Chen <[email protected]>

The rk3588 evb2 board has a full size DisplayPort connector, enable for it.

Signed-off-by Chaoyi Chen <[email protected]>

---

Changes in v2:

- Link to V1: https://lore.kernel.org/all/[email protected]/
- Fix invalid DP connector type
- Add more comment about dclk_vp2 parent clock

  .../boot/dts/rockchip/rk3588-evb2-v10.dts     | 48 +++++++++++++++++++
  1 file changed, 48 insertions(+)

arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts +31 -0

index 91fe810d38d8..60ba6ac55b23 100644
@@ -25,6 +25,18 @@ chosen {
  		stdout-path = "serial2:1500000n8";
  	};
 
+	dp-con {
+		compatible = "dp-connector";
+		label = "DP OUT";
+		type = "full-size";
+
+		port {
+			dp_con_in: endpoint {
+				remote-endpoint = <&dp0_out_con>;
+			};
+		};
+	};
+
  	hdmi-con {
  		compatible = "hdmi-connector";
  		type = "a";

@@ -106,6 +118,24 @@ vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
  	};
  };
 
+&dp0 {
+	pinctrl-0 = <&dp0m0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&dp0_in {
+	dp0_in_vp2: endpoint {
+		remote-endpoint = <&vp2_out_dp0>;
+	};
+};
+
+&dp0_out {
+	dp0_out_con: endpoint {
+		remote-endpoint = <&dp_con_in>;
+	};
+};
+
  &gpu {
  	mali-supply = <&vdd_gpu_s0>;
  	sram-supply = <&vdd_gpu_mem_s0>;

@@ -916,6 +946,17 @@ &usb_host1_xhci {
  };
 
  &vop {
+	/*

arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts &usb_host1_xhci { · line 959

Quoted 10 lines

arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts +10 -0

+	 * If no dedicated PLL was specified, the GPLL would be automatically
+	 * assigned as the PLL source for dclk_vop2. As the frequency of GPLL
+	 * is 1188 MHz, we can only get typical clock frequencies such as
+	 * 74.25MHz, 148.5MHz, 297MHz, 594MHz.
+	 *
+	 * So here we set the parent clock of VP2 to V0PLL so that we can get
+	 * any frequency.
+	 */
+	assigned-clocks = <&cru DCLK_VOP2_SRC>;
+	assigned-clock-parents = <&cru PLL_V0PLL>;

Are those board-specific? Considering the VOP and DP/HDMI/... controllers/PHYs are all internal to the SoC, would it make sense to have those specified in the SoC DTSI? I'm not familiar with the video output stack so maybe it doesn't apply here or is a bad idea, so I'm not actually asking for a change here, just asking a question :)

Cheers,
Quentin

Chaoyi Chen

2025-09-18 11:29 UTC #2 lore raw

Hi Quentin,

Quoted 74 lines · Quentin Schulz

Hi Chaoyi Chen,

Quoted 71 lines · Chaoyi Chen

From: Chaoyi Chen <[email protected]>

The rk3588 evb2 board has a full size DisplayPort connector, enable for it.

Signed-off-by Chaoyi Chen <[email protected]>

---

Changes in v2:

- Link to V1: https://lore.kernel.org/all/[email protected]/
- Fix invalid DP connector type
- Add more comment about dclk_vp2 parent clock

.../boot/dts/rockchip/rk3588-evb2-v10.dts | 48 +++++++++++++++++++

  1 file changed, 48 insertions(+)

arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts +33 -0

index 91fe810d38d8..60ba6ac55b23 100644
@@ -25,6 +25,18 @@ chosen {
           stdout-path = "serial2:1500000n8";
       };
   +    dp-con {
+        compatible = "dp-connector";
+        label = "DP OUT";
+        type = "full-size";
+
+        port {
+            dp_con_in: endpoint {
+                remote-endpoint = <&dp0_out_con>;
+            };
+        };
+    };
+
       hdmi-con {
           compatible = "hdmi-connector";
           type = "a";

@@ -106,6 +118,24 @@ vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
       };
   };
   +&dp0 {
+    pinctrl-0 = <&dp0m0_pins>;
+    pinctrl-names = "default";
+    status = "okay";
+};
+
+&dp0_in {
+    dp0_in_vp2: endpoint {
+        remote-endpoint = <&vp2_out_dp0>;
+    };
+};
+
+&dp0_out {
+    dp0_out_con: endpoint {
+        remote-endpoint = <&dp_con_in>;
+    };
+};
+
   &gpu {
       mali-supply = <&vdd_gpu_s0>;
       sram-supply = <&vdd_gpu_mem_s0>;

@@ -916,6 +946,17 @@ &usb_host1_xhci {
   };
     &vop {
+    /*
+     * If no dedicated PLL was specified, the GPLL would be automatically
+     * assigned as the PLL source for dclk_vop2. As the frequency of GPLL
+     * is 1188 MHz, we can only get typical clock frequencies such as
+     * 74.25MHz, 148.5MHz, 297MHz, 594MHz.

Quoted 8 lines

arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts &usb_host1_xhci { · line 959
Quoted 6 lines
arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts +6 -0
+     *
+     * So here we set the parent clock of VP2 to V0PLL so that we can get
+     * any frequency.
+     */
+    assigned-clocks = <&cru DCLK_VOP2_SRC>;
+    assigned-clock-parents = <&cru PLL_V0PLL>;
Are those board-specific? Considering the VOP and DP/HDMI/... controllers/PHYs are all internal to the SoC, would it make sense to have those specified in the SoC DTSI? I'm not familiar with the video output stack so maybe it doesn't apply here or is a bad idea, so I'm not actually asking for a change here, just asking a question :)

Yep, they are board-specific. Because the V0PLL may be used for non-display applications.

Quoted 5 lines

Cheers,
Quentin

Signature · 2 lines

Best,
Chaoyi

Heiko Stuebner

maintainer Applied

2025-10-14 18:07 UTC #3 lore raw

In reply to Chaoyi Chen

Quoted 4 lines · Chaoyi Chen

The rk3588 evb2 board has a full size DisplayPort connector, enable for it.

Applied, thanks!

[1/1] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2

      commit: 134fae98cfbabb7e90b1b2d957fb374408061034

Best regards,

Signature · 1 line

Heiko Stuebner <[email protected]>