gpio: renesas: Add support for GPIO and related interrupts in RZ/N1 SoC

Add GPIO controllers (Synosys DesignWare IPs) available in the r9a06g032 (RZ/N1D) SoC.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

Reviewed-by Wolfram Sang <[email protected]>

Tested-by Wolfram Sang <[email protected]>

Add GPIO controllers (Synosys DesignWare IPs) available in the r9a06g032 (RZ/N1D) SoC.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

Reviewed-by Wolfram Sang <[email protected]>

Tested-by Wolfram Sang <[email protected]>

---

Quoted 4 lines · Herve Codina (Schneider Electric)

Add GPIO controllers (Synosys DesignWare IPs) available in the r9a06g032 (RZ/N1D) SoC.

Quoted 4 lines

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

Reviewed-by Wolfram Sang <[email protected]>

Tested-by Wolfram Sang <[email protected]>

---

Reviewed-by Bartosz Golaszewski <[email protected]>

Hi Bartosz,

Quoted 11 lines · On Mon, 22 Sep 2025 16:22:14 +0200 Bartosz Golaszewski <[email protected]> wrote:

Quoted 8 lines · Herve Codina (Schneider Electric)

Add GPIO controllers (Synosys DesignWare IPs) available in the r9a06g032 (RZ/N1D) SoC.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

Reviewed-by Wolfram Sang <[email protected]>

Tested-by Wolfram Sang <[email protected]>

---

Quoted 1 line

Reviewed-by Bartosz Golaszewski <[email protected]>

I have just sent the v4 iteration.

This patch has not been modified in v4.

Can you add your 'Reviewed-by' in the v4 series?

Quoted 18 lines · Herve Codina

Hi Bartosz,

Quoted 12 lines · On Mon, 22 Sep 2025 16:22:14 +0200 Bartosz Golaszewski <[email protected]> wrote:

Quoted 8 lines · Herve Codina (Schneider Electric)

Add GPIO controllers (Synosys DesignWare IPs) available in the r9a06g032 (RZ/N1D) SoC.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

Reviewed-by Wolfram Sang <[email protected]>

Tested-by Wolfram Sang <[email protected]>

---

Reviewed-by Bartosz Golaszewski <[email protected]>

Quoted 6 lines

I have just sent the v4 iteration.

This patch has not been modified in v4.

Can you add your 'Reviewed-by' in the v4 series?

Sure, done.

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

---
 .../soc/renesas/renesas,rzn1-gpioirqmux.yaml  | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml

Quoted 7 lines · Herve Codina (Schneider Electric)

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

Quoted 5 lines

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

---
 .../soc/renesas/renesas,rzn1-gpioirqmux.yaml  | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml  

This is an interrupt controller, please move it to that subdirectory.

Otherwise,

Acked-by Conor Dooley <[email protected]>

Hi Conor,

Quoted 14 lines · On Thu, 18 Sep 2025 16:06:04 +0100 Conor Dooley <[email protected]> wrote:

Quoted 12 lines · Herve Codina (Schneider Electric)

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

---
 .../soc/renesas/renesas,rzn1-gpioirqmux.yaml  | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml  

Quoted 1 line

This is an interrupt controller, please move it to that subdirectory.

Not so sure. It is a nexus node. It routes interrupt signals to the interrupt controller (interrupt-map) but it is not an interrupt controller itself.

I am not sure that it should be moved to the interrupt-controller directory.

Quoted 21 lines · Herve Codina

Hi Conor,

Quoted 15 lines · On Thu, 18 Sep 2025 16:06:04 +0100 Conor Dooley <[email protected]> wrote:

Quoted 4 lines · Herve Codina (Schneider Electric)

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

Quoted 8 lines

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

---
 .../soc/renesas/renesas,rzn1-gpioirqmux.yaml  | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml    

This is an interrupt controller, please move it to that subdirectory.

Quoted 6 lines

Not so sure. It is a nexus node. It routes interrupt signals to the interrupt controller (interrupt-map) but it is not an interrupt controller itself.

I am not sure that it should be moved to the interrupt-controller directory.

Your node name choice disagrees with you!

Quoted 29 lines · On Thu, 18 Sep 2025 16:26:59 +0100 Conor Dooley <[email protected]> wrote:

Quoted 27 lines · Herve Codina

Hi Conor,

Quoted 8 lines · On Thu, 18 Sep 2025 16:06:04 +0100 Conor Dooley <[email protected]> wrote:

Quoted 7 lines · Herve Codina (Schneider Electric)

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

Quoted 7 lines

Quoted 5 lines

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

---
 .../soc/renesas/renesas,rzn1-gpioirqmux.yaml  | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml    

This is an interrupt controller, please move it to that subdirectory.

Not so sure. It is a nexus node. It routes interrupt signals to the interrupt controller (interrupt-map) but it is not an interrupt controller itself.

I am not sure that it should be moved to the interrupt-controller directory.

Quoted 1 line

Your node name choice disagrees with you!

Oups, you're right, my bad.

What do you think if I change the node name from "interrupt-controller" to "interrupt-mux" in the next iteration?

Quoted 32 lines · Herve Codina

Quoted 29 lines · On Thu, 18 Sep 2025 16:26:59 +0100 Conor Dooley <[email protected]> wrote:

Quoted 27 lines · Herve Codina

Hi Conor,

Quoted 8 lines · On Thu, 18 Sep 2025 16:06:04 +0100 Conor Dooley <[email protected]> wrote:

Quoted 7 lines · Herve Codina (Schneider Electric)

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

Quoted 7 lines

Quoted 5 lines

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

---
 .../soc/renesas/renesas,rzn1-gpioirqmux.yaml  | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml

This is an interrupt controller, please move it to that subdirectory.

Not so sure. It is a nexus node. It routes interrupt signals to the interrupt controller (interrupt-map) but it is not an interrupt controller itself.

I am not sure that it should be moved to the interrupt-controller directory.

Quoted 6 lines

Quoted 1 line

Your node name choice disagrees with you!

Oups, you're right, my bad.

What do you think if I change the node name from "interrupt-controller" to "interrupt-mux" in the next iteration?

I guess, sure.

Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml line 44

Quoted 6 lines

Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml new file +6 -0

+  interrupt-map:
+    description:
+      Specifies the mapping from external GPIO interrupt lines to the output
+      interrupts. The array items have to be ordered with the first item
+      related to the output line 0 (IRQ 103), the next one to the output line 1
+      (IRQ 104) and so on up to the output line 8 (IRQ 110).  

maxItems 8?

Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml line 82

Quoted 12 lines

Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml new file +11 -0

+        /*
+         * The child interrupt number is computed using the following formula:
+         *    gpio_bank * 32 + gpio_number
+         *
+         * with:
+         *    - gpio_bank: The GPIO bank number
+         *          - 0 for GPIO0A,
+         *          - 1 for GPIO1A,
+         *          - 2 for GPIO2A
+         *    - gpio_number: Number of the gpio in the bank (0..31)
+         */  

I wonder if this comment wouldn't be better in the interrupt-map description above?

drivers/soc/renesas/rzn1_irqmux.c new file +18 -0

+		}
+
+		writel(imap_item.child_imap[0], regs + index);
+		index++;
+	}
+
+	return 0;
+}
+
+static int irqmux_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	u32 __iomem *regs;
+	int nr_irqs;
+	int ret;
+
+	regs = devm_platform_ioremap_resource(pdev, 0);

Hi Herve,

drivers/soc/renesas/rzn1_irqmux.c line 17

Quoted 3 lines

drivers/soc/renesas/rzn1_irqmux.c new file +3 -0

+#define IRQMUX_MAX_IRQS 8
+
+static int irqmux_setup(struct device *dev, struct device_node *np, u32 __iomem *regs)  

The whole driver would benefit from a 'rzn1_irqmux' instead of 'irqmux' prefix, I'd say.

drivers/soc/renesas/rzn1_irqmux.c line 51

Quoted 11 lines

drivers/soc/renesas/rzn1_irqmux.c new file +10 -0

+	for_each_of_imap_item(&imap_parser, &imap_item) {
+		/*
+		 * The child #address-cells is 0 (already checked). The first
+		 * value in imap item is the src hwirq.
+		 *
+		 * imap items matches 1:1 the interrupt lines that could
+		 * be configured by registers (same order, same number).
+		 * Configure the related register with the src hwirq retrieved
+		 * from the interrupt-map.
+		 */  

I haven't looked into the above for_each_of_imap_item-helper. But wouldn't it be possibleto retrieve the GIC_SPI number as well and use the correct register based on that? That would remove the need of an already sorted interrupt-map.

drivers/soc/renesas/rzn1_irqmux.c line 55

Quoted 5 lines

drivers/soc/renesas/rzn1_irqmux.c new file +4 -0

+		if (index > IRQMUX_MAX_IRQS) {
+			of_node_put(imap_item.parent_args.np);
+			dev_err(dev, "too much items in interrupt-map\n");
+			return -EINVAL;  

-E2BIG? With such a unique errno, we could even drop the dev_err.

Quoted 23 lines

drivers/soc/renesas/rzn1_irqmux.c new file +22 -0

+		}
+
+		writel(imap_item.child_imap[0], regs + index);
+		index++;
+	}
+
+	return 0;
+}
+
+static int irqmux_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	u32 __iomem *regs;
+	int nr_irqs;
+	int ret;
+
+	regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	nr_irqs = of_irq_count(np);

drivers/soc/renesas/rzn1_irqmux.c line 83

Quoted 6 lines

drivers/soc/renesas/rzn1_irqmux.c new file +6 -0

+	if (nr_irqs < 0)
+		return nr_irqs;
+
+	if (nr_irqs > IRQMUX_MAX_IRQS) {
+		dev_err(dev, "too many output interrupts\n");
+		return -ENOENT;  

-E2BIG? Wait, isn't this the same check twice?

Rob asked to use only interrupt-map and use directly the interrupt-map index as the hardware index:
https://lore.kernel.org/lkml/[email protected]/

Quoted 3 lines

Rob asked to use only interrupt-map and use directly the interrupt-map index as the hardware index:
https://lore.kernel.org/lkml/[email protected]/

I agree with that. Currently an interrupt-map entry looks like:

interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

And the number after GIC_SPI determines the index register, no? Can't we simply say 'index = <SPI_nr_from_dt> - 103' incl. some sanity checks?

kind of:
static u8 reg_index[8] = {103, 104, 105, ... , 110};

Base on GIC IRQ number retrieve from the interrupt-map item, we search for the index in reg_index that match this number. The index found is the index used to access the register.

What do you think about this?

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

drivers/soc/renesas/rzn1_irqmux.c line 97

Quoted 6 lines

drivers/soc/renesas/rzn1_irqmux.c new file +5 -0

+static const struct of_device_id irqmux_of_match[] = {
+       { .compatible = "renesas,rzn1-gpioirqmux", },
+       { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, irq_mux_of_match);

                           ^^^^^^^^^^^^^^^^
                           irqmux_of_match

Interestingly, this built fine for me before, presumably until commit 5ab23c7923a1d2ae ("modpost: Create modalias for builtin modules") in v6.18-rc1.

Quoted 8 lines

drivers/soc/renesas/rzn1_irqmux.c line 97

Quoted 5 lines

drivers/soc/renesas/rzn1_irqmux.c new file +5 -0

+static const struct of_device_id irqmux_of_match[] = {
+       { .compatible = "renesas,rzn1-gpioirqmux", },
+       { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, irq_mux_of_match);

                           ^^^^^^^^^^^^^^^^
                           irqmux_of_match

Quoted 3 lines

Interestingly, this built fine for me before, presumably until commit 5ab23c7923a1d2ae ("modpost: Create modalias for builtin modules") in v6.18-rc1.

This should be fixed in v4 already as a side effect of my request for a better namespace prefix.

arch/arm/boot/dts/renesas/r9a06g032.dtsi +4 -0

+			/*
+			 * interrupt-map has to be updated according to GPIO
+			 * usage. The order has to be kept. Only the src irq
+			 * (0 field) has to be updated with the needed GPIO

Quoted 9 lines

arch/arm/boot/dts/renesas/r9a06g032.dtsi +9 -0

+			/*
+			 * interrupt-map has to be updated according to GPIO
+			 * usage. The order has to be kept. Only the src irq
+			 * (0 field) has to be updated with the needed GPIO
+			 * interrupt number.
+			 */
+			interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+					<0 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+					<0 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

arch/arm/boot/dts/renesas/r9a06g032.dtsi gpio2b: gpio-port@1 { · line 667

Quoted 5 lines

arch/arm/boot/dts/renesas/r9a06g032.dtsi +5 -0

+					<0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+					<0 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+					<0 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					<0 &gic GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+					<0 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;  

I'd think this should be dropped from the include and added in the board file instead. I did this with my board and it works fine.

'interrupt-map' is a required property. If the board doesn't use any interrupt GPIO, its dts has no reason to set the interrupt-map.

Quoted 2 lines

'interrupt-map' is a required property. If the board doesn't use any interrupt GPIO, its dts has no reason to set the interrupt-map.

Why is 'interrupt-map' then a required property? Can we drop it from the requirements?

Quoted 6 lines · On Fri, 19 Sep 2025 16:41:05 +0200 Wolfram Sang…

Quoted 2 lines

'interrupt-map' is a required property. If the board doesn't use any interrupt GPIO, its dts has no reason to set the interrupt-map.

Why is 'interrupt-map' then a required property? Can we drop it from the requirements?

I need to check in details but 'interrupt-map' should be kept required. Indeed, irq-mux needs this property to work. It is not an optional one.

I need to look at the 'make CHECK_DTBS=y' behavior when required property is missing in a not enabled node (node with status = "disabled").

Also, got some:
Warning (interrupts_property): /soc/interrupt-controller@51000480: Missing interrupt-controller or interrupt-map property

This could be due to the presence of #interrupt-cells or the node name (not sure). As I need to rename the node (Conor's comment), I will see if the warning disappear. If the warning is due to #interrupt-cells, I don't think that removing #interrupt-cells is the right solution to avoid the warning.

That's said, I need to perform some local tries. I will keep you informed.

/*
* interrupt-map has to be updated according to GPIO
* usage. The src irq (0 field) has to be updated with
* the needed GPIO interrupt number.
* More items can be added (up to 8). Those items must
* define a GIC SPI interrupt in the range 103 to 110. */
interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

Hi,

This series adds support for GPIO and GPIO IRQ mux available in the RZ/N1 SoCs.

The first patches in this series are related to a new helper introduced to parse an interrupt-map property.
- patch 1: Introduce the helper (for_each_of_imap_item)
- patch 2: Add a unittest for the new helper
- patch 3 and 4: convert existing drivers to use this new helper

Patch 4 will conflicts with commit 40c26230a1bf ("irqchip: Use int type to store negative error codes") available in linux-next.

Patch 5 adds support for GPIO (device-tree description)

The last patches (6, 7 and 8) of the series are related to GPIO interrupts and GPIO IRQ multiplexer.

In the RZ/N1 SoCs, GPIO interrupts are wired to a GPIO IRQ multiplexer.

This multiplexer does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

One upstreaming attempt have been done previously by Phil Edworthy [1] but the series has never been applied.

Based on my understanding, I have fully reworked the driver proposed by Phil and removed the IRQ domain. Indeed, the device doesn't handle interrupts. It just routes signals.

Also, as an interrupt-map property is used, the driver cannot be involved as an interrupt controller itself. It is a nexus node.

With that in mind,
- Patch 6 is related to the irq-mux binding.

- Patch 7 introduces the irq-mux driver.
This driver uses the 'for_each_of_imap_item' helper introduced previously. Indeed, the lines routing is defined by the interrupt-map property and the driver needs to set registers to apply this routing.

- Patch 8 is the RZ/N1 device-tree description update to have the support for the GPIO interrupts.

[1] https://lore.kernel.org/all/[email protected]/

Best regards,
Hervé

Quoted 48 lines · Herve Codina (Schneider Electric)

Hi,

This series adds support for GPIO and GPIO IRQ mux available in the RZ/N1 SoCs.

The first patches in this series are related to a new helper introduced to parse an interrupt-map property.
- patch 1: Introduce the helper (for_each_of_imap_item)
- patch 2: Add a unittest for the new helper
- patch 3 and 4: convert existing drivers to use this new helper

Patch 4 will conflicts with commit 40c26230a1bf ("irqchip: Use int type to store negative error codes") available in linux-next.

Patch 5 adds support for GPIO (device-tree description)

The last patches (6, 7 and 8) of the series are related to GPIO interrupts and GPIO IRQ multiplexer.

In the RZ/N1 SoCs, GPIO interrupts are wired to a GPIO IRQ multiplexer.

This multiplexer does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

One upstreaming attempt have been done previously by Phil Edworthy [1] but the series has never been applied.

Based on my understanding, I have fully reworked the driver proposed by Phil and removed the IRQ domain. Indeed, the device doesn't handle interrupts. It just routes signals.

Also, as an interrupt-map property is used, the driver cannot be involved as an interrupt controller itself. It is a nexus node.

With that in mind,
- Patch 6 is related to the irq-mux binding.

- Patch 7 introduces the irq-mux driver.
This driver uses the 'for_each_of_imap_item' helper introduced previously. Indeed, the lines routing is defined by the interrupt-map property and the driver needs to set registers to apply this routing.

- Patch 8 is the RZ/N1 device-tree description update to have the support for the GPIO interrupts.

[1] https://lore.kernel.org/all/[email protected]/

Quoted 2 lines

Best regards,
Hervé

This whole thing is super interesting to me. I have a gpio irq mux of my own with a driver that is massively more complex than what you have here (it's a full on irqchip driver). I'm definitely gonna have to see if I can ape what you have done here and simplify what I have.

This series adds support for GPIO and GPIO IRQ mux available in the RZ/N1 SoCs.

Quoted 3 lines

This series adds support for GPIO and GPIO IRQ mux available in the RZ/N1 SoCs.

I want to test this series today. From a glimpse, I might have some comments, so please wait a little before resending.

Quoted 6 lines · Wolfram Sang

Quoted 3 lines

This series adds support for GPIO and GPIO IRQ mux available in the RZ/N1 SoCs.

I want to test this series today. From a glimpse, I might have some comments, so please wait a little before resending.

Despite the comments, the series works fine, so:

Tested-by Wolfram Sang <[email protected]>

Maybe I can test patch 4 later today on my RZ/A1-Genmai.