Skip to contentSkip to conversation

Add Agilex5 AXI DMA support

PATCH Superseded Khairul Anuar Romli 3 participants 6 messages Nov 20, 2025 – Nov 26, 2025

Subsystems (3)

v1 of 5 Superseded Latest is v5 →

lore
Share & tools
lore
#0 lore raw

cover Add Agilex5 AXI DMA support

This series introduces support for Agilex5 SoC in the Synopsys DesignWare AXI DMA binding and updates the device tree to use the platform-specific compatible string.

The Agilex5 only has 40-bit DMA addressable bit instead of 64-bit. Hence, this specific addition will enable driver to handle this limitation.

---
Notes:
This patch series is applied on socfpga maintainer's tree
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19

This changes is validated on:
- intel/socfpga_agilex5_socdk.dtb
- snps,dw-axi-dmac.yaml
- snps,dw-axi-dmac.yaml intel/socfpga_agilex5_socdk.dtb
---
Khairul Anuar Romli (2):
dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5
arm64: dts: agilex5: Use platform-specific compatible for AXI DMA

 .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml  | 14 +++++++++-----
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi     |  6 ++++--
 2 files changed, 13 insertions(+), 7 deletions(-)
Signature · 1 line
2.43.7
#1 lore raw

PATCH 1/2 dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5

The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this will cause address truncation and translation faults. Hence introducing "altr,agilex5-axi-dma" to enable platform specific configuration to configure the dma addressable bit mask.

Add a fallback capability for the compatible property to allow driver to probe and initialize with a newly added compatible string without requiring additional entry in the driver.

---
 .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml  | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +9 -5
index a393a33c8908..db89ebf2b006 100644
@@ -17,11 +17,15 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - snps,axi-dma-1.01a
-      - intel,kmb-axi-dma
-      - starfive,jh7110-axi-dma
-      - starfive,jh8100-axi-dma
+    oneOf:
+      - enum:
+          - snps,axi-dma-1.01a
+          - intel,kmb-axi-dma
+          - starfive,jh7110-axi-dma
+          - starfive,jh8100-axi-dma
+      - items:
+          - const: altr,agilex5-axi-dma
+          - const: snps,axi-dma-1.01a
 
   reg:
     minItems: 1
Signature · 1 line
2.43.7
maintainer
#2 lore raw

Re: [PATCH 1/2] dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5

Quoted 4 lines · Khairul Anuar Romli

The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this will cause address truncation and translation faults. Hence introducing "altr,agilex5-axi-dma" to enable platform specific configuration to configure the dma addressable bit mask.

That's likely a bus limitation, not an IP limitation. So that should be handled with dma-ranges.

However, adding a specific compatible is perfectly fine.

Quoted 38 lines

Add a fallback capability for the compatible property to allow driver to probe and initialize with a newly added compatible string without requiring additional entry in the driver.

---
 .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml  | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +9 -5
index a393a33c8908..db89ebf2b006 100644
@@ -17,11 +17,15 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - snps,axi-dma-1.01a
-      - intel,kmb-axi-dma
-      - starfive,jh7110-axi-dma
-      - starfive,jh8100-axi-dma
+    oneOf:
+      - enum:
+          - snps,axi-dma-1.01a
+          - intel,kmb-axi-dma
+          - starfive,jh7110-axi-dma
+          - starfive,jh8100-axi-dma
+      - items:
+          - const: altr,agilex5-axi-dma
+          - const: snps,axi-dma-1.01a
 
   reg:
     minItems: 1
Signature · 1 line
2.43.7
#3 lore raw

Re: [PATCH 1/2] dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5

Quoted 11 lines · Rob Herring
Quoted 4 lines · Khairul Anuar Romli

The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this will cause address truncation and translation faults. Hence introducing "altr,agilex5-axi-dma" to enable platform specific configuration to configure the dma addressable bit mask.

That's likely a bus limitation, not an IP limitation. So that should be handled with dma-ranges.

However, adding a specific compatible is perfectly fine.

Would it be okay if I rephrase and send the next version with a correction in the commit message body as your comment in this version?

Thanks.

Regards,
Khairul

Quoted 38 lines
Quoted 38 lines

Add a fallback capability for the compatible property to allow driver to probe and initialize with a newly added compatible string without requiring additional entry in the driver.

---
  .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml  | 14 +++++++++-----
  1 file changed, 9 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +9 -5
index a393a33c8908..db89ebf2b006 100644
@@ -17,11 +17,15 @@ allOf:
 
  properties:
    compatible:
-    enum:
-      - snps,axi-dma-1.01a
-      - intel,kmb-axi-dma
-      - starfive,jh7110-axi-dma
-      - starfive,jh8100-axi-dma
+    oneOf:
+      - enum:
+          - snps,axi-dma-1.01a
+          - intel,kmb-axi-dma
+          - starfive,jh7110-axi-dma
+          - starfive,jh8100-axi-dma
+      - items:
+          - const: altr,agilex5-axi-dma
+          - const: snps,axi-dma-1.01a
 
    reg:
      minItems: 1
Signature · 1 line
2.43.7
#4 lore raw

Re: [PATCH 1/2] dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5

Quoted 7 lines · Khairul Anuar
Quoted 6 lines · Rob Herring
Quoted 4 lines · Khairul Anuar Romli

The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this will cause address truncation and translation faults. Hence introducing "altr,agilex5-axi-dma" to enable platform specific configuration to configure the dma addressable bit mask.

Quoted 7 lines
Quoted 5 lines

That's likely a bus limitation, not an IP limitation. So that should be handled with dma-ranges.

However, adding a specific compatible is perfectly fine.

Would it be okay if I rephrase and send the next version with a correction in the commit message body as your comment in this version?

Yes and your DTS patch might need changes - include proper dma-ranges.

I also do not see how separate compatible without any driver change solved your case. That's a no-op patch from Linux driver point of view.

See also submitting patches in DT dir about the process how patches are grouped together.

Best regards,
Krzysztof

#5 lore raw

PATCH 2/2 arm64: dts: agilex5: Use platform-specific compatible for AXI DMA

In reply to Khairul Anuar Romli

Update the compatible string for the DMA controller nodes in the Agilex5 device tree from the generic "snps,axi-dma-1.01a" to the platform-specific "altr,agilex5-axi-dma". Add fallback capability to ensure driver is able to initialize properly.

This change enables the use of platform-specific features and constraints in the driver, such as setting a 40-bit DMA addressable mask, which is required for Agilex5. It also aligns with the updated device tree bindings and driver support for this compatible string.

---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +4 -2
index a5c2025a616e..ef33f27b1a4d 100644
@@ -324,7 +324,8 @@ ocram: sram@0 {
 		};
 
 		dmac0: dma-controller@10db0000 {
-			compatible = "snps,axi-dma-1.01a";
+			compatible = "altr,agilex5-axi-dma",
+				     "snps,axi-dma-1.01a";
 			reg = <0x10db0000 0x500>;
 			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
 				 <&clkmgr AGILEX5_L4_MP_CLK>;
@@ -342,7 +343,8 @@ dmac0: dma-controller@10db0000 {
 		};
 
 		dmac1: dma-controller@10dc0000 {
-			compatible = "snps,axi-dma-1.01a";
+			compatible = "altr,agilex5-axi-dma",
+				     "snps,axi-dma-1.01a";
 			reg = <0x10dc0000 0x500>;
 			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
 				 <&clkmgr AGILEX5_L4_MP_CLK>;
Signature · 1 line
2.43.7