drm/msm: add PERFCTR_CNTL to ifpc_reglist

PATCH New Anna Maniscalco 1 participant 1 message Nov 27, 2025

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Stable branch DRM drivers Arm Qualcomm mailing list DRM driver for Qualcomm display hardware +1 more subsystems

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Anna Maniscalco

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2025-11-27 18:22 UTC #0 lore raw

PATCH v3 1/1 drm/msm: add PERFCTR_CNTL to ifpc_reglist

Previously this register would become 0 after IFPC took place which broke all usages of counters.

Fixes a6a0157cc68e ("drm/msm/a6xx: Enable IFPC on Adreno X1-85")

Cc [email protected]

Signed-off-by Anna Maniscalco <[email protected]>

Reviewed-by Akhil P Oommen <[email protected]>

Reviewed-by Dmitry Baryshkov <[email protected]>

---
Changes in v3:
- Added missing Cc: stable to commit
- Collected Rb tags
- Link to v2: https://lore.kernel.org/r/[email protected]

Changes in v2:
- Added Fixes tag
- Link to v1: https://lore.kernel.org/r/[email protected]

---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 +
 1 file changed, 1 insertion(+)

drivers/gpu/drm/msm/adreno/a6xx_catalog.c +1 -0

index 29107b362346..b731491dc522 100644
@@ -1392,6 +1392,7 @@ static const u32 a750_ifpc_reglist_regs[] = {
 	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
 	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
 	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
+	REG_A6XX_RBBM_PERFCTR_CNTL,
 	REG_A6XX_TPL1_NC_MODE_CNTL,
 	REG_A6XX_SP_NC_MODE_CNTL,
 	REG_A6XX_CP_DBG_ECO_CNTL,

---
base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530
change-id: 20251126-ifpc_counters-e8d53fa3252e

Best regards,

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Anna Maniscalco <[email protected]>