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drm/msm: add PERFCTR_CNTL to ifpc_reglist

PATCH Superseded Anna Maniscalco 4 participants 4 messages Nov 26, 2025

Subsystems (5)
Stable branch DRM drivers Arm Qualcomm mailing list DRM driver for Qualcomm display hardware +1 more subsystems

v2 of 3 Superseded Latest is v3 →

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Anna Maniscalco

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#0 lore raw

PATCH v2 1/1 drm/msm: add PERFCTR_CNTL to ifpc_reglist

Previously this register would become 0 after IFPC took place which broke all usages of counters.

Fixes a6a0157cc68e ("drm/msm/a6xx: Enable IFPC on Adreno X1-85")
Signed-off-by Anna Maniscalco <[email protected]>

---
Changes in v2:
- Added Fixes tag
- Link to v1: https://lore.kernel.org/r/[email protected]

---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 +
 1 file changed, 1 insertion(+)
drivers/gpu/drm/msm/adreno/a6xx_catalog.c +1 -0
index 29107b362346..b731491dc522 100644
@@ -1392,6 +1392,7 @@ static const u32 a750_ifpc_reglist_regs[] = {
 	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
 	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
 	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
+	REG_A6XX_RBBM_PERFCTR_CNTL,
 	REG_A6XX_TPL1_NC_MODE_CNTL,
 	REG_A6XX_SP_NC_MODE_CNTL,
 	REG_A6XX_CP_DBG_ECO_CNTL,

---
base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530
change-id: 20251126-ifpc_counters-e8d53fa3252e

Best regards,

Signature · 1 line
Anna Maniscalco <[email protected]>
build bot
#1 lore raw
FYI: kernel test robot notices the stable kernel rule is not satisfied.

Hi,

Thanks for your patch.

FYI: kernel test robot notices the stable kernel rule is not satisfied.

The check is based on https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html#option-1

Rule: add the tag "Cc: [email protected]" in the sign-off area to have the patch automatically included in the stable tree.
Subject: [PATCH v2] drm/msm: add PERFCTR_CNTL to ifpc_reglist

Link https://lore.kernel.org/stable/20251126-ifpc_counters-v2-1-b798bc433eff%40gmail.com open here
Signature · 2 lines
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
reviewer Reviewed-by on v2 1/1
#2 lore raw
In reply to Anna Maniscalco
Quoted 5 lines · Anna Maniscalco

Previously this register would become 0 after IFPC took place which broke all usages of counters.

Fixes a6a0157cc68e ("drm/msm/a6xx: Enable IFPC on Adreno X1-85")
Signed-off-by Anna Maniscalco <[email protected]>
Reviewed-by Akhil P Oommen <[email protected]>

-Akhil

Quoted 26 lines

---
Changes in v2:
- Added Fixes tag
- Link to v1: https://lore.kernel.org/r/[email protected]

---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 +
 1 file changed, 1 insertion(+)
drivers/gpu/drm/msm/adreno/a6xx_catalog.c +1 -1
index 29107b362346..b731491dc522 100644
@@ -1392,6 +1392,7 @@ static const u32 a750_ifpc_reglist_regs[] = {
 	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
 	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
 	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
+	REG_A6XX_RBBM_PERFCTR_CNTL,
 	REG_A6XX_TPL1_NC_MODE_CNTL,
 	REG_A6XX_SP_NC_MODE_CNTL,
 	REG_A6XX_CP_DBG_ECO_CNTL,
 
---

base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530
change-id: 20251126-ifpc_counters-e8d53fa3252e

Best regards,

Reviewed-by on v2 1/1
#3 lore raw
In reply to Anna Maniscalco
Quoted 8 lines · Anna Maniscalco

Previously this register would become 0 after IFPC took place which broke all usages of counters.

Fixes a6a0157cc68e ("drm/msm/a6xx: Enable IFPC on Adreno X1-85")
Signed-off-by Anna Maniscalco <[email protected]>

---
Changes in v2:
- Added Fixes tag

Cc [email protected]
Reviewed-by Dmitry Baryshkov <[email protected]>
Quoted 5 lines

- Link to v1: https://lore.kernel.org/r/[email protected]

---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 +
 1 file changed, 1 insertion(+)
Signature · 2 lines
With best wishes
Dmitry