Add Agilex5 AXI DMA support

This series introduces support for Agilex5 SoC in the Synopsys DesignWare AXI DMA binding and updates the device tree to use the platform-specific compatible string.

The Agilex5 only has 40-bit DMA addressable bit instead of 64-bit. Hence, this specific addition will enable driver to handle this limitation.

---
Notes:
This patch series is applied on socfpga maintainer's tree
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19

Changes in v2:
- Add dma-ranges property.
- Add address-cells and size-cells due to warning when dma-ranges is define without address-cells and size-cells present. Also prevent kernel panic if address-cells and size-cells are not defined.
- Add driver support to handle defined properties and set the DMA BIT MASK according to value from DT.
- Rename "arm64: dts: agilex5: Use platform-specific compatible for AXI DMA" to "arm64: dts: intel: agilex5: Add dma-ranges and address cells to dma node"

This changes is validated on:
- intel/socfpga_agilex5_socdk.dtb
- snps,dw-axi-dmac.yaml
- snps,dw-axi-dmac.yaml intel/socfpga_agilex5_socdk.dtb
- Agilex5 devkit
---
Khairul Anuar Romli (4):
dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5
dt-bindings: dma: snps,dw-axi-dmac: Add #address-cells and #size-cells
arm64: dts: intel: agilex5: Add dma-ranges and address cells to dma
node
dma: dw-axi-dmac: Add support for Agilex5 and dynamic bus width

 .../bindings/dma/snps,dw-axi-dmac.yaml        | 33 ++++++++--
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 +++-
 .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 63 ++++++++++++++++++-
 drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  1 +
 4 files changed, 101 insertions(+), 8 deletions(-)

2.43.7

The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this will cause address truncation and translation faults. Hence introducing "altr,agilex5-axi-dma" to enable platform specific configuration to configure the dma addressable bit mask.

Add a fallback capability for the compatible property to allow driver to probe and initialize with a newly added compatible string without requiring additional entry in the driver.

Add dma-ranges to the binding schema to allow specifying DMA address mapping between the controller and its parent bus.

---
Changes in v2:
- Add dma-ranges

---
 .../bindings/dma/snps,dw-axi-dmac.yaml        | 23 +++++++++++++++----
 1 file changed, 18 insertions(+), 5 deletions(-)

index a393a33c8908..1a1800d9b544 100644
@@ -17,11 +17,15 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - snps,axi-dma-1.01a
-      - intel,kmb-axi-dma
-      - starfive,jh7110-axi-dma
-      - starfive,jh8100-axi-dma
+    oneOf:
+      - enum:
+          - snps,axi-dma-1.01a
+          - intel,kmb-axi-dma
+          - starfive,jh7110-axi-dma
+          - starfive,jh8100-axi-dma
+      - items:
+          - const: altr,agilex5-axi-dma
+          - const: snps,axi-dma-1.01a
 
   reg:
     minItems: 1

@@ -104,6 +108,15 @@ properties:
     minimum: 1
     maximum: 256
 
+  dma-ranges:
+    description: |
+      Describe memory addresses translation between the DMA address and the
+      CPU address. Each memory region, is declared with 3-6 32-bit cells
+      parameters:
+        - param 1: device base address
+        - param 2: physical base address
+        - param 3: size of the memory region.
+
 required:
   - compatible
   - reg

2.43.7

Add '#address-cells' and '#size-cells' to resolved the dt-schema build build issue when dma-ranges is presence. Without address-cells and size-cells presence in DT, kernel panic is observed due to of_base driver treats address-cells as two and size-cells as one.

Defining these cells explicitly ensures the binding correctly documents the necessary structure for nodes that describe the DMA-accessible memory space.

The supported enumeration for both properties is [1, 2], accommodating both 32-bit and 64-bit address/size representations.

---
Changes in v2:
- Add address-cells and size-cells patch into the series

---
 .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml      | 10 ++++++++++
 1 file changed, 10 insertions(+)

index 1a1800d9b544..2b542ff9a6cd 100644
@@ -33,6 +33,16 @@ properties:
       - description: Address range of the DMAC registers
       - description: Address range of the DMAC APB registers
 
+  '#address-cells':
+    description: The number of cells used to represent physical base address
+      in the host address space.
+    enum: [1, 2]
+
+  '#size-cells':
+    description: The number of cells used to represent the size of an address
+      range in the host address space.
+    enum: [1, 2]
+
   reg-names:
     items:
       - const: axidma_ctrl_regs

2.43.7

Why are you fixing a problem the previous patch created?

Thinking about this some more, really 'dma-ranges' is supposed to be in a bus node, not the device node. So you should probably move the dma controllers down a level adding another simple-bus node with dma-ranges. Then you only need to add the new compatible.

Update the compatible string for the DMA controller nodes in the Agilex5 device tree from the generic "snps,axi-dma-1.01a" to the platform-specific "altr,agilex5-axi-dma". Add fallback capability to ensure driver is able to initialize properly.

This change enables the use of platform-specific features and constraints in the driver, such as setting a 40-bit DMA addressable mask through dma-ranges, which is required for Agilex5. It also aligns with the updated device tree bindings and driver support for this compatible string.

Address-cells and size-cells are also defined along with dma-ranges to ensure of_base driver does not causing kernel panic during boot up.

---
Changes in v2:
- Rename the from add platform specific to add dma-ranges, address and size cells.
- Define address-cells and size-cells for dmac0 and dmac1
- Add dma-ranges for agilex5 for 40-bit

---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

index 06f98667499b..1983869274e7 100644
@@ -336,8 +336,11 @@ ocram: sram@0 {
 		};
 
 		dmac0: dma-controller@10db0000 {
-			compatible = "snps,axi-dma-1.01a";
+			compatible = "altr,agilex5-axi-dma",
+				     "snps,axi-dma-1.01a";
 			reg = <0x10db0000 0x500>;
+			#address-cells = <1>;
+			#size-cells = <2>;
 			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
 				 <&clkmgr AGILEX5_L4_MP_CLK>;
 			clock-names = "core-clk", "cfgr-clk";

@@ -351,11 +354,15 @@ dmac0: dma-controller@10db0000 {
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;
 			iommus = <&smmu 8>;
+			dma-ranges = <0x00 0x00 0x00000100 0x00000000>;
 		};
 
 		dmac1: dma-controller@10dc0000 {
-			compatible = "snps,axi-dma-1.01a";
+			compatible = "altr,agilex5-axi-dma",
+				     "snps,axi-dma-1.01a";
 			reg = <0x10dc0000 0x500>;
+			#address-cells = <1>;
+			#size-cells = <2>;
 			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
 				 <&clkmgr AGILEX5_L4_MP_CLK>;
 			clock-names = "core-clk", "cfgr-clk";

@@ -369,6 +376,7 @@ dmac1: dma-controller@10dc0000 {
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;
 			iommus = <&smmu 9>;
+			dma-ranges = <0x00 0x00 0x00000100 0x00000000>;
 		};
 
 		rst: rstmgr@10d11000 {

2.43.7

Add device tree compatible string support for the Altera Agilex5 AXI DMA controller.

Introduces logic to parse the "dma-ranges" property and calculate the actual number of addressable bits (bus width) for the DMA engine. This calculated value is then used to set the coherent mask via 'dma_set_mask_and_coherent()', allowing the driver to correctly handle devices with bus widths less than 64 bits. The addressable bits default to 64 if 'dma-ranges' is not specified or cannot be parsed.

Introduce 'addressable_bits' to 'struct axi_dma_chip' to store this value.

---
Changes in v2:
- Add driver implementation to set the DMA BIT MAST to 40 based on dma-ranges defined in DT.
- Add glue for driver and DT.

---
 .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 63 ++++++++++++++++++-
 drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  1 +
 2 files changed, 63 insertions(+), 1 deletion(-)

index b23536645ff7..165481b4dde1 100644
@@ -271,7 +271,9 @@ static void axi_dma_hw_init(struct axi_dma_chip *chip)
 		axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
 		axi_chan_disable(&chip->dw->chan[i]);
 	}
-	ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
+
+	dev_dbg(chip->dev, "Adressable bus width: %u\n", chip->addressable_bits);
+	ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(chip->addressable_bits));
 	if (ret)
 		dev_warn(chip->dev, "Unable to set coherent mask\n");
 }

@@ -1461,13 +1463,23 @@ static int axi_req_irqs(struct platform_device *pdev, struct axi_dma_chip *chip)
 	return 0;
 }
 
+/* Forward declaration (no size required) */
+static const struct of_device_id dw_dma_of_id_table[];
+
 static int dw_probe(struct platform_device *pdev)
 {
 	struct axi_dma_chip *chip;
 	struct dw_axi_dma *dw;
 	struct dw_axi_dma_hcfg *hdata;
 	struct reset_control *resets;
+	const struct of_device_id *match;
 	unsigned int flags;
+	unsigned int addressable_bits = 64;
+	unsigned int len_bytes;
+	unsigned int num_cells;
+	const __be32 *prop;
+	u64 bus_width;
+	u32 *cells;
 	u32 i;
 	int ret;
 

@@ -1483,9 +1495,56 @@ static int dw_probe(struct platform_device *pdev)
 	if (!hdata)
 		return -ENOMEM;
 
+	match = of_match_node(dw_dma_of_id_table, pdev->dev.of_node);
+	if (!match) {
+		dev_err(&pdev->dev, "Unsupported AXI DMA device\n");
+		return -ENODEV;
+	}
+
+	prop = of_get_property(pdev->dev.of_node, "dma-ranges", &len_bytes);
+	if (prop) {
+		num_cells = len_bytes / sizeof(__be32);
+		cells = kcalloc(num_cells, sizeof(*cells), GFP_KERNEL);
+		if (!cells)
+			return -ENOMEM;
+
+		ret = of_property_read_u32(pdev->dev.of_node, "#address-cells", &i);
+		if (ret) {
+			dev_err(&pdev->dev, "missing #address-cells property\n");
+			return ret;
+		}
+
+		ret = of_property_read_u32(pdev->dev.of_node, "#size-cells", &i);
+		if (ret) {
+			dev_err(&pdev->dev, "missing #size-cells property\n");
+			return ret;
+		}
+
+		if (!of_property_read_u32_array(pdev->dev.of_node,
+						"dma-ranges", cells, num_cells)) {
+			dev_dbg(&pdev->dev, "dma-ranges numbe of cells: %u\n", num_cells);
+			// Check if size-cells is 2 cells.
+			if (i == 2 && num_cells > 3) {
+				// Combine size cells into 64-bit length
+				dev_dbg(&pdev->dev, "size-cells MSB: %u\n", cells[num_cells - 2]);
+				dev_dbg(&pdev->dev, "size-cells LSB: %u\n", cells[num_cells - 1]);
+				bus_width = ((u64)cells[num_cells - 2] << 32) |
+cells[num_cells - 1];
+			}
+
+			// Count number of bits in bus_width
+			if (bus_width)
+				addressable_bits = fls64(bus_width) - 1;
+
+			dev_dbg(&pdev->dev, "Bus width: %u bits (length: 0x%llx)\n",
+				addressable_bits, bus_width);
+		}
+	}
+
 	chip->dw = dw;
 	chip->dev = &pdev->dev;
 	chip->dw->hdata = hdata;
+	chip->addressable_bits = addressable_bits;
 
 	chip->regs = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(chip->regs))

@@ -1669,6 +1728,8 @@ static const struct of_device_id dw_dma_of_id_table[] = {
 	}, {
 		.compatible = "starfive,jh8100-axi-dma",
 		.data = (void *)AXI_DMA_FLAG_HAS_RESETS,
+	}, {
+		.compatible = "altr,agilex5-axi-dma"
 	},
 	{}
 };

index b842e6a8d90d..f8152f8b3798 100644
@@ -71,6 +71,7 @@ struct axi_dma_chip {
 	struct clk		*core_clk;
 	struct clk		*cfgr_clk;
 	struct dw_axi_dma	*dw;
+	u32			addressable_bits;
 };
 
 /* LLI == Linked List Item */

2.43.7