Add support for Allwinner PWM on D1/T113s/R329 SoCs

Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller which is different from the previous pwm-sun4i.

The D1 and T113 are identical in terms of peripherals, they differ only in the architecture of the CPU core, and even share the majority of their DT. Because of that, using the same compatible makes sense.
The R329 is a different SoC though, and should have a different compatible string added, especially as there is a difference in the number of channels.

D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one).

Add a device tree binding for them.

Signed-off-by Aleksandr Shubin <[email protected]>

---
 .../bindings/pwm/allwinner,sun20i-d1-pwm.yaml | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-d1-pwm.yaml

Allwinner's D1, T113-S3 and R329 SoCs have a quite different PWM controllers with ones supported by pwm-sun4i driver.

This patch adds a PWM controller driver for Allwinner's D1, T113-S3 and R329 SoCs. The main difference between these SoCs is the number of channels defined by the DT property.

Co-developed-by Brandon Cheo Fusi <[email protected]>

Signed-off-by Brandon Cheo Fusi <[email protected]>

Signed-off-by Aleksandr Shubin <[email protected]>

---
 drivers/pwm/Kconfig     |  10 +
 drivers/pwm/Makefile    |   1 +
 drivers/pwm/pwm-sun8i.c | 393 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 404 insertions(+)
 create mode 100644 drivers/pwm/pwm-sun8i.c

drivers/pwm/Kconfig +10 -0

index 6f3147518376..44d844eba589 100644
@@ -736,6 +736,16 @@ config PWM_SUN4I
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-sun4i.
 
+config PWM_SUN8I
+	tristate "Allwinner D1/T113s/R329 PWM support"
+	depends on ARCH_SUNXI || COMPILE_TEST
+	depends on COMMON_CLK
+	help
+	  Generic PWM framework driver for Allwinner D1/T113s/R329 SoCs.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-sun8i.
+
 config PWM_SUNPLUS
 	tristate "Sunplus PWM support"
 	depends on ARCH_SUNPLUS || COMPILE_TEST

drivers/pwm/Makefile +1 -0

index 0dc0d2b69025..ba2e0ec7fc17 100644
@@ -67,6 +67,7 @@ obj-$(CONFIG_PWM_STM32)		+= pwm-stm32.o
 obj-$(CONFIG_PWM_STM32_LP)	+= pwm-stm32-lp.o
 obj-$(CONFIG_PWM_STMPE)		+= pwm-stmpe.o
 obj-$(CONFIG_PWM_SUN4I)		+= pwm-sun4i.o
+obj-$(CONFIG_PWM_SUN8I)		+= pwm-sun8i.o
 obj-$(CONFIG_PWM_SUNPLUS)	+= pwm-sunplus.o
 obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
 obj-$(CONFIG_PWM_TH1520)	+= pwm_th1520.o

drivers/pwm/pwm-sun8i.c new file +15 -0

new file mode 100644
index 000000000000..6e196f31314b
@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PWM Controller Driver for sunxi platforms (D1, T113-S3 and R329)
+ *
+ * Limitations:
+ * - When the parameters change, the current running period is not completed
+ *   and new settings are applied immediately.
+ * - The PWM output goes to a HIGH-Z state when the channel is disabled.
+ * - Changing the clock configuration (SUN8I_PWM_CLK_CFG)
+ *   may cause a brief output glitch.
+ *
+ * Copyright (c) 2023 Aleksandr Shubin <[email protected]>
+ */
+
+#include <linux/bitfield.h>

drivers/pwm/pwm-sun8i.c new file +10 -0

+#define SUN8I_PWM_CLK_CFG_DIV_M			GENMASK(3, 0)
+#define SUN8I_PWM_CLK_DIV_M_MAX			8
+
+#define SUN8I_PWM_CLK_GATE			0x40
+#define SUN8I_PWM_CLK_GATE_BYPASS(chan)		BIT((chan) + 16)
+#define SUN8I_PWM_CLK_GATE_GATING(chan)		BIT(chan)
+
+#define SUN8I_PWM_ENABLE			0x80
+#define SUN8I_PWM_ENABLE_EN(chan)		BIT(chan)
+

drivers/pwm/pwm-sun8i.c new file +33 -0

+ * This is equivalent to:
+ *
+ * (val >> div_m) ≤ 65536 * (prescale_k + 1) + prescale_k
+ * ⟺ (val >> div_m) ≤ 65537 * prescale_k + 65536
+ * ⟺ (val >> div_m) - 65536 ≤ 65537 * prescale_k
+ * ⟺ ((val >> div_m) - 65536) / 65537 ≤ prescale_k
+ *
+ * As prescale_k is integer, this becomes
+ *
+ * ((val >> div_m) - 65536) // 65537 ≤ prescale_k
+ *
+ * And is minimized at
+ *
+ * ((val >> div_m) - 65536) // 65537
+ *
+ * Now we pick the smallest div_m that satifies prescale_k ≤ 255
+ * (i.e SUN8I_PWM_CTL_PRESCAL_K_MAX),
+ *
+ * ((val >> div_m) - 65536) // 65537 ≤ 255
+ * ⟺ (val >> div_m) - 65536 ≤ 255 * 65537 + 65536
+ * ⟺ val >> div_m ≤ 255 * 65537 + 2 * 65536
+ * ⟺ val >> div_m < (255 * 65537 + 2 * 65536 + 1)
+ * ⟺ div_m = fls((val) / (255 * 65537 + 2 * 65536 + 1))
+ *
+ * Suggested by Uwe Kleine-König
+ */
+#define SUN8I_PWM_MAGIC				(255 * 65537 + 2 * 65536 + 1)
+#define SUN8I_PWM_DIV_CONST			65537
[...]
+static int sun8i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+			    const struct pwm_state *state)
+{
+	struct sun8i_pwm_chip *sun8i_chip = to_sun8i_pwm_chip(chip);
+	u64 bus_rate, hosc_rate, val, ent_cycle, act_cycle;

drivers/pwm/pwm-sun8i.c new file +16 -0

+			clk_gate &= ~SUN8I_PWM_CLK_GATE_GATING(pwm->hwpwm);
+			pwm_en &= ~SUN8I_PWM_ENABLE_EN(pwm->hwpwm);
+			sun8i_pwm_writel(sun8i_chip, pwm_en, SUN8I_PWM_ENABLE);
+			sun8i_pwm_writel(sun8i_chip, clk_gate, SUN8I_PWM_CLK_GATE);
+		}
+		return 0;
+	}
+
+	ctl = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_CTL(pwm->hwpwm));
+	clk_cfg = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_CLK_CFG(pwm->hwpwm / 2));
+	hosc_rate = clk_get_rate(sun8i_chip->clk_hosc);
+	bus_rate = clk_get_rate(sun8i_chip->clk_apb);
+
[...]
+static int sun8i_pwm_probe(struct platform_device *pdev)
+{
+	struct pwm_chip *chip;

D1 and T113s contain a pwm controller with 8 channels. This controller is supported by the sun8i-pwm driver.

Add a device tree node for it.

Signed-off-by Aleksandr Shubin <[email protected]>

---
 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +0 -0

index 63e252b44973..8e38a0d95f5a 100644
@@ -193,6 +193,19 @@ uart3_pb_pins: uart3-pb-pins {
 			};
 		};

arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +3 -0

+			allwinner,npwms = <8>;
+		};
+
 		ccu: clock-controller@2001000 {
 			compatible = "allwinner,sun20i-d1-ccu";
 			reg = <0x2001000 0x1000>;