dt-bindings: arm: mediatek: mediatek,g3dsys: Convert to DT schema

Convert the MediaTek G3D system controller devicetree binding from the legacy text format to DT schema.

---
Changelog:
Changes since v3:
- Fix $id path to match new location

Link to v3:https://lore.kernel.org/all/[email protected]/

Changes since v2:
- Move binding to soc/mediatek directory
- Rename file to mediatek,mt2701-g3dsys.yaml based on fallback compatible

Link to v2:https://lore.kernel.org/all/[email protected]/

Changes since v1:
- Drop redundant description for reg
- Drop redundant description for provider properties

Link to v1:https://lore.kernel.org/all/[email protected]/

---
 .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ----------
 .../soc/mediatek/mediatek,mt2701-g3dsys.yaml  | 58 +++++++++++++++++++
 2 files changed, 58 insertions(+), 30 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt2701-g3dsys.yaml

deleted file mode 100644
index 7de43bf41fdc..000000000000
@@ -1,30 +0,0 @@
-MediaTek g3dsys controller
-============================
-
-The MediaTek g3dsys controller provides various clocks and reset controller to
-the GPU.
-
-Required Properties:
-
-- compatible: Should be:
-	- "mediatek,mt2701-g3dsys", "syscon":
-		for MT2701 SoC
-	- "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
-		for MT7623 SoC
-- #clock-cells: Must be 1
-- #reset-cells: Must be 1
-
-The g3dsys controller uses the common clk binding from
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-
-Example:
-
-g3dsys: clock-controller@13000000 {
-	compatible = "mediatek,mt7623-g3dsys",
-		     "mediatek,mt2701-g3dsys",
-		     "syscon";
-	reg = <0 0x13000000 0 0x200>;
-	#clock-cells = <1>;
-	#reset-cells = <1>;
-};

2.34.1

Best regards,
Krzysztof

Thank you, Krzysztof. This patch has not yet been merged into the mainline. Please let me know if any updates are required from my side.

Regards,
Udaya Kiran Challa

This should be taken by mediatek SoC maintainers, but they were not Cc-ed, probably because of missing maintainers patterns.

See also (I think wasn't picked up eventually):
https://lore.kernel.org/all/[email protected]/

Best regards,
Krzysztof