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arm64: dts: imx8mp-var-som-symphony: align DTS with hardware revision

PATCH Superseded Stefano Radaelli 3 participants 18 messages Jun 8

Subsystems (2)
Device tree bindings Arm i.MX and Layerscape

v4 of 5 Superseded Latest is v5 →

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Stefano Radaelli

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#0 lore raw

v4 cover arm64: dts: imx8mp-var-som-symphony: align DTS with hardware revision

This series updates the i.MX8MP VAR-SOM and Symphony device trees to better align them with the current hardware configuration.

It adds the missing board peripherals and completes the related pinctrl, GPIO and bus configuration.

v3->v4:
- Fixed USB irq edge type
- Add HDMI HPD support
- Add pcie reset-gpios instead of deprecated one
- Fixed eth regulator

v2->v3:
- Add FlexCAN2 controller support
- Add FEC controller and MaxLinear MXL86110 PHY support
- Describe PCIe PERST# reset GPIO

v1->v2:
- Add missing HDMI pinctrl configuration
- Enable LCDIF3 for the HDMI display pipeline
- Adjust PCIe controller configuration
- Update PTN5150 interrupt trigger type

Stefano Radaelli (14):
arm64: dts: imx8mp-var-som-symphony: add input keys
arm64: dts: imx8mp-var-som-symphony: enable USB support
arm64: dts: imx8mp-var-som-symphony: add TPM support
arm64: dts: imx8mp-var-som-symphony: add external RTC
arm64: dts: imx8mp-var-som-symphony: enable header UARTs
arm64: dts: imx8mp-var-som-symphony: enable PCIe
arm64: dts: imx8mp-var-som-symphony: add HDMI support
arm64: dts: imx8mp-var-som-symphony: add capacitive touchscreen
arm64: dts: imx8mp-var-som-symphony: enable ECSPI2
arm64: dts: imx8mp-var-som-symphony: keep RGB_SEL low
arm64: dts: imx8mp-var-som-symphony: enable PWM1
arm64: dts: imx8mp-var-som-symphony: enable CAN
arm64: dts: imx8mp-var-som-symphony: add second Ethernet port
arm64: dts: freescale: imx8mp-var-som: add I2C1 bus recovery GPIOs

 .../dts/freescale/imx8mp-var-som-symphony.dts | 397 +++++++++++++++++-
 .../boot/dts/freescale/imx8mp-var-som.dtsi    |  12 +-
 2 files changed, 407 insertions(+), 2 deletions(-)

base-commit: b3c1d1631f097619f8091f0293e027c4301285d6

Signature · 1 line
2.47.3
author
#1 lore raw

PATCH v4 1/14 arm64: dts: imx8mp-var-som-symphony: add input keys

Add the Back, Home and Menu keys connected through the GPIO expander on the Symphony carrier board.

Also enable the SNVS power key.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../dts/freescale/imx8mp-var-som-symphony.dts | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +29 -0
index 291f65e36865..25f707012f62 100644
@@ -13,6 +13,31 @@ chosen {
 		stdout-path = &uart2;
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		button-back {
+			label = "Back";
+			linux,code = <KEY_BACK>;
+			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-home {
+			label = "Home";
+			linux,code = <KEY_HOME>;
+			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-menu {
+			label = "Menu";
+			linux,code = <KEY_MENU>;
+			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+	};
+
 	gpio-leds {
 		compatible = "gpio-leds";
 

@@ -72,6 +97,10 @@ usb3-sata-sel-hog {
 	};
 };
 
+&snvs_pwrkey {
+	status = "okay";
+};
+
 /* Console */
 &uart2 {
 	pinctrl-names = "default";
Signature · 1 line
2.47.3
author
#2 lore raw

PATCH v4 2/14 arm64: dts: imx8mp-var-som-symphony: enable USB support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable the USB controllers on the Symphony carrier board.

Add the PTN5150 Type-C controller for USB role switching, enable the USB3 PHYs and controllers, configure the I2C bus used by the Type-C controller, and set the first USB port in OTG mode and the second port in host mode.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
- Fixed USB irq edge type

v2->v3:
-

v1->v2:
- Update PTN5150 interrupt trigger type

 .../dts/freescale/imx8mp-var-som-symphony.dts | 80 ++++++++++++++++++-
 1 file changed, 79 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +79 -1
index 25f707012f62..2b04c9027125 100644
@@ -72,8 +72,11 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
 
 &i2c3 {
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
 	/* GPIO expander */

@@ -95,6 +98,22 @@ usb3-sata-sel-hog {
 			line-name = "usb3_sata_sel";
 		};
 	};
+
+	/* USB Type-C Controller */
+	typec@3d {
+		compatible = "nxp,ptn5150";
+		reg = <0x3d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ptn5150>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+
+		port {
+			typec_dr_sw: endpoint {
+				remote-endpoint = <&usb3_drd_sw>;
+			};
+		};
+	};
 };
 
 &snvs_pwrkey {

@@ -108,6 +127,52 @@ &uart2 {
 	status = "okay";
 };
 
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	adp-disable;
+	dr_mode = "otg";
+	hnp-disable;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	srp-disable;
+	usb-role-switch;
+	status = "okay";
+
+	port {
+		usb3_drd_sw: endpoint {
+			remote-endpoint = <&typec_dr_sw>;
+		};
+	};
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb3_phy0 {
+	fsl,phy-comp-dis-tune-percent = <115>;
+	fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>;
+	fsl,phy-pcs-tx-swing-full-percent = <100>;
+	fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
+	fsl,phy-tx-vboost-level-microvolt = <1156>;
+	fsl,phy-tx-vref-tune-percent = <122>;
+	status = "okay";
+};
+
+&usb3_phy1 {
+	fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
+	fsl,phy-tx-vref-tune-percent = <116>;
+	status = "okay";
+};
+
 /* SD-card */
 &usdhc2 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";

@@ -129,12 +194,25 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                                 0x400001c2
 		>;
 	};
 
+	pinctrl_i2c3_gpio: i2c3gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18				0x1c2
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19				0x1c2
+		>;
+	};
+
 	pinctrl_pca9534: pca9534grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15                             0xc0
 		>;
 	};
 
+	pinctrl_ptn5150: ptn5150grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x10
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                            0x40
Signature · 1 line
2.47.3
AI review
#3 lore raw

Re: [PATCH v4 02/14] arm64: dts: imx8mp-var-som-symphony: enable USB support

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] Missing SION bit in I2C GPIO recovery pinmux configuration, which breaks I2C stuck-bus detection…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing SION bit in I2C GPIO recovery pinmux configuration, which breaks I2C stuck-bus detection during recovery. --

commit 8540c0ff1319c92d20f6a6b155aa57f03c50adce
Author: Stefano Radaelli <[email protected]>

arm64: dts: imx8mp-var-som-symphony: enable USB support

This commit enables the USB controllers on the Symphony carrier board. It adds the PTN5150 Type-C controller, configures the associated I2C bus, enables the USB3 PHYs, and sets up port modes for OTG and host operations.

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +0 -0
index 25f707012f62c..2b04c90271250 100644

[ ... ]

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 · line 200

Quoted 8 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +4 -0
@@ -129,12 +194,25 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                                 0x400001c2
 		>;
 	};
 
+	pinctrl_i2c3_gpio: i2c3gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18				0x1c2
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19				0x1c2

[Severity: Medium]
Does this configuration omit the SION (Software Input On) bit for the I2C recovery pins?

When an I2C bus hangs, the i2c-imx driver initiates a recovery sequence by reconfiguring the I2C pins to GPIO mode. The driver sets SCL as an output to manually toggle the clock, and then reads the state of SCL to verify if the line successfully went high or if a slave is stuck stretching the clock.

On i.MX processors, if a pad is configured as a GPIO output, reading its state returns the value written to the data register, rather than the actual physical voltage level on the pad, unless the SION bit (0x40000000) is set.

Without the SION bit set here (0x1c2 instead of 0x400001c2), the kernel will read back the logic value it just wrote. Will this defeat the stuck-bus detection, causing the driver to assume a successful recovery even if the bus is physically still held low?

Quoted 6 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +3 -0
+		>;
+	};
+
 	pinctrl_pca9534: pca9534grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15                             0xc0
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
author
#4 lore raw

PATCH v4 3/14 arm64: dts: imx8mp-var-som-symphony: add TPM support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the ST33KTPM2XI2C TPM device on the Symphony carrier board.

Enable the I2C4 bus, add the PCAL6408 GPIO expander used by the TPM and describe the TPM reset line.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../dts/freescale/imx8mp-var-som-symphony.dts | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +39 -0
index 2b04c9027125..e9fcc491e5b2 100644
@@ -116,6 +116,31 @@ typec_dr_sw: endpoint {
 	};
 };
 
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio", "sleep";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	pinctrl-2 = <&pinctrl_i2c4_gpio>;
+	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	pcal6408: gpio@21 {
+		compatible = "nxp,pcal6408";
+		reg = <0x21>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	st33ktpm2xi2c: tpm@2e {
+		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+		reg = <0x2e>;
+		label = "tpm";
+		reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
+	};
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };

@@ -201,6 +226,20 @@ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19				0x1c2
 		>;
 	};
 
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL					0x400001c2
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA					0x400001c2
+		>;
+	};
+
+	pinctrl_i2c4_gpio: i2c4gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20				0x1c2
+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21				0x1c2
+		>;
+	};
+
 	pinctrl_pca9534: pca9534grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15                             0xc0
Signature · 1 line
2.47.3
author
#5 lore raw

PATCH v4 4/14 arm64: dts: imx8mp-var-som-symphony: add external RTC

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the DS1337 RTC on the Symphony carrier board and disable the internal SNVS RTC.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +9 -0
index e9fcc491e5b2..7b839efdbcbc 100644
@@ -139,12 +139,21 @@ st33ktpm2xi2c: tpm@2e {
 		label = "tpm";
 		reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
 	};
+
+	rtc@68 {
+		compatible = "dallas,ds1337";
+		reg = <0x68>;
+	};
 };
 
 &snvs_pwrkey {
 	status = "okay";
 };
 
+&snvs_rtc {
+	status = "disabled";
+};
+
 /* Console */
 &uart2 {
 	pinctrl-names = "default";
Signature · 1 line
2.47.3
author
#6 lore raw

PATCH v4 5/14 arm64: dts: imx8mp-var-som-symphony: enable header UARTs

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable UART1 and UART4 on the Symphony carrier board and add the corresponding pinctrl configurations.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../dts/freescale/imx8mp-var-som-symphony.dts | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +28 -0
index 7b839efdbcbc..34a956c98635 100644
@@ -154,6 +154,13 @@ &snvs_rtc {
 	status = "disabled";
 };
 
+/* Header UART */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
 /* Console */
 &uart2 {
 	pinctrl-names = "default";

@@ -161,6 +168,13 @@ &uart2 {
 	status = "okay";
 };
 
+/* Header UART */
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
 &usb3_0 {
 	status = "okay";
 };

@@ -261,6 +275,13 @@ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x10
 		>;
 	};
 
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX				0x40
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX				0x40
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                            0x40

@@ -268,6 +289,13 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX                            0x40
 		>;
 	};
 
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX				0x40
+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX				0x40
+		>;
+	};
+
 	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14                             0x1c4
Signature · 1 line
2.47.3
author
#7 lore raw

PATCH v4 6/14 arm64: dts: imx8mp-var-som-symphony: enable PCIe

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the PCIe reference clock and enable the PCIe controller and PHY on the Symphony carrier board.

Describe the PERST# reset GPIO and configure the PHY to use an external reference clock input.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
- Add pcie reset-gpios instead of deprecated one

v2->v3:
-

v1->v2:
- Adjust PCIe controller configuration

 .../dts/freescale/imx8mp-var-som-symphony.dts  | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +18 -0
index 34a956c98635..a2becf5409cf 100644
@@ -48,6 +48,12 @@ led-0 {
 		};
 	};
 
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 		compatible = "regulator-fixed";
 		regulator-name = "VSD_3V3";

@@ -146,6 +152,18 @@ rtc@68 {
 	};
 };
 
+&pcie {
+	reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie_phy {
+	clocks = <&pcie0_refclk>;
+	clock-names = "ref";
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
Signature · 1 line
2.47.3
author
#8 lore raw

PATCH v4 7/14 arm64: dts: imx8mp-var-som-symphony: add HDMI support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable the HDMI display pipeline and HDMI audio support on the Symphony carrier board.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
- Add HDMI HPD support

v2->v3:
-

v1->v2:
- Add missing HDMI pinctrl configuration
- Enable LCDIF3 for the HDMI display pipeline

 .../dts/freescale/imx8mp-var-som-symphony.dts | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +62 -0
index a2becf5409cf..f27ba602c743 100644
@@ -48,6 +48,18 @@ led-0 {
 		};
 	};
 
+	native-hdmi-connector {
+		compatible = "hdmi-connector";
+		label = "HDMI OUT";
+		type = "a";
+
+		port {
+			hdmi_in: endpoint {
+				remote-endpoint = <&hdmi_tx_out>;
+			};
+		};
+	};
+
 	pcie0_refclk: pcie0-refclk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;

@@ -74,6 +86,43 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
 		states = <3300000 0x0 1800000 0x1>;
 		vin-supply = <&ldo5>;
 	};
+
+	sound-hdmi {
+		compatible = "fsl,imx-audio-hdmi";
+		model = "audio-hdmi";
+		audio-cpu = <&aud2htx>;
+		hdmi-out;
+	};
+};
+
+&aud2htx {
+	status = "okay";
+};
+
+&hdmi_pai {
+	status = "okay";
+};
+
+&hdmi_pvi {
+	status = "okay";
+};
+
+&hdmi_tx {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi>;
+	status = "okay";
+
+	ports {
+		port@1 {
+			hdmi_tx_out: endpoint {
+				remote-endpoint = <&hdmi_in>;
+			};
+		};
+	};
+};
+
+&hdmi_tx_phy {
+	status = "okay";
 };
 
 &i2c3 {

@@ -152,6 +201,10 @@ rtc@68 {
 	};
 };
 
+&lcdif3 {
+	status = "okay";
+};
+
 &pcie {
 	reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>;
 	status = "okay";

@@ -253,6 +306,15 @@ &usdhc2 {
 };
 
 &iomuxc {
+	pinctrl_hdmi: hdmigrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL			0x1c2
+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA			0x1c2
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC				0x10
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD				0x10
+		>;
+	};
+
 	pinctrl_i2c3: i2c3grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                                 0x400001c2
Signature · 1 line
2.47.3
author
#9 lore raw

PATCH v4 8/14 arm64: dts: imx8mp-var-som-symphony: add capacitive touchscreen

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the FT5206 capacitive touchscreen controller on the Symphony carrier board.
Describe the interrupt pin and touchscreen geometry.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../dts/freescale/imx8mp-var-som-symphony.dts | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +21 -0
index f27ba602c743..bac3de6e1530 100644
@@ -195,6 +195,21 @@ st33ktpm2xi2c: tpm@2e {
 		reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
 	};
 
+	/* Capacitive touch controller */
+	ft5x06_ts: touchscreen@38 {
+		compatible = "edt,edt-ft5206";
+		reg = <0x38>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_captouch>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+		touchscreen-inverted-x;
+		touchscreen-inverted-y;
+		wakeup-source;
+	};
+
 	rtc@68 {
 		compatible = "dallas,ds1337";
 		reg = <0x68>;

@@ -306,6 +321,12 @@ &usdhc2 {
 };
 
 &iomuxc {
+	pinctrl_captouch: captouchgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03				0x16
+		>;
+	};
+
 	pinctrl_hdmi: hdmigrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL			0x1c2
Signature · 1 line
2.47.3
author
#10 lore raw

PATCH v4 9/14 arm64: dts: imx8mp-var-som-symphony: enable ECSPI2

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable the ECSPI2 bus on the Symphony carrier board and add the pinctrl configuration for the SPI signals and chip select GPIO.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../dts/freescale/imx8mp-var-som-symphony.dts    | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +16 -0
index bac3de6e1530..c7073fcb679e 100644
@@ -99,6 +99,13 @@ &aud2htx {
 	status = "okay";
 };
 
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
 &hdmi_pai {
 	status = "okay";
 };

@@ -327,6 +334,15 @@ MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03				0x16
 		>;
 	};
 
+	pinctrl_ecspi2: ecspi2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK				0x12
+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI				0x12
+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO				0x12
+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13				0x12
+		>;
+	};
+
 	pinctrl_hdmi: hdmigrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL			0x1c2
Signature · 1 line
2.47.3
author
#11 lore raw

PATCH v4 10/14 arm64: dts: imx8mp-var-som-symphony: keep RGB_SEL low

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Keep the RGB_SEL line driven low on the Symphony carrier board.

This avoids leaving the line floating and ensures the board remains in the expected display configuration.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
-

v2->v3:
-

v1->v2:
-

 arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +8 -0
index c7073fcb679e..4f1d61c55ffb 100644
@@ -193,6 +193,14 @@ pcal6408: gpio@21 {
 		reg = <0x21>;
 		#gpio-cells = <2>;
 		gpio-controller;
+
+		/* RGB_SEL */
+		lvds-brg-enable-hog {
+			gpio-hog;
+			gpios = <7 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "rgb_sel";
+		};
 	};
 
 	st33ktpm2xi2c: tpm@2e {
Signature · 1 line
2.47.3
author
#12 lore raw

PATCH v4 11/14 arm64: dts: imx8mp-var-som-symphony: enable PWM1

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../boot/dts/freescale/imx8mp-var-som-symphony.dts   | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +12 -0
index 4f1d61c55ffb..e1b78ed167b4 100644
@@ -247,6 +247,12 @@ &pcie_phy {
 	status = "okay";
 };
 
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };

@@ -400,6 +406,12 @@ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x10
 		>;
 	};
 
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT				0x116
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX				0x40
Signature · 1 line
2.47.3
author
#13 lore raw

PATCH v4 12/14 arm64: dts: imx8mp-var-som-symphony: enable CAN

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable the FlexCAN2 controller on the Symphony carrier board and add the corresponding pinctrl configuration.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
-

v2->v3:
- Add FlexCAN2 controller support

v1->v2:
-

 .../boot/dts/freescale/imx8mp-var-som-symphony.dts  | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +13 -0
index e1b78ed167b4..7ad57caa0f1c 100644
@@ -106,6 +106,12 @@ &ecspi2 {
 	status = "okay";
 };
 
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	status = "okay";
+};
+
 &hdmi_pai {
 	status = "okay";
 };

@@ -357,6 +363,13 @@ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13				0x12
 		>;
 	};
 
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART3_RXD__CAN2_TX					0x154
+			MX8MP_IOMUXC_UART3_TXD__CAN2_RX					0x154
+		>;
+	};
+
 	pinctrl_hdmi: hdmigrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL			0x1c2
Signature · 1 line
2.47.3
author
#14 lore raw

PATCH v4 13/14 arm64: dts: imx8mp-var-som-symphony: add second Ethernet port

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add support for the second Ethernet interface available on the Symphony carrier board.

Enable the FEC controller, add the MaxLinear MXL86110 Gigabit Ethernet PHY on the MDIO bus, describe its reset and power configuration, and add the required RGMII pinctrl settings.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
- Fixed eth regulator

v2->v3:
- Add FEC controller and MaxLinear MXL86110 PHY support

 .../dts/freescale/imx8mp-var-som-symphony.dts | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +62 -0
index 7ad57caa0f1c..c5a38018d494 100644
@@ -66,6 +66,24 @@ pcie0_refclk: pcie0-refclk {
 		clock-frequency = <100000000>;
 	};
 
+	reg_fec_phy: regulator-fec-phy {
+		compatible = "regulator-fixed";
+		regulator-name = "fec-phy";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-enable-ramp-delay = <20000>;
+		gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	reg_phy_vddio: regulator-phy-vddio {
+		compatible = "regulator-fixed";
+		regulator-name = "vddio-1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 		compatible = "regulator-fixed";
 		regulator-name = "VSD_3V3";

@@ -106,6 +124,33 @@ &ecspi2 {
 	status = "okay";
 };
 
+&eqos {
+	mdio {
+		ethphy1: ethernet-phy@5 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <5>;
+			reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <20000>;
+			vddio-supply = <&reg_phy_vddio>;
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec>;
+	/*
+	 * The required RGMII TX and RX 2ns delays are implemented directly
+	 * in hardware via passive delay elements on the SOM PCB.
+	 * No delay configuration is needed in software via PHY driver.
+	 */
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	phy-supply = <&reg_fec_phy>;
+	status = "okay";
+};
+
 &flexcan2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexcan2>;

@@ -363,6 +408,23 @@ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13				0x12
 		>;
 	};
 
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0				0x90
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1				0x90
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2				0x90
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3				0x90
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC				0x90
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL			0x90
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0				0x00
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1				0x00
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2				0x00
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3				0x00
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL			0x00
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC				0x00
+		>;
+	};
+
 	pinctrl_flexcan2: flexcan2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART3_RXD__CAN2_TX					0x154
Signature · 1 line
2.47.3
AI review
#15 lore raw

Re: [PATCH v4 13/14] arm64: dts: imx8mp-var-som-symphony: add second Ethernet port

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] The RGMII TX pads in `pinctrl_fec` are misconfigured with a value of `0x00`, resulting in a slow…

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The RGMII TX pads in pinctrl_fec are misconfigured with a value of 0x00, resulting in a slow slew rate and minimal drive strength.
- [Low] The reg_phy_vddio node and label are redundantly redefined, which will cause a Device Tree Compiler duplicate label error.
- [Low] Potential missing RGMII delay configuration and misleading comment due to a blindly copy-pasted phy-mode.
--

commit 6c050703eb451d931bc2a42a7966eecdf5e1949c
Author: Stefano Radaelli <[email protected]>

arm64: dts: imx8mp-var-som-symphony: add second Ethernet port

This commit adds support for the second Ethernet interface on the Symphony carrier board. It enables the FEC controller, configures the MaxLinear PHY on the MDIO bus, and sets up the required RGMII pinctrl settings.

Quoted 15 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +7 -0
index 7ad57caa0f1c2..c5a38018d494b 100644
@@ -66,6 +66,24 @@ pcie0_refclk: pcie0-refclk {
 		clock-frequency = <100000000>;
 	};
 
+	reg_fec_phy: regulator-fec-phy {
+		compatible = "regulator-fixed";
+		regulator-name = "fec-phy";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-enable-ramp-delay = <20000>;
+		gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts pcie0_refclk: pcie0-refclk { · line 85

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +10 -0
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	reg_phy_vddio: regulator-phy-vddio {
+		compatible = "regulator-fixed";
+		regulator-name = "vddio-1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};

[Severity: Low]
Will this cause a Device Tree Compiler duplicate label error?

The reg_phy_vddio label and its node appear to already be defined at the root level in the included imx8mp-var-som.dtsi file. Redefining it directly here in the symphony dts usually causes dtc to fail compilation.

[ ... ]

Quoted 16 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +12 -0
@@ -106,6 +124,33 @@ &ecspi2 {
 	status = "okay";
 };
 
+&eqos {
+	mdio {
+		ethphy1: ethernet-phy@5 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <5>;
+			reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <20000>;
+			vddio-supply = <&reg_phy_vddio>;
+		};
+	};
+};

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts &ecspi2 { · line 148

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +10 -0
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec>;
+	/*
+	 * The required RGMII TX and RX 2ns delays are implemented directly
+	 * in hardware via passive delay elements on the SOM PCB.
+	 * No delay configuration is needed in software via PHY driver.
+	 */
+	phy-mode = "rgmii";

[Severity: Low]
Is this comment accurate for this interface, or was it copy-pasted from the SOM eqos interface?

The comment states the delays are implemented via passive delay elements on the SOM PCB, but this Ethernet PHY is located on the Symphony carrier board.

If the carrier board lacks these passive delay elements, should phy-mode be set to "rgmii-id" instead?

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +4 -0
+	phy-handle = <&ethphy1>;
+	phy-supply = <&reg_fec_phy>;
+	status = "okay";
+};

[ ... ]

Quoted 8 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +4 -0
@@ -363,6 +408,23 @@ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13				0x12
 		>;
 	};
 
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0				0x90
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1				0x90

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12 · line 424

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +10 -0
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2				0x90
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3				0x90
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC				0x90
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL			0x90
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0				0x00
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1				0x00
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2				0x00
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3				0x00
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL			0x00
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC				0x00

[Severity: High]
Will configuring these RGMII TX pads with 0x00 degrade signal integrity?

In the i.MX8MP pad configuration, a value of 0x00 sets a Slow Slew Rate (SRE=0) and the weakest Drive Strength (DSE=X1). RGMII interfaces run at 125 MHz DDR and typically require a fast slew rate and high drive strength (such as 0x16 or 0x1f).

Does using 0x00 risk heavy distortion, TX packet loss, or a complete link failure?

Quoted 2 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +2 -0
+		>;
+	};
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=13
reviewer
#16 lore raw

Re: [PATCH v4 13/14] arm64: dts: imx8mp-var-som-symphony: add second Ethernet port

In reply to Stefano Radaelli

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts pcie0_refclk: pcie0-refclk { · line 77

Quoted 9 lines · Stefano Radaelli
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +9 -0
+       reg_fec_phy: regulator-fec-phy {
+               compatible = "regulator-fixed";
+               regulator-name = "fec-phy";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-enable-ramp-delay = <20000>;
+               gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               regulator-always-on;

There is no need to mark it as regulator-always-on, as reg_fec_phy has a consumer.

Please check globally.

author
#17 lore raw

PATCH v4 14/14 arm64: dts: freescale: imx8mp-var-som: add I2C1 bus recovery GPIOs

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the GPIO pinctrl state and GPIO descriptors required for I2C1 bus recovery on the VAR-SOM-MX8M-PLUS.

This allows the I2C controller to recover the bus if SDA or SCL are held low by a device.

Signed-off-by Stefano Radaelli <[email protected]>

---
v3->v4:
-

v2->v3:
-

 arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +11 -1
index 49467b48d0b0..61786eee0e82 100644
@@ -180,8 +180,11 @@ led@1 {
 
 &i2c1 {
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
 	pmic@25 {

@@ -415,6 +418,13 @@ MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA				0x400001c2
 		>;
 	};
 
+	pinctrl_i2c1_gpio: i2c1gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06				0x1c2
+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07				0x1c2
+		>;
+	};
+
 	pinctrl_pmic: pmicgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04				0x1c0
Signature · 1 line
2.47.3