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dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5

PATCH In review Dinh Nguyen 3 participants 5 messages Jun 29

Subsystems (4)
Network drivers Device tree bindings Arm STM32 Arm/socfpga dwmac glue layer
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Dinh Nguyen

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#0 lore raw

PATCH v2 1/2 dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5

The stmmac hardware on Agilex5 supports 8 TX/RX queue pairs and is dma-coherent. Update the schema to handle the hardware differences between SoC variants.

Also make 'interrupts' and 'interrupt-names' as required properties.

Signed-off-by Dinh Nguyen <[email protected]>

---
v2: Set the top level interrupts to include the widest contraints(1-17)
Just have 1 list of all interrupt-names
Update commit message to include 'interrupts' and 'interrupt-names' as required properties
Change minItems 1 to maxItems 1 for non agilex5 variants Add same constraint for interrupt-names

---
 .../bindings/net/altr,socfpga-stmmac.yaml     | 46 ++++++++++++++++++-
 1 file changed, 45 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +45 -1
index fc445ad5a1f1..63084f762373 100644
@@ -63,11 +63,29 @@ properties:
       - const: ptp_ref
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    maxItems: 17
 
   interrupt-names:
+    minItems: 1
     items:
       - const: macirq
+      - const: tx-queue-0
+      - const: tx-queue-1
+      - const: tx-queue-2
+      - const: tx-queue-3
+      - const: tx-queue-4
+      - const: tx-queue-5
+      - const: tx-queue-6
+      - const: tx-queue-7
+      - const: rx-queue-0
+      - const: rx-queue-1
+      - const: rx-queue-2
+      - const: rx-queue-3
+      - const: rx-queue-4
+      - const: rx-queue-5
+      - const: rx-queue-6
+      - const: rx-queue-7
 
   iommus:
     minItems: 1

@@ -149,10 +167,36 @@ required:
   - clocks
   - clock-names
   - altr,sysmgr-syscon
+  - interrupts
+  - interrupt-names
 
 allOf:
   - $ref: snps,dwmac.yaml#
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: altr,socfpga-stmmac-agilex5
+    then:
+      properties:
+        interrupts:
+          minItems: 17
+
+        interrupt-names:
+          minItems: 17
+
+        dma-coherent: true
+    else:
+      properties:
+        interrupts:
+          maxItems: 1
+
+        interrupt-names:
+          maxItems: 1
+
+        dma-coherent: false
+
 unevaluatedProperties: false
 
 examples:
Signature · 1 line
2.42.0.411.g813d9a9188
author
#1 lore raw

PATCH v2 2/2 arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue pairs.

Signed-off-by Dinh Nguyen <[email protected]>

---
v2: no changes

---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 72 +++++++++++++++++--
 1 file changed, 68 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +68 -4
index 2096decb5655..f54767d1526e 100644
@@ -702,8 +702,40 @@ gmac1: ethernet@10820000 {
 			compatible = "altr,socfpga-stmmac-agilex5",
 				     "snps,dwxgmac-2.10";
 			reg = <0x10820000 0x3500>;
-			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
+			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq",
+					  "tx-queue-0",
+					  "tx-queue-1",
+					  "tx-queue-2",
+					  "tx-queue-3",
+					  "tx-queue-4",
+					  "tx-queue-5",
+					  "tx-queue-6",
+					  "tx-queue-7",
+					  "rx-queue-0",
+					  "rx-queue-1",
+					  "rx-queue-2",
+					  "rx-queue-3",
+					  "rx-queue-4",
+					  "rx-queue-5",
+					  "rx-queue-6",
+					  "rx-queue-7";
 			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 			reset-names = "stmmaceth", "ahb";
 			clocks = <&clkmgr AGILEX5_EMAC1_CLK>,

@@ -816,8 +848,40 @@ gmac2: ethernet@10830000 {
 			compatible = "altr,socfpga-stmmac-agilex5",
 				     "snps,dwxgmac-2.10";
 			reg = <0x10830000 0x3500>;
-			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
+			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq",
+					  "tx-queue-0",
+					  "tx-queue-1",
+					  "tx-queue-2",
+					  "tx-queue-3",
+					  "tx-queue-4",
+					  "tx-queue-5",
+					  "tx-queue-6",
+					  "tx-queue-7",
+					  "rx-queue-0",
+					  "rx-queue-1",
+					  "rx-queue-2",
+					  "rx-queue-3",
+					  "rx-queue-4",
+					  "rx-queue-5",
+					  "rx-queue-6",
+					  "rx-queue-7";
 			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 			reset-names = "stmmaceth", "ahb";
 			clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
Signature · 1 line
2.42.0.411.g813d9a9188
AI review
#2 lore raw

Re: [PATCHv2 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] The patch adds 16 additional queue interrupts to the gmac1 and gmac2 device tree nodes, violating…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch adds 16 additional queue interrupts to the gmac1 and gmac2 device tree nodes, violating the strict maxItems: 1 constraint in the altr,socfpga-stmmac.yaml binding schema. --

commit 40c2d176bae16fd4cc692701cf60a99607edf61f
Author: Dinh Nguyen <[email protected]>

arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue pairs in the agilex5 device tree.

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi gmac1: ethernet@10820000 { · line 675

Quoted 13 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +3 -2
index 02e62d954e949..140e4bf9fb155 100644
@@ -670,8 +670,40 @@ gmac1: ethernet@10820000 {
 			compatible = "altr,socfpga-stmmac-agilex5",
 				     "snps,dwxgmac-2.10";
 			reg = <0x10820000 0x3500>;
-			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
+			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,

[Severity: Low]
Does this expansion of the interrupts list trigger a dtbs_check warning?

Looking at Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml, it strictly limits interrupts:

interrupts:
maxItems: 1

interrupt-names:
items:
- const: macirq

Should the binding schema be updated concurrently with the dtsi to allow these queue-specific interrupts and avoid validation failures?

[ ... ]

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi gmac2: ethernet@10830000 { · line 820

Quoted 9 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +3 -2
@@ -783,8 +815,40 @@ gmac2: ethernet@10830000 {
 			compatible = "altr,socfpga-stmmac-agilex5",
 				     "snps,dwxgmac-2.10";
 			reg = <0x10830000 0x3500>;
-			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
+			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,

[Severity: Low]
Same question here regarding the altr,socfpga-stmmac.yaml binding schema limiting interrupts to maxItems: 1.

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
AI review
#3 lore raw
In reply to Dinh Nguyen
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The schema enforces a strict minimum of 17 interrupts for the Agilex5 compatible, breaking…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The schema enforces a strict minimum of 17 interrupts for the Agilex5 compatible, breaking validation for existing in-tree device trees that only define 1 interrupt. --

commit 7df8c6aab116c93fb2cc3131f91a04fdfb5b5ecf
Author: Dinh Nguyen <[email protected]>

dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5

The stmmac hardware on Agilex5 supports 8 TX/RX queue pairs and is dma-coherent. Update the schema to handle the hardware differences between SoC variants.

Also make 'interrupts' and 'interrupt-names' as required properties.

Quoted 4 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +0 -0
index fc445ad5a1f1a..63084f7623738 100644

[ ... ]

Quoted 12 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +4 -0
@@ -149,10 +167,36 @@ required:
   - clocks
   - clock-names
   - altr,sysmgr-syscon
+  - interrupts
+  - interrupt-names
 
 allOf:
   - $ref: snps,dwmac.yaml#
 
+  - if:
+      properties:

Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml required: · line 187

Quoted 10 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +10 -0
+        compatible:
+          contains:
+            const: altr,socfpga-stmmac-agilex5
+    then:
+      properties:
+        interrupts:
+          minItems: 17
+
+        interrupt-names:
+          minItems: 17

[Severity: Medium]
Will this strict minimum break devicetree validation for existing in-tree device trees?

For example, in arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi, the existing gmac0 node only defines one interrupt:

    gmac0: ethernet@10810000 {
        compatible = "altr,socfpga-stmmac-agilex5",
                 "snps,dwxgmac-2.10";
        reg = <0x10810000 0x3500>;
        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "macirq";
        ...

If existing trees don't provide all 17 interrupts, enforcing exactly 17 here will cause dtbs_check to fail. Could minItems be relaxed or should the existing device trees be updated alongside this change?

Quoted 15 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +12 -0
+
+        dma-coherent: true
+    else:
+      properties:
+        interrupts:
+          maxItems: 1
+
+        interrupt-names:
+          maxItems: 1
+
+        dma-coherent: false
+
 unevaluatedProperties: false
 
 examples:
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1