pwm: Add Nuvoton MA35D1 PWM controller support
Subsystems (3)
v6 cover pwm: Add Nuvoton MA35D1 PWM controller support
From: Chi-Wen Weng <[email protected]>
This series adds the device tree binding and PWM framework driver for the Nuvoton MA35D1 EPWM controller.
The MA35D1 EPWM controller provides 6 PWM channels. The hardware supports up, down and up-down counter types, auto-reload and one-shot modes, and independent and complementary output modes.
The initial driver supports independent output mode only and configures a channel for up-counting and auto-reload operation when an explicit .apply() request is made. The waveform generator drives the output high at the zero point and low at the compare-up point.
In up-counting mode, the counter counts from 0 to PERIOD inclusive. With the selected waveform actions, CMPDAT = 0 generates a 0% duty cycle and CMPDAT > PERIOD generates a 100% duty cycle. The driver keeps PERIOD one count below the 16-bit field maximum so that CMPDAT can be programmed greater than PERIOD for the full-duty case.
PERIOD and CMPDAT use the hardware period-loading buffers. Since the two registers are written separately, if a period boundary occurs between the writes, one transitional cycle can use the new PERIOD value with the previous CMPDAT value. The following period then uses both new values.
The driver selects period loading mode by clearing IMMLDENn, WINLDENn and CTRLDn. When a PWM is disabled, POENn and CNTENn are cleared. Clearing POENn disables the output driver and puts the output pin into high impedance.
The driver does not modify the PWM controller during probe. This preserves PWM outputs that may have been configured and enabled by firmware, such as a display backlight. The counter and waveform configuration is changed only for the channel passed to .apply().
Since the independent/complementary mode selection is shared by each pair of channels, the driver refuses to change an active complementary pair to independent mode when the paired channel is active.
Changes in v6:
- Document that clearing POENn disables the output driver and puts the output pin into high impedance.
- Document that a period boundary between the PERIOD and CMPDAT writes can result in one transitional cycle using the new period with the previous duty cycle.
- No functional changes.
Changes in v5:
- Remove the probe-time controller initialization to preserve PWM outputs configured by firmware.
- Configure the counter and waveform settings only for the channel passed to .apply().
- Keep the disable path limited to clearing POENn and CNTENn.
- Check for an active paired channel before changing a complementary pair to independent mode.
- Return -EBUSY when changing the shared output mode would disturb an active paired channel.
- Document that the initial driver supports independent output mode only.
- Remove the unnecessary <linux/mod_devicetable.h> include.
- Simplify the WGCTL action field handling and remove the associated static inline mask helpers.
- Rename the PWM field and period limits to clarify their different semantics.
- Configure period loading mode explicitly in .apply().
- Preserve the pair-shared clock prescaler and account for it in period and duty-cycle calculations.
- Limit the period to 0xffff counter cycles while reserving CMPDAT = 0xffff for the full-duty case.
Changes in v4:
- Add a Limitations section to describe the hardware capabilities and driver limitations.
- Add a link to the MA35D1 reference manual.
- Replace register address macros containing the base pointer with register offset macros.
- Add readl/writel/rmw helper functions.
- Rename TOTAL_CHANNELS to NUM_CHANNELS.
- Use unsigned long for the cached clock rate.
- Use devm_clk_rate_exclusive_get().
- Configure polarity before enabling the counter and output.
- Add controller initialization for up-counting, auto-reload and independent output mode.
- Configure the waveform generator for zero-point-high and compare-up-low output.
- Fix the period conversion because the hardware period is PERIOD + 1 cycles.
- Limit the maximum PERIOD value to 0xfffe so that CMPDAT = 0xffff can be used to generate 100% duty cycle.
- Use CNTEN and POEN bits to report the enabled state in .get_state().
- Disable the PWM by clearing POENn and CNTENn.
- Fix error message capitalization and trailing newlines.
- Fix coding style issues reported by review/checkpatch-style tools.
Changes in v3:
- Update nuvoton,ma35d1-pwm.yaml:
- Add maintainers entry.
- Increase "#pwm-cells" to 3.
- Update the MA35D1 PWM driver:
- Organize include headers and macro definitions.
- Rename REG_PWM_XXXX macros to MA35D1_REG_PWM_XXXX.
- Add register address macros.
v2 resend:
- Remove incorrect Reviewed-by tags.
Changes in v2:
- Update nuvoton,ma35d1-pwm.yaml:
- Fix maxItems of reg to 1.
- Remove unused label.
- Update the MA35D1 PWM driver:
- Remove MODULE_ALIAS().
- Add chip->atomic = true.
Chi-Wen Weng (2):
dt-bindings: pwm: Add Nuvoton MA35D1 PWM controller
pwm: Add Nuvoton MA35D1 PWM controller support
Documentation/devicetree/bindings/pwm/nuvoton,ma35d1-pwm.yaml | 45 +++ drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ma35d1.c | 387 +++++++++++++++++++++ 4 files changed, 443 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/nuvoton,ma35d1-pwm.yaml create mode 100644 drivers/pwm/pwm-ma35d1.c
Signature · 1 line
2.25.1
PATCH v6 1/2 dt-bindings: pwm: Add Nuvoton MA35D1 PWM controller
From: Chi-Wen Weng <[email protected]>
Add device tree binding for the Nuvoton MA35D1 PWM controller.
The MA35D1 PWM controller provides 6 PWM channels and uses one register region and one functional clock. The binding uses the standard PWM binding with three PWM cells.
--- .../bindings/pwm/nuvoton,ma35d1-pwm.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/nuvoton,ma35d1-pwm.yaml
Documentation/devicetree/bindings/pwm/nuvoton,ma35d1-pwm.yaml new file +45 -0
@@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/nuvoton,ma35d1-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 PWM controller + +maintainers: + - Chi-Wen Weng <[email protected]> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - nuvoton,ma35d1-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> + + pwm@40580000 { + compatible = "nuvoton,ma35d1-pwm"; + reg = <0x40580000 0x400>; + clocks = <&clk EPWM0_GATE>; + #pwm-cells = <3>; + };
Signature · 1 line
2.25.1
PATCH v6 2/2 pwm: Add Nuvoton MA35D1 PWM controller support
In reply to Chi-Wen WengFrom: Chi-Wen Weng <[email protected]>
Add a PWM framework driver for the Nuvoton MA35D1 EPWM controller.
The controller provides 6 PWM channels. The initial driver supports up-counting, auto-reload, independent output mode and period loading mode.
Configure the waveform generator to drive the output high at the zero point and low at the compare-up point. In up-counting mode the counter counts from 0 to PERIOD inclusive. CMPDAT = 0 therefore generates a 0% duty cycle, while CMPDAT > PERIOD generates a 100% duty cycle.
Limit the period to 0xffff counter cycles so that PERIOD is at most 0xfffe and CMPDAT = 0xffff remains available to represent a 100% duty cycle.
The clock prescaler is shared by each pair of PWM channels. Preserve the existing prescaler value and account for CLKPSC + 1 when calculating and reporting the period and duty cycle.
Do not modify the controller during probe, preserving PWM outputs that may have been configured by firmware. Configure only the requested channel from the apply callback, and refuse to change an active complementary pair to independent mode if doing so would disturb the paired output.
Period and compare values use the hardware period-loading buffers. Because PERIOD and CMPDAT are written separately, a period boundary between the two writes can result in one transitional cycle using the new period with the previous duty cycle.
When disabling a channel, clear its output-enable and counter-enable bits. Clearing the output-enable bit places the output pin in high impedance.
--- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ma35d1.c | 387 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 398 insertions(+) create mode 100644 drivers/pwm/pwm-ma35d1.c
drivers/pwm/Kconfig +10 -0
@@ -463,6 +463,16 @@ config PWM_LPSS_PLATFORM To compile this driver as a module, choose M here: the module will be called pwm-lpss-platform. +config PWM_MA35D1 + tristate "Nuvoton MA35D1 PWM support" + depends on ARCH_MA35 || COMPILE_TEST + help + Generic PWM framework driver for the Nuvoton MA35D1 PWM + controller, which provides 6 PWM outputs. + + To compile this driver as a module, choose M here: the module + will be called pwm-ma35d1. + config PWM_MAX7360 tristate "MAX7360 PWMs" depends on MFD_MAX7360
drivers/pwm/Makefile +1 -0
@@ -40,6 +40,7 @@ obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o +obj-$(CONFIG_PWM_MA35D1) += pwm-ma35d1.o obj-$(CONFIG_PWM_MAX7360) += pwm-max7360.o obj-$(CONFIG_PWM_MC33XS2410) += pwm-mc33xs2410.o obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
drivers/pwm/pwm-ma35d1.c new file +387 -0
387 lines not on this page · raw message
Signature · 1 line
2.25.1
[email protected]
AI reviewThank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The driver relies on the bootloader-configured CLKPSC (prescaler) register but does not cache…
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The driver relies on the bootloader-configured CLKPSC (prescaler) register but does not cache its value, which will cause incorrect period calculations after a system suspend/resume cycle. --
commit b9ac3c051c5908fe946a0ef1c7b809030aa32933
Author: Chi-Wen Weng <[email protected]>
pwm: Add Nuvoton MA35D1 PWM controller support
This commit adds a generic PWM framework driver for the Nuvoton MA35D1 PWM controller. The initial driver supports 6 channels in up-counting, auto-reload, independent output, and period loading modes.
Quoted 4 lines
drivers/pwm/pwm-ma35d1.c new file +0
-0
[ ... ]
drivers/pwm/pwm-ma35d1.c line 136
Quoted 6 lines
drivers/pwm/pwm-ma35d1.c new file +6
-0+static u32 nuvoton_pwm_get_prescale (struct nuvoton_pwm *nvtpwm, +unsigned int ch) +{ +return nuvoton_pwm_readl (nvtpwm,MA35D1_REG_PWM_CLKPSC (ch)) & +MA35D1_PWM_CLKPSC_MASK ; +}
[Severity: Medium]
Does reading the hardware register directly here make the driver vulnerable to hardware state loss during system suspend?
If the controller loses power during suspend, the clock prescaler register might reset to its default value. When the system resumes and a consumer subsequently calls into the apply callback, this function will return the reset value instead of the bootloader-configured value. This could result in drastically altered PWM output frequencies.
Would it be safer to cache the prescaler value during probe?
[ ... ]
drivers/pwm/pwm-ma35d1.c line 382
Quoted 7 lines
drivers/pwm/pwm-ma35d1.c new file +7
-0+static struct platform_driver nuvoton_pwm_driver = { + .probe = nuvoton_pwm_probe, + .driver = { + .name ="nuvoton-pwm" , + .of_match_table = nuvoton_pwm_of_match, + }, +};
[Severity: Medium]
Should this driver include PM callbacks to handle saving and restoring the hardware state?
Currently, there are no suspend/resume hooks provided. If the platform powers down the PWM domain during system suspend, the controller state will be lost upon resume and might not be appropriately reconfigured before the next state application.
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
[email protected] 於 2026/9/14 下午 07:17 寫道:
Quoted 50 lines
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The driver relies on the bootloader-configured CLKPSC (prescaler) register but does not cache its value, which will cause incorrect period calculations after a system suspend/resume cycle. --commit
b9ac3c051c5908fe946a0ef1c7b809030aa32933
Author: Chi-Wen Weng <[email protected]>pwm: Add Nuvoton MA35D1 PWM controller support
This commit adds a generic PWM framework driver for the Nuvoton MA35D1 PWM controller. The initial driver supports 6 channels in up-counting, auto-reload, independent output, and period loading modes.
Quoted 4 lines
drivers/pwm/pwm-ma35d1.c new file +0
-0[ ... ]
drivers/pwm/pwm-ma35d1.c line 136
Quoted 6 lines
drivers/pwm/pwm-ma35d1.c new file +6
-0+static u32 nuvoton_pwm_get_prescale (struct nuvoton_pwm *nvtpwm, +unsigned int ch) +{ +return nuvoton_pwm_readl (nvtpwm,MA35D1_REG_PWM_CLKPSC (ch)) & +MA35D1_PWM_CLKPSC_MASK ; +}[Severity: Medium]
Does reading the hardware register directly here make the driver vulnerable to hardware state loss during system suspend?If the controller loses power during suspend, the clock prescaler register might reset to its default value. When the system resumes and a consumer subsequently calls into the apply callback, this function will return the reset value instead of the bootloader-configured value. This could result in drastically altered PWM output frequencies.
Would it be safer to cache the prescaler value during probe?
[ ... ]
drivers/pwm/pwm-ma35d1.c line 382
Quoted 7 lines
drivers/pwm/pwm-ma35d1.c new file +7
-0+static struct platform_driver nuvoton_pwm_driver = { + .probe = nuvoton_pwm_probe, + .driver = { + .name ="nuvoton-pwm" , + .of_match_table = nuvoton_pwm_of_match, + }, +};[Severity: Medium]
Should this driver include PM callbacks to handle saving and restoring the hardware state?
Quoted 5 lines
Currently, there are no suspend/resume hooks provided. If the platform powers down the PWM domain during system suspend, the controller state will be lost upon resume and might not be appropriately reconfigured before the next state application.
Hi,
Thanks for the review.
On MA35D1, the EPWM register context is retained across system suspend. This includes CLKPSC as well as the other EPWM configuration registers used by the driver.
Therefore, after resume, nuvoton_pwm_get_prescale() still reads the same CLKPSC value that was present before suspend. The firmware-provided prescaler value is not lost, so caching CLKPSC during probe would be redundant.
For the same reason, suspend/resume callbacks are not required to save and restore the EPWM register state on MA35D1.
So I don't think either of these issues requires a driver change.
Best regards,
Chi-Wen