arm64: dts: qcom: sm8150: Add standalone ICE node for UFS
Subsystems (8)
v3 cover arm64: dts: qcom: sm8150: Add standalone ICE node for UFS
Hi everyone,
This series adds standalone ICE support to SM8150 (Snapdragon 855), matching newer Qualcomm platforms.
Patch 1 documents the sm8150 ICE compatible.
Patch 2 moves sm8150-ufshc to the standalone-ICE UFS binding. Patch 3 converts the UFS node to use a dedicated ICE node.
Tested on a Google Pixel 4 (google-flame): AES-256-XTS advertised, ext4 encryption supported, ICE self-test passes.
Changes in v3:
- Split bindings into two commits (compatible + standalone-ICE move).
- Drop author Tested-by from DTS patch.
- Link to v2: https://patch.msgid.link/[email protected]
Changes in v2:
- Move sm8150-ufshc to the standalone-ICE binding.
- Keep the ICE compatible sorted.
- Link to v1: https://patch.msgid.link/[email protected]
---
Andrew Gigena (3):
dt-bindings: crypto: ice: document sm8150 compatible
dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE
arm64: dts: qcom: sm8150: use standalone ICE for UFS
.../bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + .../devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 2 ++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 11 ++++------ arch/arm64/boot/dts/qcom/sm8150.dtsi | 25 ++++++++++++++-------- 4 files changed, 23 insertions(+), 16 deletions(-)
---
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
change-id: 20261104-sm8150-ice-rfc-0b4b2c035e80
Best regards,
Signature · 1 line
Andrew Gigena <[email protected]>
PATCH v3 1/3 dt-bindings: crypto: ice: document sm8150 compatible
SM8150 uses a standalone ICE node, so its compatible must be listed.
--- Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +1 -0
@@ -24,6 +24,7 @@ properties: - qcom,sc7180-inline-crypto-engine - qcom,sc7280-inline-crypto-engine - qcom,shikra-inline-crypto-engine + - qcom,sm8150-inline-crypto-engine - qcom,sm8450-inline-crypto-engine - qcom,sm8550-inline-crypto-engine - qcom,sm8650-inline-crypto-engine
Signature · 1 line
2.56.0
Re: [PATCH v3 1/3] dt-bindings: crypto: ice: document sm8150 compatible
Quoted 6 lines · Andrew Gigena
SM8150 uses a standalone ICE node, so its compatible must be listed.
Signed-off-by Andrew Gigena <[email protected]>--- Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + 1 file changed, 1 insertion(+)
Best regards,
Krzysztof
PATCH v3 2/3 dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE
In reply to Andrew GigenaSM8150 UFS uses a standalone ICE node, so its compatible belongs to the standalone-ICE binding rather than the embedded-ICE one.
--- Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 2 ++ Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 11 ++++------- 2 files changed, 6 insertions(+), 7 deletions(-)
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml +2 -0
@@ -23,6 +23,7 @@ select: - qcom,sc7280-ufshc - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc + - qcom,sm8150-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc - qcom,sm8450-ufshc
@@ -48,6 +49,7 @@ properties: - qcom,sc7280-ufshc - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc + - qcom,sm8150-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc - qcom,sm8450-ufshc
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +4 -7
@@ -23,7 +23,6 @@ select: - qcom,sm6115-ufshc - qcom,sm6125-ufshc - qcom,sm6350-ufshc - - qcom,sm8150-ufshc required: - compatible
@@ -38,7 +37,6 @@ properties: - qcom,sm6115-ufshc - qcom,sm6125-ufshc - qcom,sm6350-ufshc - - qcom,sm8150-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0
@@ -69,7 +67,6 @@ allOf: enum: - qcom,sdm845-ufshc - qcom,sm6350-ufshc - - qcom,sm8150-ufshc then: properties: clocks:
@@ -175,10 +172,10 @@ unevaluatedProperties: false examples: - | - #include <dt-bindings/clock/qcom,gcc-sm8150.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/gpio/gpio.h> - #include <dt-bindings/interconnect/qcom,sm8150.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> #include <dt-bindings/interrupt-controller/arm-gic.h> soc {
@@ -186,7 +183,7 @@ examples: #size-cells = <2>; ufs@1d84000 { - compatible = "qcom,sm8150-ufshc", "qcom,ufshc", + compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x2500>, <0x0 0x01d90000 0x0 0x8000>;
@@ -207,7 +204,7 @@ examples: vccq-max-microamp = <1200000>; power-domains = <&gcc UFS_PHY_GDSC>; - iommus = <&apps_smmu 0x300 0>; + iommus = <&apps_smmu 0x100 0xf>; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
Signature · 1 line
2.56.0
[email protected]
AI reviewRe: [PATCH v3 2/3] dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE
Thank you for your contribution! Sashiko AI review found 1 potential issue to consider: - [Medium] dt-bindings: ufs: qcom: moving sm8150-ufshc breaks existing 2-reg/9-clock DTs --
Thank you for your contribution! Sashiko AI review found 1 potential issue to consider:
- [Medium] dt-bindings: ufs: qcom: moving sm8150-ufshc breaks existing 2-reg/9-clock DTs
--
commit 830241ce50cfd60c40fb1ab69965eff9ecfda73c
Author: Andrew Gigena <[email protected]>
dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE
This commit moves the qcom,sm8150-ufshc compatible from Documentation/devicetree/bindings/ufs/qcom,ufs.yaml to Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml and updates the example in qcom,ufs.yaml to use qcom,sdm845-ufshc.
Quoted 13 lines
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml +1
-0@@ -23,6 +23,7 @@ select: - qcom,sc7280-ufshc - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc + - qcom,sm8150-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc - qcom,sm8450-ufshc
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml properties: · line 55
Quoted 7 lines
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml +1
-0@@ -48,6 +49,7 @@ properties: - qcom,sc7280-ufshc - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc + - qcom,sm8150-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc - qcom,sm8450-ufshc
[Severity: Medium]
As reported by Krzysztof Kozlowski on v2 [1], does moving qcom,sm8150-ufshc to qcom,sc7180-ufshc.yaml break dtbs_check for existing SM8150 and SA8155P device trees?
qcom,sc7180-ufshc.yaml restricts reg to maxItems: 1 and clocks to
maxItems: 8, rejecting the second ice register region and the ninth ice_core_clk clock used by the embedded-ICE representation (supported since 462c5c0aa798 ("dt-bindings: ufs: qcom,ufs: convert to dtschema")). Later commit "arm64: dts: qcom: sm8150: use standalone ICE for UFS" in this series converts the in-tree sm8150.dtsi to use a standalone ICE node, but dtbs_check fails at this commit (and across subsystem trees if UFS bindings and QCOM DTS changes are merged separately) and schema backwards compatibility with existing 2-reg/9-clock DTBs is broken.
[1] https://lore.kernel.org/r/20261106-offbeat-hawk-of-purring-50a8aa@quoll
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
Re: [PATCH v3 2/3] dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE
In reply to Andrew GigenaQuoted 9 lines · Andrew Gigena
SM8150 UFS uses a standalone ICE node, so its compatible belongs to the standalone-ICE binding rather than the embedded-ICE one.
Signed-off-by Andrew Gigena <[email protected]>--- Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 2 ++ Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 11 ++++------- 2 files changed, 6 insertions(+), 7 deletions(-)
This introduces new dtbs_check warning, which is fine but should be explained that it has no practical impact.
Best regards,
Krzysztof
PATCH v3 3/3 arm64: dts: qcom: sm8150: use standalone ICE for UFS
In reply to Andrew GigenaAlign SM8150 with the standalone ICE representation used on newer platforms instead of embedding ICE registers in the UFS node.
--- arch/arm64/boot/dts/qcom/sm8150.dtsi | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-)
arch/arm64/boot/dts/qcom/sm8150.dtsi +16 -9
@@ -2071,9 +2071,7 @@ pcie1_phy: phy@1c0e000 { ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; + reg = <0 0x01d84000 0 0x2500>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy>; phy-names = "ufsphy";
@@ -2092,8 +2090,7 @@ ufs_mem_hc: ufshc@1d84000 { "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; + "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
@@ -2102,8 +2099,7 @@ ufs_mem_hc: ufshc@1d84000 { <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <37500000 300000000>, <0 0>,
@@ -2112,8 +2108,8 @@ ufs_mem_hc: ufshc@1d84000 { <0 0>, <0 0>, <0 0>, - <0 0>, - <0 300000000>; + <0 0>; + qcom,ice = <&ice>; status = "disabled"; };
@@ -2139,6 +2135,17 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; }; + ice: crypto@1d90000 { + compatible = "qcom,sm8150-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d90000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>;
Signature · 1 line
2.56.0