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riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110

PATCH Superseded E Shattow 3 participants 8 messages Jun 6, 2025 – Jun 23, 2025

Subsystems (4)
Device tree bindings RISC-V Memory controller drivers StarFive devicetrees

v1 of 3 Superseded Latest is v3 →

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E Shattow

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#0 lore raw

cover riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110

Bring in additional downstream U-Boot boot loader changes for StarFive VisionFive2 board target (and related JH7110 common boards). There is a memory controller with no downstream dt-binding; create a basic dt-binding (and not any Linux driver) in support of the memory-controller dts node needed by U-Boot starfive_ddr.c driver. Also add bootph-pre-ram hinting to jh7110.dtsi needed at SPL boot phase.

Changes since RFC:

- Drop additional timer node from series as not strictly needed for boot.
- Add patch for starfive,jh7110-dmc binding
- Adjust ordering of bootph-pre-ram hints to follow devicetree style guide

E Shattow (3):
dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
riscv: dts: starfive: jh7110: add memory controller node
riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
loader

 .../starfive,jh7110-dmc.yaml                  | 76 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 22 ++++++
 2 files changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

base-commit: d50108706a63dfd896db42172bf9f6aebec219c5

Signature · 7 lines
2.49.0


_______________________________________________
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author
#1 lore raw

PATCH 1/3 dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

Document bindings for the JH7110 SoC DMC as implemented in downstream U-Boot driver starfive_ddr.c

Signed-off-by E Shattow <[email protected]>
---
 .../starfive,jh7110-dmc.yaml                  | 76 +++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file +76 -0
new file mode 100644
index 000000000000..299c86893db1
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 DMC
+
+maintainers:
+  - E Shattow <[email protected]>
+
+description:
+  JH7110 DMC as implemented by U-Boot boot loader driver starfive_ddr.c
+
+properties:
+  compatible:
+    items:
+      - const: starfive,jh7110-dmc
+
+  reg:
+    minItems: 2
+    maxItems: 2
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: pll1_out
+
+  clock-frequency:
+    enum: [2133, 2800]
+    default: 2133
+
+  resets:
+    minItems: 3
+    maxItems: 3
+
+  reset-names:
+    items:
+      - const: axi
+      - const: osc
+      - const: apb
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - clock-frequency
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive,jh7110-crg.h>
+    #include <dt-bindings/reset/starfive,jh7110-crg.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      memory-controller@15700000 {
+        compatible = "starfive,jh7110-dmc";
+        reg = <0x0 0x15700000 0x0 0x10000>,
+              <0x0 0x13000000 0x0 0x10000>;
+        clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+        clock-names = "pll1_out";
+        clock-frequency = <2133>;
+        resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+                 <&syscrg JH7110_SYSRST_DDR_OSC>,
+                 <&syscrg JH7110_SYSRST_DDR_APB>;
+        reset-names = "axi", "osc", "apb";
+      };
+    };
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maintainer
#2 lore raw

Re: [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

Quoted 18 lines · E Shattow

Document bindings for the JH7110 SoC DMC as implemented in downstream U-Boot driver starfive_ddr.c

Signed-off-by E Shattow <[email protected]>
---
 .../starfive,jh7110-dmc.yaml                  | 76 +++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file +3 -0
new file mode 100644
index 000000000000..299c86893db1
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---

Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml line 13

Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file +10 -0
+$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 DMC
+
+maintainers:
+  - E Shattow <[email protected]>
+
+description:
+  JH7110 DMC as implemented by U-Boot boot loader driver starfive_ddr.c

Bindings are about hardware. Explain the hardware, not drivers.

Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml line 21

Quoted 8 lines
Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file +8 -0
+
+properties:
+  compatible:
+    items:
+      - const: starfive,jh7110-dmc
+
+  reg:
+    minItems: 2

Drop

Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml line 22

Quoted 1 line
Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file +1 -0
+    maxItems: 2

Drop and list items with description instead

Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml line 33

Quoted 11 lines
Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file +11 -0
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: pll1_out
+
+  clock-frequency:
+    enum: [2133, 2800]
+    default: 2133

Drop clock-frequency. I doubt 2133 Hz is even correct... This is a legacy property, use common clock framework.

Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml line 37

Quoted 4 lines
Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file +4 -0
+
+  resets:
+    minItems: 3
+    maxItems: 3

List the items with description instead

Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file +5 -0
+
+  reset-names:
+    items:
+      - const: axi
+      - const: osc

Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml line 52

Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file +10 -0
+      - const: apb
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - clock-frequency
+  - resets
+  - reset-names

Best regards,
Krzysztof

maintainer
#3 lore raw

Re: [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

In reply to E Shattow
Quoted 2 lines · E Shattow

Document bindings for the JH7110 SoC DMC as implemented in downstream U-Boot driver starfive_ddr.c

Heh, I totally missed "downstream"... We do not add bindings for downstream. We do not care about downstream, so I should not spend my time on this.

Do not send code for downstream.

Best regards,
Krzysztof

maintainer
#4 lore raw

Re: [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

Quoted 9 lines · Krzysztof Kozlowski
Quoted 2 lines · E Shattow

Document bindings for the JH7110 SoC DMC as implemented in downstream U-Boot driver starfive_ddr.c

Heh, I totally missed "downstream"... We do not add bindings for downstream. We do not care about downstream, so I should not spend my time on this.

Do not send code for downstream.

I think that's either an accident or poor wording, there's a user for this in mainline U-Boot.

maintainer
#5 lore raw

Re: [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

Quoted 5 lines · Conor Dooley
Quoted 4 lines · Krzysztof Kozlowski
Quoted 2 lines · E Shattow

Document bindings for the JH7110 SoC DMC as implemented in downstream U-Boot driver starfive_ddr.c

Quoted 8 lines
Quoted 5 lines

Heh, I totally missed "downstream"... We do not add bindings for downstream. We do not care about downstream, so I should not spend my time on this.

Do not send code for downstream.

I think that's either an accident or poor wording, there's a user for this in mainline U-Boot.

OK, then my review stays. Commit msg should be rephrased.

In future: bindings always should be accepted prior other project starts accepting drivers (just in case if you plan to play Uno card called:
"but my driver is like that").

Best regards,
Krzysztof

author
#6 lore raw

PATCH 2/3 riscv: dts: starfive: jh7110: add memory controller node

In reply to E Shattow

add memory controller node used downstream by U-Boot boot loader.

Signed-off-by E Shattow <[email protected]>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/riscv/boot/dts/starfive/jh7110.dtsi +13 -0
index 0ba74ef04679..6fdeac3e0aff 100644
@@ -372,6 +372,19 @@ ccache: cache-controller@2010000 {
 			cache-unified;
 		};
 
+		memory-controller@15700000 {
+			compatible = "starfive,jh7110-dmc";
+			reg = <0x0 0x15700000 0x0 0x10000>,
+			      <0x0 0x13000000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+			clock-names = "pll1_out";
+			clock-frequency = <2133>;
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				 <&syscrg JH7110_SYSRST_DDR_OSC>,
+				 <&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+		};
+
 		plic: interrupt-controller@c000000 {
 			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
Signature · 1 line
2.49.0
author
#7 lore raw

PATCH 3/3 riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

In reply to E Shattow

Add bootph-pre-ram hinting to jh7110.dtsi:
- CPU interrupt controller(s)
- core local interrupt timer
- DDR memory controller
- oscillator
- syscrg clock-controller

Signed-off-by E Shattow <[email protected]>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/riscv/boot/dts/starfive/jh7110.dtsi +9 -0
index 6fdeac3e0aff..8a56e8b91b61 100644
@@ -35,6 +35,7 @@ S7_0: cpu@0 {
 
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -68,6 +69,7 @@ U74_1: cpu@1 {
 
 			cpu1_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -101,6 +103,7 @@ U74_2: cpu@2 {
 
 			cpu2_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -134,6 +137,7 @@ U74_3: cpu@3 {
 
 			cpu3_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -167,6 +171,7 @@ U74_4: cpu@4 {
 
 			cpu4_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};

@@ -321,6 +326,7 @@ mclk_ext: mclk-ext-clock {
 
 	osc: oscillator {
 		compatible = "fixed-clock";
+		bootph-pre-ram;
 		clock-output-names = "osc";
 		#clock-cells = <0>;
 	};

@@ -354,6 +360,7 @@ soc {
 		clint: timer@2000000 {
 			compatible = "starfive,jh7110-clint", "sifive,clint0";
 			reg = <0x0 0x2000000 0x0 0x10000>;
+			bootph-pre-ram;
 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 					      <&cpu1_intc 3>, <&cpu1_intc 7>,
 					      <&cpu2_intc 3>, <&cpu2_intc 7>,

@@ -376,6 +383,7 @@ memory-controller@15700000 {
 			compatible = "starfive,jh7110-dmc";
 			reg = <0x0 0x15700000 0x0 0x10000>,
 			      <0x0 0x13000000 0x0 0x10000>;
+			bootph-pre-ram;
 			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
 			clock-names = "pll1_out";
 			clock-frequency = <2133>;

@@ -893,6 +901,7 @@ qspi: spi@13010000 {
 		syscrg: clock-controller@13020000 {
 			compatible = "starfive,jh7110-syscrg";
 			reg = <0x0 0x13020000 0x0 0x10000>;
+			bootph-pre-ram;
 			clocks = <&osc>, <&gmac1_rmii_refin>,
 				 <&gmac1_rgmii_rxin>,
 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
Signature · 1 line
2.49.0