Add advanced features for Huawei hinic pmd

index f599947..fe26aad 100644
@@ -121,9 +121,7 @@ static inline int hinic_test_bit(int nr, volatile unsigned long *addr)
 {
 	int res;
 
-	rte_mb();
 	res = ((*addr) & (1UL << nr)) != 0;
-	rte_mb();
 	return res;
 }
 

@@ -227,7 +225,7 @@ static inline u16 ilog2(u32 n)
  * hinic_cpu_to_be32 - convert data to big endian 32 bit format
  * @data: the data to convert
  * @len: length of data to convert, must be Multiple of 4B
- **/
+ */
 static inline void hinic_cpu_to_be32(void *data, u32 len)
 {
 	u32 i;

@@ -243,7 +241,7 @@ static inline void hinic_cpu_to_be32(void *data, u32 len)
  * hinic_be32_to_cpu - convert data from big endian 32 bit format
  * @data: the data to convert
  * @len: length of data to convert, must be Multiple of 4B
- **/
+ */
 static inline void hinic_be32_to_cpu(void *data, u32 len)
 {
 	u32 i;

@@ -278,4 +276,34 @@ static inline int hinic_mutex_destroy(pthread_mutex_t *pthreadmutex)
 	return err;
 }
 
+static inline int hinic_mutex_lock(pthread_mutex_t *pthreadmutex)
+{
+	int err;
+
+	err = pthread_mutex_lock(pthreadmutex);
+	if (!err) {
+		return err;
+	} else if (err == EOWNERDEAD) {
+		PMD_DRV_LOG(ERR, "Mutex lock failed. (ErrorNo=%d)", errno);
+#if defined(__GLIBC__)
+#if __GLIBC_PREREQ(2, 12)
+		(void)pthread_mutex_consistent(pthreadmutex);
+#else
+		(void)pthread_mutex_consistent_np(pthreadmutex);
+#endif
+#else
+		(void)pthread_mutex_consistent(pthreadmutex);
+#endif
+	} else {
+		PMD_DRV_LOG(ERR, "Mutex lock failed. (ErrorNo=%d)", errno);
+	}
+
+	return err;
+}
+
+static inline int hinic_mutex_unlock(pthread_mutex_t *pthreadmutex)
+{
+	return pthread_mutex_unlock(pthreadmutex);
+}
+
 #endif /* _HINIC_COMPAT_H_ */

index 6c21c47..fc5bdf9 100644
@@ -7,13 +7,15 @@
 
 #include "hinic_pmd_cmd.h"
 
-#define HINIC_PAGE_SIZE_MAX	20
+#define HINIC_PAGE_SIZE_MAX		20
 
 #define HINIC_MGMT_CMD_UNSUPPORTED	0xFF
 #define HINIC_PF_SET_VF_ALREADY		0x4
 
 #define MAX_PCIE_DFX_BUF_SIZE		1024
 
+#define HINIC_DEV_BUSY_ACTIVE_FW	0xFE
+
 /* dma pool */
 struct dma_pool {
 	u32 inuse;

@@ -436,6 +438,7 @@ struct hinic_hwdev {
 	struct hinic_hwif *hwif;
 	struct cfg_mgmt_info *cfg_mgmt;
 	struct hinic_aeqs *aeqs;
+	struct hinic_mbox_func_to_func *func_to_func;
 	struct hinic_msg_pf_to_mgmt *pf_to_mgmt;
 	struct hinic_cmdqs *cmdqs;
 	struct hinic_nic_io *nic_io;

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index fe26aad..e4a7f12 100644
@@ -113,7 +113,7 @@
 #define GFP_KERNEL		RTE_MEMZONE_IOVA_CONTIG
 #define HINIC_PAGE_SHIFT	12
 #define HINIC_PAGE_SIZE		RTE_PGSIZE_4K
-#define HINIC_MEM_ALLOC_ALIGNE_MIN	8
+#define HINIC_MEM_ALLOC_ALIGN_MIN	8
 
 #define HINIC_PAGE_SIZE_DPDK	6
 

@@ -168,7 +168,7 @@ struct dma_pool *dma_pool_create(const char *name, void *dev, size_t size,
 void *dma_pool_alloc(struct pci_pool *pool, int flags, dma_addr_t *dma_addr);
 void dma_pool_free(struct pci_pool *pool, void *vaddr, dma_addr_t dma);
 
-#define kzalloc(size, flag) rte_zmalloc(NULL, size, HINIC_MEM_ALLOC_ALIGNE_MIN)
+#define kzalloc(size, flag) rte_zmalloc(NULL, size, HINIC_MEM_ALLOC_ALIGN_MIN)
 #define kzalloc_aligned(size, flag) rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE)
 #define kfree(ptr)            rte_free(ptr)
 

@@ -221,38 +221,6 @@ static inline u16 ilog2(u32 n)
 	return res;
 }
 
-/**
- * hinic_cpu_to_be32 - convert data to big endian 32 bit format
- * @data: the data to convert
- * @len: length of data to convert, must be Multiple of 4B
- */
-static inline void hinic_cpu_to_be32(void *data, u32 len)
-{
-	u32 i;
-	u32 *mem = (u32 *)data;
-
-	for (i = 0; i < (len >> 2); i++) {
-		*mem = cpu_to_be32(*mem);
-		mem++;
-	}
-}
-
-/**
- * hinic_be32_to_cpu - convert data from big endian 32 bit format
- * @data: the data to convert
- * @len: length of data to convert, must be Multiple of 4B
- */
-static inline void hinic_be32_to_cpu(void *data, u32 len)
-{
-	u32 i;
-	u32 *mem = (u32 *)data;
-
-	for (i = 0; i < (len >> 2); i++) {
-		*mem = be32_to_cpu(*mem);
-		mem++;
-	}
-}
-
 static inline int hinic_mutex_init(pthread_mutex_t *pthreadmutex,
 					const pthread_mutexattr_t *mattr)
 {

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index 61537b1..aa883e0 100644
@@ -8,6 +8,7 @@
 #include "hinic_pmd_mgmt.h"
 #include "hinic_pmd_eqs.h"
 #include "hinic_pmd_cfg.h"
+#include "hinic_pmd_mbox.h"
 
 bool hinic_support_nic(struct hinic_hwdev *hwdev, struct nic_service_cap *cap)
 {

@@ -122,6 +123,10 @@ static void hinic_parse_pub_res_cap(struct service_cap *cap,
 		cap->vf_id_start = dev_cap->vf_id_start;
 		cap->max_sqs = dev_cap->nic_max_sq + 1;
 		cap->max_rqs = dev_cap->nic_max_rq + 1;
+	} else {
+		cap->max_vf = 0;
+		cap->max_sqs = dev_cap->nic_max_sq;
+		cap->max_rqs = dev_cap->nic_max_rq;
 	}
 
 	cap->chip_svc_type = CFG_SVC_NIC_BIT0;

@@ -180,6 +185,28 @@ static int get_cap_from_fw(struct hinic_hwdev *dev, enum func_type type)
 	return 0;
 }
 
+static int get_cap_from_pf(struct hinic_hwdev *dev, enum func_type type)
+{
+	int err;
+	u16 in_len, out_len;
+	struct hinic_dev_cap dev_cap;
+
+	memset(&dev_cap, 0, sizeof(dev_cap));
+	in_len = sizeof(dev_cap);
+	out_len = in_len;
+	err = hinic_mbox_to_pf(dev, HINIC_MOD_CFGM, HINIC_CFG_MBOX_CAP,
+			       &dev_cap, in_len, &dev_cap, &out_len,
+			       CFG_MAX_CMD_TIMEOUT);
+	if (err || dev_cap.mgmt_msg_head.status || !out_len) {
+		PMD_DRV_LOG(ERR, "Get capability from PF failed, err: %d, status: %d, out_len: %d",
+				err, dev_cap.mgmt_msg_head.status, out_len);
+		return -EFAULT;
+	}
+
+	parse_dev_cap(dev, &dev_cap, type);
+	return 0;
+}
+
 static int get_dev_cap(struct hinic_hwdev *dev)
 {
 	int err;

@@ -194,6 +221,14 @@ static int get_dev_cap(struct hinic_hwdev *dev)
 			return err;
 		}
 		break;
+	case TYPE_VF:
+		err = get_cap_from_pf(dev, type);
+		if (err) {
+			PMD_DRV_LOG(ERR, "Get VF capability failed, err: %d",
+					err);
+			return err;
+		}
+		break;
 	default:
 		PMD_DRV_LOG(ERR, "Unsupported PCI function type");
 		return -EINVAL;

index 7a9e9f6..c8750b8 100644
@@ -25,6 +25,12 @@ enum hinic_mod_type {
 	HINIC_MOD_MAX	= 15
 };
 
+/* only used by VFD communicating with PFD to register or unregister,
+ * command mode type is HINIC_MOD_L2NIC
+ */
+#define HINIC_PORT_CMD_VF_REGISTER	0x0
+#define HINIC_PORT_CMD_VF_UNREGISTER	0x1
+
 /* cmd of mgmt CPU message for NIC module */
 enum hinic_port_cmd {
 	HINIC_PORT_CMD_MGMT_RESET		= 0x0,

@@ -416,12 +422,12 @@ enum hinic_pf_status {
 };
 
 /* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */
-#define HINIC_DB_DWQE_SIZE       0x00080000
+#define HINIC_DB_DWQE_SIZE	0x00080000
 
-/* db/dwqe page size: 4K */
-#define HINIC_DB_PAGE_SIZE		0x00001000ULL
+/* db page size: 4K */
+#define HINIC_DB_PAGE_SIZE	0x00001000ULL
 
-#define HINIC_DB_MAX_AREAS         (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)
+#define HINIC_DB_MAX_AREAS	(HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)
 
 #define HINIC_PCI_MSIX_ENTRY_SIZE			16
 #define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL		12

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index fc5bdf9..ac21947 100644
@@ -18,7 +18,7 @@
 
 /* dma pool */
 struct dma_pool {
-	u32 inuse;
+	rte_atomic32_t inuse;
 	size_t elem_size;
 	size_t align;
 	size_t boundary;

@@ -485,4 +485,8 @@ void hinic_hilink_async_event_handle(struct hinic_hwdev *hwdev, u8 cmd,
 
 int hinic_set_pagesize(void *hwdev, u8 page_size);
 
+void hinic_cpu_to_be32(void *data, u32 len);
+
+void hinic_be32_to_cpu(void *data, u32 len);
+
 #endif /* _HINIC_PMD_HWDEV_H_ */

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index c1289b5..6752587 100644
@@ -31,7 +31,7 @@ enum hinic_msix_state {
 	HINIC_MSIX_DISABLE,
 };
 
-/* Defines the IRQ information structure*/
+/* Defines the IRQ information structure */
 struct irq_info {
 	u16 msix_entry_idx; /* IRQ corresponding index number */
 	u32 irq_id;         /* the IRQ number from OS */

@@ -59,11 +59,11 @@ struct hinic_func_attr {
 
 	u8			ppf_idx;
 
-	u16			num_irqs;		/* max: 2 ^ 15 */
-	u8			num_aeqs;		/* max: 2 ^ 3 */
-	u8			num_ceqs;		/* max: 2 ^ 7 */
+	u16			num_irqs;	/* max: 2 ^ 15 */
+	u8			num_aeqs;	/* max: 2 ^ 3 */
+	u8			num_ceqs;	/* max: 2 ^ 7 */
 
-	u8			num_dma_attr;		/* max: 2 ^ 6 */
+	u8			num_dma_attr;	/* max: 2 ^ 6 */
 
 	u16			global_vf_id_of_pf;
 };

@@ -104,6 +104,9 @@ static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg)
 
 void hinic_free_db_addr(void *hwdev, void __iomem *db_base);
 
+int wait_until_doorbell_flush_states(struct hinic_hwif *hwif,
+					enum hinic_doorbell_ctrl states);
+
 void hinic_set_msix_state(void *hwdev, u16 msix_idx,
 			  enum hinic_msix_state flag);
 

@@ -116,4 +119,6 @@ void hinic_misx_intr_clear_resend_bit(void *hwdev, u16 msix_idx,
 
 void hinic_hwif_res_free(struct hinic_hwdev *hwdev);
 
+u8 hinic_dma_attr_entry_num(void *hwdev);
+
 #endif /* _HINIC_PMD_HWIF_H_ */

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index 7804708..cc18843 100644
@@ -82,7 +82,7 @@ struct hinic_msg_pf_to_mgmt {
 	struct hinic_hwdev		*hwdev;
 
 	/* mutex for sync message */
-	pthread_mutex_t			sync_msg_lock;
+	pthread_mutex_t			sync_msg_mutex;
 
 	void				*async_msg_buf;
 	void				*sync_msg_buf;

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index 174b40f..dcb9602 100644
@@ -655,4 +655,8 @@ int hinic_set_link_status_follow(void *hwdev,
 
 int hinic_clear_phy_port_stats(struct hinic_hwdev *hwdev);
 
+int hinic_vf_func_init(struct hinic_hwdev *hwdev);
+
+void hinic_vf_func_free(struct hinic_hwdev *hwdev);
+
 #endif /* _HINIC_PMD_NICCFG_H_ */

index 248211f..f6cc033 100644
@@ -442,7 +442,7 @@ static int clean_qp_offload_ctxt(struct hinic_nic_io *nic_io)
  * @rx_buf_sz: receive buffer size
  * @return
  *   hw rx buffer size
- **/
+ */
 static u16 get_hw_rx_buf_size(u32 rx_buf_sz)
 {
 	u16 num_hw_types = sizeof(hinic_hw_rx_buf_size)

@@ -466,7 +466,7 @@ static u16 get_hw_rx_buf_size(u32 rx_buf_sz)
  * @sq_depth: the depth of transmit queue
  * @rx_buf_sz: receive buffer size from app
  * Return: 0 on success, negative error value otherwise.
- **/
+ */
 static int
 hinic_set_root_ctxt(void *hwdev, u16 rq_depth, u16 sq_depth, int rx_buf_sz)
 {

@@ -495,7 +495,7 @@ static u16 get_hw_rx_buf_size(u32 rx_buf_sz)
  * @return
  *   0 on success,
  *   negative error value otherwise.
- **/
+ */
 static int hinic_clean_root_ctxt(void *hwdev)
 {
 	struct hinic_root_ctxt root_ctxt;

@@ -618,6 +618,12 @@ static int hinic_init_nic_hwdev(struct hinic_hwdev *hwdev)
 		goto err_init_nic_hwdev;
 	}
 
+	err = hinic_vf_func_init(hwdev);
+	if (err) {
+		PMD_DRV_LOG(ERR, "Failed to init nic mbox");
+		goto err_init_nic_hwdev;
+	}
+
 	err = hinic_set_fast_recycle_mode(hwdev, RECYCLE_MODE_DPDK);
 	if (err) {
 		PMD_DRV_LOG(ERR, "Failed to set fast recycle mode");

@@ -632,6 +638,7 @@ static int hinic_init_nic_hwdev(struct hinic_hwdev *hwdev)
 
 static void hinic_free_nic_hwdev(struct hinic_hwdev *hwdev)
 {
+	hinic_vf_func_free(hwdev);
 	hwdev->nic_io = NULL;
 }
 

@@ -861,7 +868,7 @@ void hinic_deinit_nicio(struct hinic_hwdev *hwdev)
  * @return
  *   0 on success,
  *   negative error value otherwise.
- **/
+ */
 int hinic_convert_rx_buf_size(u32 rx_buf_sz, u32 *match_sz)
 {
 	u32 i, num_hw_types, best_match_sz;

index 487e440..9a487d0 100644
@@ -217,7 +217,7 @@ struct hinic_nic_io {
 	u16			vhd_mode;
 
 	struct hinic_qp		*qps;
-	/* sq ci mem base addr of the function*/
+	/* sq ci mem base addr of the function */
 	void			*ci_vaddr_base;
 	dma_addr_t		ci_dma_base;
 

@@ -229,7 +229,6 @@ struct hinic_sq_db {
 	u32	db_info;
 };
 
-
 int hinic_init_qp_ctxts(struct hinic_hwdev *hwdev);
 
 void hinic_free_qp_ctxts(struct hinic_hwdev *hwdev);

index d3bbc3d..0a20ade 100644
@@ -1436,3 +1436,38 @@ int hinic_flush_qp_res(void *hwdev)
 
 	return 0;
 }
+
+/**
+ * hinic_vf_get_default_cos - Get default cos of VF.
+ *
+ * @param hwdev
+ *   The hardware interface of a nic device.
+ * @param cos_id
+ *   Cos value.
+ *
+ * @return
+ *   0 on success.
+ *   negative error value otherwise.
+ */
+int hinic_vf_get_default_cos(struct hinic_hwdev *hwdev, u8 *cos_id)
+{
+	struct hinic_vf_default_cos vf_cos;
+	u16 out_size = sizeof(vf_cos);
+	int err;
+
+	memset(&vf_cos, 0, sizeof(vf_cos));
+	vf_cos.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;
+
+	err = hinic_msg_to_mgmt_sync(hwdev, HINIC_MOD_L2NIC,
+				     HINIC_PORT_CMD_GET_VF_COS, &vf_cos,
+				     sizeof(vf_cos), &vf_cos,
+				     &out_size, 0);
+	if (err || !out_size || vf_cos.mgmt_msg_head.status) {
+		PMD_DRV_LOG(ERR, "Get VF default cos failed, err: %d, status: 0x%x, out size: 0x%x",
+			err, vf_cos.mgmt_msg_head.status, out_size);
+		return -EFAULT;
+	}
+	*cos_id = vf_cos.state.default_cos;
+
+	return 0;
+}

index dcb9602..94371bb 100644
@@ -562,6 +562,18 @@ struct hinic_clear_qp_resource {
 	u16	rsvd1;
 };
 
+struct hinic_dcb_state {
+	u8 dcb_on;
+	u8 default_cos;
+	u8 up_cos[8];
+};
+
+struct hinic_vf_default_cos {
+	struct hinic_mgmt_msg_head mgmt_msg_head;
+
+	struct hinic_dcb_state state;
+};
+
 /* set physical port Anti-Attack rate */
 struct hinic_port_anti_attack_rate {
 	struct hinic_mgmt_msg_head mgmt_msg_head;

@@ -659,4 +671,6 @@ int hinic_set_link_status_follow(void *hwdev,
 
 void hinic_vf_func_free(struct hinic_hwdev *hwdev);
 
+int hinic_vf_get_default_cos(struct hinic_hwdev *hwdev, u8 *cos_id);
+
 #endif /* _HINIC_PMD_NICCFG_H_ */

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index c8750b8..5c38b5f 100644
@@ -140,6 +140,7 @@ enum hinic_port_cmd {
 
 	HINIC_PORT_CMD_SET_VHD_CFG		= 0xF7,
 	HINIC_PORT_CMD_SET_LINK_FOLLOW		= 0xF8,
+	HINIC_PORT_CMD_SET_VLAN_FILTER		= 0xFF
 };
 
 /* cmd of mgmt CPU message for HW module */

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index 94371bb..d19a834 100644
@@ -380,6 +380,29 @@ struct hinic_mtu {
 	u32	mtu;
 };
 
+struct hinic_vlan_config {
+	struct hinic_mgmt_msg_head mgmt_msg_head;
+
+	u16	func_id;
+	u16	vlan_id;
+};
+
+struct hinic_vlan_filter {
+	struct hinic_mgmt_msg_head mgmt_msg_head;
+
+	u16	func_id;
+	u8	rsvd1[2];
+	u32	vlan_filter_ctrl;
+};
+
+struct hinic_vlan_offload {
+	struct hinic_mgmt_msg_head mgmt_msg_head;
+
+	u16	func_id;
+	u8	vlan_rx_offload;
+	u8	rsvd1[5];
+};
+
 struct hinic_get_link {
 	struct hinic_mgmt_msg_head mgmt_msg_head;
 

@@ -597,6 +620,12 @@ int hinic_update_mac(void *hwdev, u8 *old_mac, u8 *new_mac, u16 vlan_id,
 
 int hinic_set_port_mtu(void *hwdev, u32 new_mtu);
 
+int hinic_add_remove_vlan(void *hwdev, u16 vlan_id, u16 func_id, bool add);
+
+int hinic_config_vlan_filter(void *hwdev, u32 vlan_filter_ctrl);
+
+int hinic_set_rx_vlan_offload(void *hwdev, u8 en);
+
 int hinic_set_vport_enable(void *hwdev, bool enable);
 
 int hinic_set_port_enable(void *hwdev, bool enable);

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index 4aeddc2..66eaf20 100644
@@ -11,12 +11,12 @@
 #include "base/hinic_compat.h"
 #include "base/hinic_pmd_cfg.h"
 
-#define HINIC_DEV_NAME_LEN	(32)
-#define HINIC_MAX_RX_QUEUES	(64)
+#define HINIC_DEV_NAME_LEN	32
+#define HINIC_MAX_RX_QUEUES	64
 
 /* mbuf pool for copy invalid mbuf segs */
-#define HINIC_COPY_MEMPOOL_DEPTH (128)
-#define HINIC_COPY_MBUF_SIZE     (4096)
+#define HINIC_COPY_MEMPOOL_DEPTH	128
+#define HINIC_COPY_MBUF_SIZE		4096
 
 #define SIZE_8BYTES(size)	(ALIGN((u32)(size), 8) >> 3)
 

@@ -31,6 +31,9 @@
 #define HINIC_TXD_ALIGN                 1
 #define HINIC_RXD_ALIGN                 1
 
+#define HINIC_UINT32_BIT_SIZE      (CHAR_BIT * sizeof(uint32_t))
+#define HINIC_VFTA_SIZE            (4096 / HINIC_UINT32_BIT_SIZE)
+
 enum hinic_dev_status {
 	HINIC_DEV_INIT,
 	HINIC_DEV_CLOSE,

@@ -54,10 +57,12 @@ struct hinic_nic_dev {
 	u8 num_rss;
 	u8 rx_queue_list[HINIC_MAX_RX_QUEUES];
 
+	u32 vfta[HINIC_VFTA_SIZE];	/* VLAN bitmap */
+
 	/* info */
 	unsigned int flags;
 	struct nic_service_cap nic_cap;
-	u32 rx_mode_status;	/* promisc allmulticast */
+	u32 rx_mode_status;	/* promisc or allmulticast */
 	unsigned long dev_status;
 
 	/* dpdk only */

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index 66eaf20..f7a1167 100644
@@ -20,9 +20,6 @@
 
 #define SIZE_8BYTES(size)	(ALIGN((u32)(size), 8) >> 3)
 
-#define HINIC_PKTLEN_TO_MTU(pktlen)	\
-	((pktlen) - (ETH_HLEN + ETH_CRC_LEN))
-
 #define HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev) \
 	((struct hinic_nic_dev *)(dev)->data->dev_private)
 

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index f7a1167..b4f93ad 100644
@@ -56,6 +56,8 @@ struct hinic_nic_dev {
 
 	u32 vfta[HINIC_VFTA_SIZE];	/* VLAN bitmap */
 
+	struct rte_ether_addr default_addr;
+	struct rte_ether_addr *mc_list;
 	/* info */
 	unsigned int flags;
 	struct nic_service_cap nic_cap;

index 5c38b5f..6b3dcf3 100644
@@ -140,6 +140,8 @@ enum hinic_port_cmd {
 
 	HINIC_PORT_CMD_SET_VHD_CFG		= 0xF7,
 	HINIC_PORT_CMD_SET_LINK_FOLLOW		= 0xF8,
+	HINIC_PORT_CMD_Q_FILTER			= 0xFC,
+	HINIC_PORT_CMD_TCAM_FILTER		= 0xFE,
 	HINIC_PORT_CMD_SET_VLAN_FILTER		= 0xFF
 };
 

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index b4f93ad..58a38d9 100644
@@ -38,6 +38,30 @@ enum hinic_dev_status {
 	HINIC_DEV_INTR_EN,
 };
 
+/* Information about the fdir mode. */
+struct hinic_hw_fdir_mask {
+	uint32_t src_ipv4_mask;
+	uint32_t dst_ipv4_mask;
+	uint16_t src_port_mask;
+	uint16_t dst_port_mask;
+};
+
+/* Flow Director attribute */
+struct hinic_atr_input {
+	u32 dst_ip;
+	u32 src_ip;
+	u16 src_port;
+	u16 dst_port;
+};
+
+struct hinic_fdir_rule {
+	struct hinic_hw_fdir_mask mask;
+	struct hinic_atr_input hinic_fdir; /* key of fdir filter */
+	uint8_t queue; /* queue assigned when matched */
+};
+
+extern const struct rte_flow_ops hinic_flow_ops;
+
 /* hinic nic_device */
 struct hinic_nic_dev {
 	/* hardware device */

1,172 lines not on this page · raw message

index 58a38d9..93cd6a7 100644
@@ -38,6 +38,57 @@ enum hinic_dev_status {
 	HINIC_DEV_INTR_EN,
 };
 
+#define HINIC_MAX_Q_FILTERS	64 /* hinic just support 64 filter types */
+#define HINIC_PKT_TYPE_FIND_ID(pkt_type) ((pkt_type) - HINIC_MAX_Q_FILTERS)
+
+/* 5tuple filter info */
+struct hinic_5tuple_filter_info {
+	uint32_t dst_ip;
+	uint32_t src_ip;
+	uint16_t dst_port;
+	uint16_t src_port;
+	uint8_t proto; /* l4 protocol. */
+	/*
+	 * seven levels (001b-111b), 111b is highest,
+	 * used when more than one filter matches.
+	 */
+	uint8_t priority;
+	uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
+		src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
+		dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
+		src_port_mask:1, /* if mask is 1b, do not compare src port. */
+		proto_mask:1; /* if mask is 1b, do not compare protocol. */
+};
+
+/* 5tuple filter structure */
+struct hinic_5tuple_filter {
+	TAILQ_ENTRY(hinic_5tuple_filter) entries;
+	uint16_t index;       /* the index of 5tuple filter */
+	struct hinic_5tuple_filter_info filter_info;
+	uint16_t queue;       /* rx queue assigned to */
+};
+
+TAILQ_HEAD(hinic_5tuple_filter_list, hinic_5tuple_filter);
+
+/*
+ * If this filter is added by configuration,
+ * it should not be removed.
+ */
+struct hinic_pkt_filter {
+	uint16_t pkt_proto;
+	uint8_t qid;
+	bool	enable;
+};
+
+/* Structure to store filters' info. */
+struct hinic_filter_info {
+	uint8_t pkt_type;
+	uint8_t qid;
+	uint64_t type_mask;  /* Bit mask for every used filter */
+	struct hinic_5tuple_filter_list fivetuple_list;
+	struct hinic_pkt_filter pkt_filters[HINIC_MAX_Q_FILTERS];
+};
+
 /* Information about the fdir mode. */
 struct hinic_hw_fdir_mask {
 	uint32_t src_ipv4_mask;

@@ -60,6 +111,26 @@ struct hinic_fdir_rule {
 	uint8_t queue; /* queue assigned when matched */
 };
 
+/* ntuple filter list structure */
+struct hinic_ntuple_filter_ele {
+	TAILQ_ENTRY(hinic_ntuple_filter_ele) entries;
+	struct rte_eth_ntuple_filter filter_info;
+};
+
+struct rte_flow {
+	enum rte_filter_type filter_type;
+	void *rule;
+};
+
+/* hinic_flow memory list structure */
+struct hinic_flow_mem {
+	TAILQ_ENTRY(hinic_flow_mem) entries;
+	struct rte_flow *flow;
+};
+
+TAILQ_HEAD(hinic_ntuple_filter_list, hinic_ntuple_filter_ele);
+TAILQ_HEAD(hinic_flow_mem_list, hinic_flow_mem);
+
 extern const struct rte_flow_ops hinic_flow_ops;
 
 /* hinic nic_device */

@@ -94,6 +165,10 @@ struct hinic_nic_dev {
 	 * vf: the same with associate pf
 	 */
 	u32 default_cos;
+
+	struct hinic_filter_info    filter;
+	struct hinic_ntuple_filter_list filter_ntuple_list;
+	struct hinic_flow_mem_list hinic_flow_list;
 };
 
 #endif /* _HINIC_PMD_ETHDEV_H_ */

705 lines not on this page · raw message

index 93cd6a7..b7fcef6 100644
@@ -117,6 +117,18 @@ struct hinic_ntuple_filter_ele {
 	struct rte_eth_ntuple_filter filter_info;
 };
 
+/* ethertype filter list structure */
+struct hinic_ethertype_filter_ele {
+	TAILQ_ENTRY(hinic_ethertype_filter_ele) entries;
+	struct rte_eth_ethertype_filter filter_info;
+};
+
+/* fdir filter list structure */
+struct hinic_fdir_rule_ele {
+	TAILQ_ENTRY(hinic_fdir_rule_ele) entries;
+	struct hinic_fdir_rule filter_info;
+};
+
 struct rte_flow {
 	enum rte_filter_type filter_type;
 	void *rule;

@@ -129,6 +141,8 @@ struct hinic_flow_mem {
 };
 
 TAILQ_HEAD(hinic_ntuple_filter_list, hinic_ntuple_filter_ele);
+TAILQ_HEAD(hinic_ethertype_filter_list, hinic_ethertype_filter_ele);
+TAILQ_HEAD(hinic_fdir_rule_filter_list, hinic_fdir_rule_ele);
 TAILQ_HEAD(hinic_flow_mem_list, hinic_flow_mem);
 
 extern const struct rte_flow_ops hinic_flow_ops;

@@ -168,6 +182,8 @@ struct hinic_nic_dev {
 
 	struct hinic_filter_info    filter;
 	struct hinic_ntuple_filter_list filter_ntuple_list;
+	struct hinic_ethertype_filter_list filter_ethertype_list;
+	struct hinic_fdir_rule_filter_list filter_fdir_rule_list;
 	struct hinic_flow_mem_list hinic_flow_list;
 };
 

474 lines not on this page · raw message

index f2f0fa9..d0bcbe5 100644
@@ -341,6 +341,9 @@ static int hinic_dev_configure(struct rte_eth_dev *dev)
 		return err;
 	}
 
+	/*clear fdir filter flag in function table*/
+	hinic_free_fdir_filter(nic_dev);
+
 	return HINIC_OK;
 }
 

@@ -1115,6 +1118,8 @@ static void hinic_dev_stop(struct rte_eth_dev *dev)
 	/* clean root context */
 	hinic_free_qp_ctxts(nic_dev->hwdev);
 
+	hinic_free_fdir_filter(nic_dev);
+
 	/* free mbuf */
 	hinic_free_all_rx_mbuf(dev);
 	hinic_free_all_tx_mbuf(dev);

@@ -2816,6 +2821,7 @@ static int hinic_func_init(struct rte_eth_dev *eth_dev)
 	struct rte_pci_device *pci_dev;
 	struct rte_ether_addr *eth_addr;
 	struct hinic_nic_dev *nic_dev;
+	struct hinic_filter_info *filter_info;
 	u32 mac_size;
 	int rc;
 

@@ -2907,6 +2913,16 @@ static int hinic_func_init(struct rte_eth_dev *eth_dev)
 	}
 	hinic_set_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status);
 
+	/* initialize filter info */
+	filter_info = &nic_dev->filter;
+	memset(filter_info, 0, sizeof(struct hinic_filter_info));
+	/* initialize 5tuple filter list */
+	TAILQ_INIT(&filter_info->fivetuple_list);
+	TAILQ_INIT(&nic_dev->filter_ntuple_list);
+	TAILQ_INIT(&nic_dev->filter_ethertype_list);
+	TAILQ_INIT(&nic_dev->filter_fdir_rule_list);
+	TAILQ_INIT(&nic_dev->hinic_flow_list);
+
 	hinic_set_bit(HINIC_DEV_INIT, &nic_dev->dev_status);
 	PMD_DRV_LOG(INFO, "Initialize %s in primary successfully",
 		    eth_dev->data->name);

index b7fcef6..dd96667 100644
@@ -173,7 +173,6 @@ struct hinic_nic_dev {
 	u32 rx_mode_status;	/* promisc or allmulticast */
 	unsigned long dev_status;
 
-	/* dpdk only */
 	char proc_dev_name[HINIC_DEV_NAME_LEN];
 	/* PF0->COS4, PF1->COS5, PF2->COS6, PF3->COS7,
 	 * vf: the same with associate pf

@@ -187,4 +186,6 @@ struct hinic_nic_dev {
 	struct hinic_flow_mem_list hinic_flow_list;
 };
 
+void hinic_free_fdir_filter(struct hinic_nic_dev *nic_dev);
+
 #endif /* _HINIC_PMD_ETHDEV_H_ */

154 lines not on this page · raw message

index 6b3dcf3..55d4292 100644
@@ -119,6 +119,8 @@ enum hinic_port_cmd {
 	HINIC_PORT_CMD_SET_IPSU_MAC		= 0xcb,
 	HINIC_PORT_CMD_GET_IPSU_MAC		= 0xcc,
 
+	HINIC_PORT_CMD_SET_XSFP_STATUS		= 0xD4,
+
 	HINIC_PORT_CMD_GET_LINK_MODE		= 0xD9,
 	HINIC_PORT_CMD_SET_SPEED		= 0xDA,
 	HINIC_PORT_CMD_SET_AUTONEG		= 0xDB,

index 53d981b..9f23fdd 100644
@@ -1613,6 +1613,44 @@ int hinic_get_link_mode(void *hwdev, u32 *supported, u32 *advertised)
 }
 
 /**
+ * hinic_set_xsfp_tx_status - Enable or disable the fiber in
+ * tx direction when set link up or down.
+ *
+ * @param hwdev
+ *   The hardware interface of a nic device.
+ * @param enable
+ *   Enable or Disable.
+ *
+ * @return
+ *   0 on success.
+ *   negative error value otherwise.
+ */
+int hinic_set_xsfp_tx_status(void *hwdev, bool enable)
+{
+	struct hinic_set_xsfp_status xsfp_status;
+	u16 out_size = sizeof(struct hinic_set_xsfp_status);
+	int err;
+
+	memset(&xsfp_status, 0, sizeof(xsfp_status));
+	xsfp_status.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;
+	xsfp_status.port_id = hinic_global_func_id(hwdev);
+	xsfp_status.xsfp_tx_dis = ((enable == 0) ? 1 : 0);
+
+	err = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_XSFP_STATUS,
+		&xsfp_status, sizeof(struct hinic_set_xsfp_status),
+		&xsfp_status, &out_size);
+	if (err || !out_size || xsfp_status.mgmt_msg_head.status) {
+		PMD_DRV_LOG(ERR,
+			"Failed to %s port xsfp status, err: %d, status: 0x%x, out size: 0x%x\n",
+			enable ? "Disable" : "Enable", err,
+			xsfp_status.mgmt_msg_head.status, out_size);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/**
  * hinic_flush_qp_res - Flush tx && rx chip resources in case of set vport
  * fake failed when device start.
  *

index e8ce332..beab630 100644
@@ -578,6 +578,13 @@ struct hinic_link_mode_cmd {
 	u16	advertised;
 };
 
+struct hinic_set_xsfp_status {
+	struct hinic_mgmt_msg_head mgmt_msg_head;
+
+	u32 port_id;
+	u32 xsfp_tx_dis;	/* 0: tx enable; 1: tx disable */
+};
+
 struct hinic_clear_qp_resource {
 	struct hinic_mgmt_msg_head mgmt_msg_head;
 

@@ -807,6 +814,8 @@ int hinic_set_link_status_follow(void *hwdev,
 
 int hinic_get_link_mode(void *hwdev, u32 *supported, u32 *advertised);
 
+int hinic_set_xsfp_tx_status(void *hwdev, bool enable);
+
 int hinic_flush_qp_res(void *hwdev);
 
 int hinic_init_function_table(void *hwdev, u16 rx_buf_sz);

74 lines not on this page · raw message

index 55d4292..e0633bd 100644
@@ -85,6 +85,8 @@ enum hinic_port_cmd {
 	HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE	= 0x4a,
 	HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE,
 
+	HINIC_PORT_CMD_GET_MGMT_VERSION		= 0x58,
+
 	HINIC_PORT_CMD_GET_PORT_TYPE		= 0x5b,
 
 	HINIC_PORT_CMD_GET_VPORT_ENABLE		= 0x5c,

index 9f23fdd..2dc431e 100644
@@ -1293,6 +1293,46 @@ int hinic_set_rx_mode(void *hwdev, u32 enable)
 	return 0;
 }
 
+/**
+ * hinic_get_mgmt_version - Get mgmt module version from chip.
+ *
+ * @param hwdev
+ *   The hardware interface of a nic device.
+ * @param fw
+ *   Firmware version.
+ *
+ * @return
+ *   0 on success.
+ *   negative error value otherwise.
+ */
+int hinic_get_mgmt_version(void *hwdev, char *fw)
+{
+	struct hinic_version_info fw_ver;
+	u16 out_size = sizeof(fw_ver);
+	int err;
+
+	if (!hwdev || !fw) {
+		PMD_DRV_LOG(ERR, "Hwdev or fw is NULL");
+		return -EINVAL;
+	}
+
+	memset(&fw_ver, 0, sizeof(fw_ver));
+	fw_ver.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;
+
+	err = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_GET_MGMT_VERSION,
+				     &fw_ver, sizeof(fw_ver), &fw_ver,
+				     &out_size);
+	if (err || !out_size || fw_ver.mgmt_msg_head.status) {
+		PMD_DRV_LOG(ERR, "Failed to get mgmt version, err: %d, status: 0x%x, out size: 0x%x\n",
+			err, fw_ver.mgmt_msg_head.status, out_size);
+		return -EINVAL;
+	}
+
+	snprintf(fw, HINIC_MGMT_VERSION_MAX_LEN, "%s", fw_ver.ver);
+
+	return 0;
+}
+
 int hinic_set_rx_csum_offload(void *hwdev, u32 en)
 {
 	struct hinic_checksum_offload rx_csum_cfg;

index beab630..b9e037e 100644
@@ -471,6 +471,17 @@ struct hinic_rx_mode_config {
 	u32	rx_mode;
 };
 
+#define HINIC_MGMT_VERSION_MAX_LEN	32
+#define HINIC_COMPILE_TIME_LEN		20
+#define HINIC_FW_VERSION_NAME		16
+
+struct hinic_version_info {
+	struct hinic_mgmt_msg_head mgmt_msg_head;
+
+	u8 ver[HINIC_FW_VERSION_NAME];
+	u8 time[HINIC_COMPILE_TIME_LEN];
+};
+
 /* rss */
 struct nic_rss_indirect_tbl {
 	u32 group_index;

@@ -807,6 +818,8 @@ int hinic_get_rss_type(void *hwdev, u32 tmpl_idx,
 
 int hinic_set_rx_mode(void *hwdev, u32 enable);
 
+int hinic_get_mgmt_version(void *hwdev, char *fw);
+
 int hinic_set_rx_csum_offload(void *hwdev, u32 en);
 
 int hinic_set_link_status_follow(void *hwdev,

index ea39ff0..48ec467 100644
@@ -752,6 +752,27 @@ static void hinic_get_speed_capa(struct rte_eth_dev *dev, uint32_t *speed_capa)
 	return 0;
 }
 
+static int hinic_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
+				size_t fw_size)
+{
+	struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
+	char fw_ver[HINIC_MGMT_VERSION_MAX_LEN] = {0};
+	int err;
+
+	err = hinic_get_mgmt_version(nic_dev->hwdev, fw_ver);
+	if (err) {
+		PMD_DRV_LOG(ERR, "Failed to get fw version\n");
+		return -EINVAL;
+	}
+
+	if (fw_size < strlen(fw_ver) + 1)
+		return (strlen(fw_ver) + 1);
+
+	snprintf(fw_version, fw_size, "%s", fw_ver);
+
+	return 0;
+}
+
 static int hinic_config_rx_mode(struct hinic_nic_dev *nic_dev, u32 rx_mode_ctrl)
 {
 	int err;

@@ -2813,6 +2834,7 @@ static void hinic_dev_close(struct rte_eth_dev *dev)
 static const struct eth_dev_ops hinic_pmd_ops = {
 	.dev_configure                 = hinic_dev_configure,
 	.dev_infos_get                 = hinic_dev_infos_get,
+	.fw_version_get                = hinic_fw_version_get,
 	.rx_queue_setup                = hinic_rx_queue_setup,
 	.tx_queue_setup                = hinic_tx_queue_setup,
 	.dev_start                     = hinic_dev_start,

@@ -2849,6 +2871,7 @@ static void hinic_dev_close(struct rte_eth_dev *dev)
 static const struct eth_dev_ops hinic_pmd_vf_ops = {
 	.dev_configure                 = hinic_dev_configure,
 	.dev_infos_get                 = hinic_dev_infos_get,
+	.fw_version_get                = hinic_fw_version_get,
 	.rx_queue_setup                = hinic_rx_queue_setup,
 	.tx_queue_setup                = hinic_tx_queue_setup,
 	.dev_start                     = hinic_dev_start,

index 48ec467..b2cc0e4 100644
@@ -255,7 +255,7 @@ static int hinic_xstats_calc_num(struct hinic_nic_dev *nic_dev)
  * specific event.
  *
  * @param: The address of parameter (struct rte_eth_dev *) regsitered before.
- **/
+ */
 static void hinic_dev_interrupt_handler(void *param)
 {
 	struct rte_eth_dev *dev = param;

@@ -1088,7 +1088,7 @@ static void hinic_rx_queue_release(void *queue)
 	nic_dev = rxq->nic_dev;
 
 	/* free rxq_pkt mbuf */
-	hinic_free_all_rx_skbs(rxq);
+	hinic_free_all_rx_mbufs(rxq);
 
 	/* free rxq_cqe, rxq_info */
 	hinic_free_rx_resources(rxq);

@@ -1120,7 +1120,7 @@ static void hinic_tx_queue_release(void *queue)
 	nic_dev = txq->nic_dev;
 
 	/* free txq_pkt mbuf */
-	hinic_free_all_tx_skbs(txq);
+	hinic_free_all_tx_mbufs(txq);
 
 	/* free txq_info */
 	hinic_free_tx_resources(txq);

index dd96667..3e3f3b3 100644
@@ -178,6 +178,7 @@ struct hinic_nic_dev {
 	 * vf: the same with associate pf
 	 */
 	u32 default_cos;
+	u32 rx_csum_en;
 
 	struct hinic_filter_info    filter;
 	struct hinic_ntuple_filter_list filter_ntuple_list;

index 08e02ae..a9f3962 100644
@@ -309,7 +309,6 @@ static int hinic_rx_alloc_cqe(struct hinic_rxq *rxq)
 {
 	size_t cqe_mem_size;
 
-	/* allocate continuous cqe memory for saving number of memory zone */
 	cqe_mem_size = sizeof(struct hinic_rq_cqe) * rxq->q_depth;
 	rxq->cqe_start_vaddr =
 		dma_zalloc_coherent(rxq->nic_dev->hwdev,

@@ -421,7 +420,7 @@ void hinic_free_all_rx_resources(struct rte_eth_dev *eth_dev)
 		if (nic_dev->rxqs[q_id] == NULL)
 			continue;
 
-		hinic_free_all_rx_skbs(nic_dev->rxqs[q_id]);
+		hinic_free_all_rx_mbufs(nic_dev->rxqs[q_id]);
 		hinic_free_rx_resources(nic_dev->rxqs[q_id]);
 		kfree(nic_dev->rxqs[q_id]);
 		nic_dev->rxqs[q_id] = NULL;

@@ -435,11 +434,11 @@ void hinic_free_all_rx_mbuf(struct rte_eth_dev *eth_dev)
 	u16 q_id;
 
 	for (q_id = 0; q_id < nic_dev->num_rq; q_id++)
-		hinic_free_all_rx_skbs(nic_dev->rxqs[q_id]);
+		hinic_free_all_rx_mbufs(nic_dev->rxqs[q_id]);
 }
 
 static void hinic_recv_jumbo_pkt(struct hinic_rxq *rxq,
-				 struct rte_mbuf *head_skb,
+				 struct rte_mbuf *head_mbuf,
 				 u32 remain_pkt_len)
 {
 	struct hinic_nic_dev *nic_dev = rxq->nic_dev;

@@ -462,11 +461,11 @@ static void hinic_recv_jumbo_pkt(struct hinic_rxq *rxq,
 		cur_mbuf->data_len = (u16)pkt_len;
 		cur_mbuf->next = NULL;
 
-		head_skb->pkt_len += cur_mbuf->data_len;
-		head_skb->nb_segs++;
+		head_mbuf->pkt_len += cur_mbuf->data_len;
+		head_mbuf->nb_segs++;
 
 		if (!rxm)
-			head_skb->next = cur_mbuf;
+			head_mbuf->next = cur_mbuf;
 		else
 			rxm->next = cur_mbuf;
 

@@ -658,7 +657,6 @@ int hinic_rx_configure(struct rte_eth_dev *dev)
 	struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
 	struct rte_eth_rss_conf rss_conf =
 		dev->data->dev_conf.rx_adv_conf.rss_conf;
-	u32 csum_en = 0;
 	int err;
 
 	if (nic_dev->flags & ETH_MQ_RX_RSS_FLAG) {

@@ -678,9 +676,10 @@ int hinic_rx_configure(struct rte_eth_dev *dev)
 
 	/* Enable both L3/L4 rx checksum offload */
 	if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CHECKSUM)
-		csum_en = HINIC_RX_CSUM_OFFLOAD_EN;
+		nic_dev->rx_csum_en = HINIC_RX_CSUM_OFFLOAD_EN;
 
-	err = hinic_set_rx_csum_offload(nic_dev->hwdev, csum_en);
+	err = hinic_set_rx_csum_offload(nic_dev->hwdev,
+					HINIC_RX_CSUM_OFFLOAD_EN);
 	if (err)
 		goto rx_csum_ofl_err;
 

@@ -703,7 +702,7 @@ void hinic_rx_remove_configure(struct rte_eth_dev *dev)
 	}
 }
 
-void hinic_free_all_rx_skbs(struct hinic_rxq *rxq)
+void hinic_free_all_rx_mbufs(struct hinic_rxq *rxq)
 {
 	struct hinic_nic_dev *nic_dev = rxq->nic_dev;
 	struct hinic_rx_info *rx_info;

@@ -781,6 +780,10 @@ static inline uint64_t hinic_rx_csum(uint32_t status, struct hinic_rxq *rxq)
 {
 	uint32_t checksum_err;
 	uint64_t flags;
+	struct hinic_nic_dev *nic_dev = rxq->nic_dev;
+
+	if (unlikely(!(nic_dev->rx_csum_en & HINIC_RX_CSUM_OFFLOAD_EN)))
+		return PKT_RX_IP_CKSUM_UNKNOWN;
 
 	/* most case checksum is ok */
 	checksum_err = HINIC_GET_RX_CSUM_ERR(status);

@@ -999,8 +1002,8 @@ u16 hinic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, u16 nb_pkts)
 			rxm->data_len = rx_buf_len;
 			rxm->pkt_len = rx_buf_len;
 
-			/* if jumbo use multi-wqebb update ci,
-			 * recv_jumbo_pkt will also update ci
+			/* if receive jumbo, updating ci will be done by
+			 * hinic_recv_jumbo_pkt function.
 			 */
 			HINIC_UPDATE_RQ_LOCAL_CI(rxq, wqebb_cnt + 1);
 			wqebb_cnt = 0;

index fe2735b..5cd17ec 100644
@@ -105,7 +105,7 @@ struct hinic_rxq {
 
 u16 hinic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, u16 nb_pkts);
 
-void hinic_free_all_rx_skbs(struct hinic_rxq *rxq);
+void hinic_free_all_rx_mbufs(struct hinic_rxq *rxq);
 
 void hinic_rx_alloc_pkts(struct hinic_rxq *rxq);
 

302 lines not on this page · raw message

index 8a3df27..a1ca580 100644
@@ -131,7 +131,7 @@ struct hinic_txq {
 
 u16 hinic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, u16 nb_pkts);
 
-void hinic_free_all_tx_skbs(struct hinic_txq *txq);
+void hinic_free_all_tx_mbufs(struct hinic_txq *txq);
 
 void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats);
 

index b2cc0e4..54b9b49 100644
@@ -70,6 +70,9 @@
 #define HINIC_PKTLEN_TO_MTU(pktlen)	\
 	((pktlen) - (ETH_HLEN + ETH_CRC_LEN))
 
+/* lro numer limit for one packet */
+#define HINIC_LRO_WQE_NUM_DEFAULT	8
+
 /* Driver-specific log messages type */
 int hinic_logtype;
 

@@ -731,7 +734,8 @@ static void hinic_get_speed_capa(struct rte_eth_dev *dev, uint32_t *speed_capa)
 				DEV_RX_OFFLOAD_TCP_CKSUM |
 				DEV_RX_OFFLOAD_VLAN_FILTER |
 				DEV_RX_OFFLOAD_SCATTER |
-				DEV_RX_OFFLOAD_JUMBO_FRAME;
+				DEV_RX_OFFLOAD_JUMBO_FRAME |
+				DEV_RX_OFFLOAD_TCP_LRO;
 
 	info->tx_queue_offload_capa = 0;
 	info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |

@@ -792,6 +796,7 @@ static int hinic_rxtx_configure(struct rte_eth_dev *dev)
 {
 	int err;
 	struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
+	bool lro_en;
 
 	/* rx configure, if rss enable, need to init default configuration */
 	err = hinic_rx_configure(dev);

@@ -808,6 +813,18 @@ static int hinic_rxtx_configure(struct rte_eth_dev *dev)
 		goto set_rx_mode_fail;
 	}
 
+	/* config lro */
+	lro_en = dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ?
+			true : false;
+
+	err = hinic_set_rx_lro(nic_dev->hwdev, lro_en, lro_en,
+				HINIC_LRO_WQE_NUM_DEFAULT);
+	if (err) {
+		PMD_DRV_LOG(ERR, "%s lro failed, err: %d",
+			lro_en ? "Enable" : "Disable", err);
+		goto set_rx_mode_fail;
+	}
+
 	return HINIC_OK;
 
 set_rx_mode_fail:

@@ -2478,11 +2495,6 @@ static int hinic_set_default_hw_feature(struct hinic_nic_dev *nic_dev)
 	if (err)
 		return err;
 
-	/* disable LRO */
-	err = hinic_set_rx_lro(nic_dev->hwdev, 0, 0, (u8)0);
-	if (err)
-		return err;
-
 	/* Set pause enable, and up will disable pfc. */
 	err = hinic_set_default_pause_feature(nic_dev);
 	if (err)

index b63e52b..2626f69 100644
@@ -48,16 +48,12 @@
 
 /* EQ registers */
 #define HINIC_AEQ_MTT_OFF_BASE_ADDR			0x200
-#define HINIC_CEQ_MTT_OFF_BASE_ADDR			0x400
 
 #define HINIC_EQ_MTT_OFF_STRIDE				0x40
 
 #define HINIC_CSR_AEQ_MTT_OFF(id)			\
 	(HINIC_AEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
 
-#define HINIC_CSR_CEQ_MTT_OFF(id)			\
-	(HINIC_CEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
-
 #define HINIC_CSR_EQ_PAGE_OFF_STRIDE			8
 
 #define HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num)	\

@@ -68,23 +64,11 @@
 		(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
 		(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
 
-#define HINIC_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)	\
-		(HINIC_CSR_CEQ_MTT_OFF(q_id) + \
-		(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
-
-#define HINIC_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num)	\
-		(HINIC_CSR_CEQ_MTT_OFF(q_id) + \
-		(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
-
 #define HINIC_EQ_HI_PHYS_ADDR_REG(type, q_id, pg_num)	\
-		((u32)((type == HINIC_AEQ) ? \
-		HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num) : \
-		HINIC_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)))
+		((u32)(HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num)))
 
 #define HINIC_EQ_LO_PHYS_ADDR_REG(type, q_id, pg_num)	\
-		((u32)((type == HINIC_AEQ) ? \
-		HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num) : \
-		HINIC_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num)))
+		((u32)(HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num)))
 
 #define HINIC_AEQ_CTRL_0_ADDR_BASE			0xE00
 #define HINIC_AEQ_CTRL_1_ADDR_BASE			0xE04

@@ -105,15 +89,6 @@
 #define HINIC_CSR_AEQ_PROD_IDX_ADDR(idx) \
 	(HINIC_AEQ_CONS_IDX_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
 
-#define HINIC_CEQ_CONS_IDX_0_ADDR_BASE			0x1008
-#define HINIC_CEQ_CONS_IDX_1_ADDR_BASE			0x100C
-
-#define HINIC_CSR_CEQ_CONS_IDX_ADDR(idx) \
-	(HINIC_CEQ_CONS_IDX_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
-
-#define HINIC_CSR_CEQ_PROD_IDX_ADDR(idx) \
-	(HINIC_CEQ_CONS_IDX_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
-
 /* API CMD registers */
 #define HINIC_CSR_API_CMD_BASE				0xF000
 

index e0633bd..c025851 100644
@@ -5,10 +5,7 @@
 #ifndef _HINIC_PORT_CMD_H_
 #define _HINIC_PORT_CMD_H_
 
-enum hinic_eq_type {
-	HINIC_AEQ,
-	HINIC_CEQ
-};
+#define HINIC_AEQ	0
 
 enum hinic_resp_aeq_num {
 	HINIC_AEQ0 = 0,

401 lines not on this page · raw message

index fdb9854..16046ec 100644
@@ -21,9 +21,6 @@
 
 #define HINIC_DEFAULT_AEQ_LEN		64
 
-#define HINIC_RECV_NEXT_AEQE		HINIC_ERROR
-#define HINIC_RECV_DONE			HINIC_OK
-
 #define GET_EQ_ELEMENT(eq, idx)		\
 		(((u8 *)(eq)->virt_addr[(idx) / (eq)->num_elem_in_pg]) + \
 		(((u32)(idx) & ((eq)->num_elem_in_pg - 1)) * (eq)->elem_size))

@@ -58,7 +55,7 @@ enum hinic_aeq_type {
 struct hinic_eq {
 	struct hinic_hwdev		*hwdev;
 	u16				q_id;
-	enum hinic_eq_type		type;
+	u16				type;
 	u32				page_size;
 	u16				eq_len;
 

index a9f3962..743bae9 100644
@@ -971,13 +971,10 @@ u16 hinic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, u16 nb_pkts)
 	while (pkts < nb_pkts) {
 		 /* 2. current ci is done */
 		rx_cqe = &rxq->rx_cqe[sw_ci];
-		status = rx_cqe->status;
+		status = __atomic_load_n(&rx_cqe->status, __ATOMIC_ACQUIRE);
 		if (!HINIC_GET_RX_DONE_BE(status))
 			break;
 
-		/* read other cqe member after status */
-		rte_rmb();
-
 		/* convert cqe and get packet length */
 		hinic_rq_cqe_be_to_cpu32(&cqe, (volatile void *)rx_cqe);
 		vlan_len = cqe.vlan_len;

index 5cd17ec..1a80f95 100644
@@ -35,7 +35,7 @@ struct hinic_rq_cqe {
 	u32 rss_hash;
 
 	u32 rsvd[4];
-};
+} __rte_cache_aligned;
 
 struct hinic_rq_cqe_sect {
 	struct hinic_sge	sge;

index 54b9b49..9f37a40 100644
@@ -53,6 +53,11 @@
 #define HINIC_MIN_RX_BUF_SIZE		1024
 #define HINIC_MAX_UC_MAC_ADDRS		128
 #define HINIC_MAX_MC_MAC_ADDRS		2048
+
+#define HINIC_DEFAULT_BURST_SIZE	32
+#define HINIC_DEFAULT_NB_QUEUES		1
+#define HINIC_DEFAULT_RING_SIZE		1024
+
 /*
  * vlan_id is a 12 bit number.
  * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.

@@ -753,6 +758,14 @@ static void hinic_get_speed_capa(struct rte_eth_dev *dev, uint32_t *speed_capa)
 	info->rx_desc_lim = hinic_rx_desc_lim;
 	info->tx_desc_lim = hinic_tx_desc_lim;
 
+	/* Driver-preferred Rx/Tx parameters */
+	info->default_rxportconf.burst_size = HINIC_DEFAULT_BURST_SIZE;
+	info->default_txportconf.burst_size = HINIC_DEFAULT_BURST_SIZE;
+	info->default_rxportconf.nb_queues = HINIC_DEFAULT_NB_QUEUES;
+	info->default_txportconf.nb_queues = HINIC_DEFAULT_NB_QUEUES;
+	info->default_rxportconf.ring_size = HINIC_DEFAULT_RING_SIZE;
+	info->default_txportconf.ring_size = HINIC_DEFAULT_RING_SIZE;
+
 	return 0;
 }
 

@@ -2157,6 +2170,23 @@ static int hinic_dev_xstats_get(struct rte_eth_dev *dev,
 	return count;
 }
 
+static void hinic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
+				struct rte_eth_rxq_info *qinfo)
+{
+	struct hinic_rxq  *rxq = dev->data->rx_queues[queue_id];
+
+	qinfo->mp = rxq->mb_pool;
+	qinfo->nb_desc = rxq->q_depth;
+}
+
+static void hinic_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
+				struct rte_eth_txq_info *qinfo)
+{
+	struct hinic_txq  *txq = dev->data->tx_queues[queue_id];
+
+	qinfo->nb_desc = txq->q_depth;
+}
+
 /**
  * DPDK callback to retrieve names of extended device statistics
  *

@@ -2873,6 +2903,8 @@ static void hinic_dev_close(struct rte_eth_dev *dev)
 	.xstats_get                    = hinic_dev_xstats_get,
 	.xstats_reset                  = hinic_dev_xstats_reset,
 	.xstats_get_names              = hinic_dev_xstats_get_names,
+	.rxq_info_get                  = hinic_rxq_info_get,
+	.txq_info_get                  = hinic_txq_info_get,
 	.mac_addr_set                  = hinic_set_mac_addr,
 	.mac_addr_remove               = hinic_mac_addr_remove,
 	.mac_addr_add                  = hinic_mac_addr_add,

@@ -2906,6 +2938,8 @@ static void hinic_dev_close(struct rte_eth_dev *dev)
 	.xstats_get                    = hinic_dev_xstats_get,
 	.xstats_reset                  = hinic_dev_xstats_reset,
 	.xstats_get_names              = hinic_dev_xstats_get_names,
+	.rxq_info_get                  = hinic_rxq_info_get,
+	.txq_info_get                  = hinic_txq_info_get,
 	.mac_addr_set                  = hinic_set_mac_addr,
 	.mac_addr_remove               = hinic_mac_addr_remove,
 	.mac_addr_add                  = hinic_mac_addr_add,