arm64: dts: qcom: sc7280: Add nodes for eMMC and SD card
Subsystems (5)
PATCH v2 1/1 arm64: dts: qcom: sc7280: Add nodes for eMMC and SD card
Add nodes for eMMC and SD card on sc7280.
---
This change is depends on the below patch series:
https://lore.kernel.org/patchwork/project/lkml/list/?series=488871
https://lore.kernel.org/patchwork/project/lkml/list/?series=489530
https://lore.kernel.org/patchwork/project/lkml/list/?series=488429
Changes since V1:
- Moved SDHC nodes as suggested by Bjorn Andersson.
- Dropped "pinconf-" prefix as suggested by Bjorn Andersson.
- Removed extra newlines as suggested by Konrad Dybcio.
- Changed sd-cd pin to bias-pull-up in sdc2_off as suggested by Veerabhadrarao Badiganti.
- Added bandwidth votes for eMMC and SD card.
--- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 25 ++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 213 ++++++++++++++++++++++++++++++++ 2 files changed, 238 insertions(+)
arch/arm64/boot/dts/qcom/sc7280-idp.dts +25 -0
@@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Qualcomm Technologies, Inc. sc7280 IDP platform";
@@ -242,6 +243,30 @@ status = "okay"; }; +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default","sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + /* PINCTRL - additions to nodes defined in sc7280.dtsi */ &qup_uart5_default {
arch/arm64/boot/dts/qcom/sc7280.dtsi +213 -0
237 lines not on this page · raw message
Signature · 1 line
2.7.4
kernel test robot
build botThank you for the patch! Yet something to improve:
Hi Shaik,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on next-20210319]
[cannot apply to robh/for-next v5.12-rc3 v5.12-rc2 v5.12-rc1 v5.12-rc3] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Shaik-Sajida-Bhanu/arm64-dts-qcom-sc7280-Add-nodes-for-eMMC-and-SD-card/20210321-022010 base: f00397ee41c79b6155b9b44abd0055b2c0621349 config: arm64-randconfig-r015-20210321 (attached as .config) compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 436c6c9c20cc522c92a923440a5fc509c342a7db)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/0day-ci/linux/commit/4476a83ec3090af1252f388b48edd2340e66329e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Shaik-Sajida-Bhanu/arm64-dts-qcom-sc7280-Add-nodes-for-eMMC-and-SD-card/20210321-022010 git checkout 4476a83ec3090af1252f388b48edd2340e66329e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/qcom/sc7280.dtsi:305.33-34 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
Quoting Shaik Sajida Bhanu (2021-03-20 11:17:00)
arch/arm64/boot/dts/qcom/sc7280-idp.dts line 11
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +1
-0@@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280.dtsi" +#include <dt-bindings/gpio/gpio.h>
Please include this before sc7280.dtsi
Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +5
-0/ { model = "Qualcomm Technologies, Inc. sc7280 IDP platform";@@ -242,6 +243,30 @@ status = "okay"; }; +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>;
arch/arm64/boot/dts/qcom/sc7280-idp.dts line 260
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +10
-0+ pinctrl-1 = <&sdc1_off>; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default","sleep";
Please add a space after the comma ^
Quoted 29 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +9
-0+ pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + /* PINCTRL - additions to nodes defined in sc7280.dtsi */ &qup_uart5_default {arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0@@ -20,6 +20,11 @@ chosen { }; + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock";
arch/arm64/boot/dts/qcom/sc7280.dtsi line 315
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0@@ -305,6 +310,64 @@ #power-domain-cells = <1>; }; + sdhc_1: sdhci@7c4000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0 0x7c4000 0 0x1000>,
Please add leading zeroes to the physical address, i.e. 0x007c4000
arch/arm64/boot/dts/qcom/sc7280.dtsi line 319
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ <0 0x7c5000 0 0x1000>; + reg-names = "hc", "cqhci"; + + iommus = <&apps_smmu 0xC0 0x0>;
Lowercase hex please.
Quoted 11 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +11
-0+ interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc";
arch/arm64/boot/dts/qcom/sc7280.dtsi line 340
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + bus-width = <8>; + non-removable; + supports-cqe; + no-sd; + no-sdio; + + max-frequency = <192000000>;
Is this necessary?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 350
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + status = "disabled";
Can this be near the compatible string?
Quoted 24 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +20
-0+ + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1200000 76000>; + opp-avg-kBps = <1200000 50000>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <6000000 300000>; + }; + }; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>;
arch/arm64/boot/dts/qcom/sc7280.dtsi line 396
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0@@ -328,6 +391,54 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>;
This has leading zeroes, great!
arch/arm64/boot/dts/qcom/sc7280.dtsi line 405
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +9
-0+ + iommus = <&apps_smmu 0x100 0x0>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>;
Is this aligned properly?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 418
Quoted 13 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +13
-0+ clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + bus-width = <4>; + + no-mmc; + no-sdio; + + max-frequency = <202000000>;
Is this necessary?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 350
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ + qcom,dll-config = <0x0007642c>; + + status = "disabled";
Move up near compatible?
Quoted 22 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +19
-0+ + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz =/bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1200000 76000>; + opp-avg-kBps = <1200000 50000>; + }; + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3500000 1200000>; + opp-avg-kBps = <5000000 100000>; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;
Quoted 8 lines · Stephen Boyd
Quoting Shaik Sajida Bhanu (2021-03-20 11:17:00)
Quoted 7 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +0
-0@@ -8,6 +8,7 @@ /dts-v1/;
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts line 11
Quoted 2 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +1
-0#include "sc7280.dtsi" +#include <dt-bindings/gpio/gpio.h>Please include this before
sc7280.dtsi
Sure
Quoted 16 lines
Quoted 16 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +9
-0/ { model = "Qualcomm Technologies, Inc. sc7280 IDP platform";@@ -242,6 +243,30 @@ status = "okay"; }; +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>;
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts line 260
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +6
-0+}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default","sleep";Please add a space after the comma ^
Sure
Quoted 33 lines
Quoted 33 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +9
-0+ pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + /* PINCTRL - additions to nodes defined in sc7280.dtsi */ &qup_uart5_default {arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0@@ -20,6 +20,11 @@ chosen { }; + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock";@@ -305,6 +310,64 @@ #power-domain-cells = <1>; };
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 315
Quoted 3 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ sdhc_1: sdhci@7c4000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0 0x7c4000 0 0x1000>,Please add leading zeroes to the physical address, i.e.
0x007c4000
Sure
Quoted 7 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 319
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ <0 0x7c5000 0 0x1000>; + reg-names = "hc", "cqhci"; + + iommus = <&apps_smmu 0xC0 0x0>;Lowercase hex please.
Sure
Quoted 20 lines
Quoted 20 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0&cnoc2
SLAVE_SDCC_10>;arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + bus-width = <8>;
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 340
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +6
-0+ non-removable; + supports-cqe; + no-sd; + no-sdio; + + max-frequency = <192000000>;Is this necessary?
yes, to avoid lower speed modes running with high clock rates.
Quoted 13 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 350
Quoted 11 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + status = "disabled";Can this be near the compatible string?
Sure
Quoted 42 lines
Quoted 33 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +6
-0+ + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64<100000000>;
+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1200000
76000>;
+ opp-avg-kBps = <1200000
50000>;arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ }; + + opp-384000000 { + opp-hz = /bits/ 64<384000000>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000
1600000>;
+ opp-avg-kBps = <6000000
300000>;arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ }; + }; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>;arch/arm64/boot/dts/qcom/sc7280.dtsi line 396
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0@@ -328,6 +391,54 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>;This has leading zeroes, great!
Quoted 13 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 405
Quoted 11 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +9
-0+ + iommus = <&apps_smmu 0x100 0x0>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>;Is this aligned properly?
yes
Quoted 10 lines
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0&cnoc2
SLAVE_SDCC_20>;arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc2_opp_table>; +
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 418
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +6
-0+ bus-width = <4>; + + no-mmc; + no-sdio; + + max-frequency = <202000000>;Is this necessary?
yes, to avoid clock running more than required clock rate.
Quoted 7 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 350
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ + qcom,dll-config = <0x0007642c>; + + status = "disabled";Move up near compatible?
sure
Quoted 32 lines
Quoted 32 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ + sdhc2_opp_table: sdhc2-opp-table { + compatible ="operating-points-v2";
arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ + opp-100000000 { + opp-hz =/bits/ 64<100000000>;
+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps =
<1200000 76000>;
+ opp-avg-kBps =
<1200000 50000>;arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ }; + opp-202000000 { + opp-hz = /bits/ 64<202000000>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ opp-peak-kBps =
<3500000 1200000>;
+ opp-avg-kBps =
<5000000 100000>;arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;
Quoting [email protected] (2021-03-24 08:23:55)
Quoted 12 lines · Stephen Boyd
Quoted 11 lines
Quoting Shaik Sajida Bhanu (2021-03-20 11:17:00)
arch/arm64/boot/dts/qcom/sc7280.dtsi line 340
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +8
-0+ + bus-width = <8>; + non-removable; + supports-cqe; + no-sd; + no-sdio; + + max-frequency = <192000000>;Is this necessary?
Quoted 1 line
yes, to avoid lower speed modes running with high clock rates.
Is it part of the DT binding? I don't see any mention of it.
Quoting Stephen Boyd (2021-03-24 08:57:33)
Quoted 13 lines
Quoting [email protected] (2021-03-24 08:23:55)
Quoted 12 lines · Stephen Boyd
Quoted 11 lines
Quoting Shaik Sajida Bhanu (2021-03-20 11:17:00)
arch/arm64/boot/dts/qcom/sc7280.dtsi line 340
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +8
-0+ + bus-width = <8>; + non-removable; + supports-cqe; + no-sd; + no-sdio; + + max-frequency = <192000000>;Is this necessary?
Quoted 3 lines
Quoted 1 line
yes, to avoid lower speed modes running with high clock rates.
Is it part of the DT binding? I don't see any mention of it.
Nevermind, found it in mmc-controller.yaml. But I think this is to work around some problem with the clk driver picking lower speeds than requested? That has been fixed on the clk driver side (see commit like 148ddaa89d4a "clk: qcom: gcc-sc7180: Use floor ops for the correct sdcc1 clk") so ideally this property can be omitted.
Quoted 13 lines · Stephen Boyd
Quoting Stephen Boyd (2021-03-24 08:57:33)
Quoted 12 lines
Quoting [email protected] (2021-03-24 08:23:55)
Quoted 11 lines · Stephen Boyd
Quoted 10 lines
Quoting Shaik Sajida Bhanu (2021-03-20 11:17:00)
arch/arm64/boot/dts/qcom/sc7280.dtsi line 340
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +8
-0+ + bus-width = <8>; + non-removable; + supports-cqe; + no-sd; + no-sdio; + + max-frequency = <192000000>;Is this necessary?
Quoted 7 lines
Quoted 2 lines
Quoted 1 line
yes, to avoid lower speed modes running with high clock rates.
Is it part of the DT binding? I don't see any mention of it.
Nevermind, found it in
mmc-controller.yaml. But I think this is to work around some problem with the clk driver picking lower speeds than requested? That has been fixed on the clk driver side (see commit like148ddaa89d4a"clk: qcom: gcc-sc7180: Use floor ops for the correct sdcc1 clk") so ideally this property can be omitted.
This is a good have dt node.
This will align clock requests between mmc core layer and sdhci-msm platform driver. Say, for HS200/HS400 modes of eMMC, mmc-core layer tries to set clock at 200Mhz, whereas sdhci-msm expects 192Mhz for these modes. So we have to rely on clock driver floor/ceil values. By having this property, mmc-core layer itself request for 192Mhz.
Same is for SD card SDR104 mode, core layer expects clock at 208Mhz whereas sdhci-msm can max operate only at 202Mhz. By having this property, core layer requests only for 202Mhz for SDR104 mode.
BTW, this helps only for max possible speed modes.
In case of lower-speed modes (for DDR52) we still need to rely on clock floor rounding.
Hi,
Quoted 31 lines · Veerabhadrarao Badiganti
Quoted 13 lines · Stephen Boyd
Quoting Stephen Boyd (2021-03-24 08:57:33)
Quoted 12 lines
Quoting [email protected] (2021-03-24 08:23:55)
Quoted 11 lines · Stephen Boyd
Quoted 10 lines
Quoting Shaik Sajida Bhanu (2021-03-20 11:17:00)
arch/arm64/boot/dts/qcom/sc7280.dtsi line 340
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arch/arm64/boot/dts/qcom/sc7280.dtsi +8
-0+ + bus-width = <8>; + non-removable; + supports-cqe; + no-sd; + no-sdio; + + max-frequency = <192000000>;Is this necessary?
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yes, to avoid lower speed modes running with high clock rates.
Is it part of the DT binding? I don't see any mention of it.
Nevermind, found it in
mmc-controller.yaml. But I think this is to work around some problem with the clk driver picking lower speeds than requested? That has been fixed on the clk driver side (see commit like148ddaa89d4a"clk: qcom: gcc-sc7180: Use floor ops for the correct sdcc1 clk") so ideally this property can be omitted.This is a good have dt node.
This will align clock requests between mmc core layer and sdhci-msm platform driver. Say, for HS200/HS400 modes of eMMC, mmc-core layer tries to set clock at 200Mhz, whereas sdhci-msm expects 192Mhz for these modes. So we have to rely on clock driver floor/ceil values. By having this property, mmc-core layer itself request for 192Mhz.
Quoted 7 lines
Same is for SD card SDR104 mode, core layer expects clock at 208Mhz whereas sdhci-msm can max operate only at 202Mhz. By having this property, core layer requests only for 202Mhz for SDR104 mode.
BTW, this helps only for max possible speed modes.
In case of lower-speed modes (for DDR52) we still need to rely on clock floor rounding.
Just let the clock driver figure it out and remove this from the devicetree, please. As you said, the clock driver needs to understand how to round rates anyway for the non-maximum requests. Putting the information here just duplicates the data.
-Doug
Hi,
Quoted 36 lines · Shaik Sajida Bhanu
Add nodes for eMMC and SD card on sc7280.
Signed-off-by Shaik Sajida Bhanu <[email protected]>---
This change is depends on the below patch series:
https://lore.kernel.org/patchwork/project/lkml/list/?series=488871
https://lore.kernel.org/patchwork/project/lkml/list/?series=489530
https://lore.kernel.org/patchwork/project/lkml/list/?series=488429Changes since V1:
- Moved SDHC nodes as suggested by Bjorn Andersson.
- Dropped "pinconf-" prefix as suggested by Bjorn Andersson.
- Removed extra newlines as suggested by Konrad Dybcio.
- Changed sd-cd pin to bias-pull-up insdc2_offas suggested by Veerabhadrarao Badiganti.
- Added bandwidth votes for eMMC and SD card.--- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 25 ++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 213 ++++++++++++++++++++++++++++++++ 2 files changed, 238 insertions(+)arch/arm64/boot/dts/qcom/sc7280-idp.dts +1
-0@@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Qualcomm Technologies, Inc. sc7280 IDP platform";
arch/arm64/boot/dts/qcom/sc7280-idp.dts line 247
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arch/arm64/boot/dts/qcom/sc7280-idp.dts +2
-0@@ -242,6 +243,30 @@ status = "okay"; }; +&sdhc_1 { + status = "okay";
When I apply your patch I find that your sort order is wrong. "s" comes before "u" and after "q" in the alphabet so "sdhc_1" and "sdhc_2" should sort _after "qupv3_id_0" and before "uart5"
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +9
-0+ pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; +}; + +&sdhc_2 {
arch/arm64/boot/dts/qcom/sc7280-idp.dts line 267
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +10
-0+ status = "okay"; + + pinctrl-names = "default","sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
Where is the pinctrl for the card detect? Oh, I see it's in "sdc2_on". Probably would be good to break it out since this is board-specific. See below.
Quoted 22 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +2
-0+}; + /* PINCTRL - additions to nodes defined in sc7280.dtsi */ &qup_uart5_default {arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0@@ -20,6 +20,11 @@ chosen { }; + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock";
arch/arm64/boot/dts/qcom/sc7280.dtsi line 314
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arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0@@ -305,6 +310,64 @@ #power-domain-cells = <1>; }; + sdhc_1: sdhci@7c4000 { + compatible = "qcom,sdhci-msm-v5";
Please make the compatible:
compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
...and add to the bindings. It should be a trivial bindings patch so not too much trouble.
NOTE: even though the "qcom,sc7280-sdhci" should be in the bindings and here you _shouldn't_ be adding any code for it. Just let the fallback compatible string ("qcom,sdhci-msm-v5") do its magic. Adding the sc7280 specific version is more of a "just in case we need it later" type thing.
arch/arm64/boot/dts/qcom/sc7280.dtsi line 327
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arch/arm64/boot/dts/qcom/sc7280.dtsi +13
-0+ reg = <0 0x7c4000 0 0x1000>, + <0 0x7c5000 0 0x1000>; + reg-names = "hc", "cqhci"; + + iommus = <&apps_smmu 0xC0 0x0>; + interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo";
I'm curious: why is the "xo" clock needed here but not for sc7180?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 335
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +8
-0+ interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + bus-width = <8>; + non-removable;
This was actually a problem on sc7180 too, but you probably don't want "non-removable" in the SoC file. Board files really should be adding this. Though the SoC might be designed with the idea that this would be used for a non-removable eMMC card I don't know why it wouldn't be possible for someone to hook this up to an external slot and use a GPIO somewhere as a card detect.
arch/arm64/boot/dts/qcom/sc7280.dtsi line 338
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arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ supports-cqe; + no-sd; + no-sdio;
Does the port really not support SD / SDIO, or are you adding these two properties just because on your reference board it's not hooked up to SD/SDIO? What exactly makes it impossible to use SD/SDIO on this port?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 340
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arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0+ max-frequency = <192000000>;
Why do you need to specify this?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 343
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arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0+ qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>;
These magic hex values really have no place being in dts which should have things expressed at a higher level. ...but I guess that ship has sailed and this is in the bindings so I guess we're stuck with them, so I guess they're fine.
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +
arch/arm64/boot/dts/qcom/sc7280.dtsi line 359
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ status = "disabled"; + + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1200000 76000>; + opp-avg-kBps = <1200000 50000>;
Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 366
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arch/arm64/boot/dts/qcom/sc7280.dtsi +7
-0+ }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <6000000 300000>;
These opp numbers are also quite different than sc7180
Quoted 24 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +17
-0+ }; + }; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>;@@ -328,6 +391,54 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + iommus = <&apps_smmu 0x100 0x0>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo";
arch/arm64/boot/dts/qcom/sc7280.dtsi line 416
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + bus-width = <4>; + + no-mmc; + no-sdio;
Similar question to above: why exactly would mmc not work? Are you saying that if someone hooked this up to a full sized SD card slot and placed an MMC card into the slot that it wouldn't work? Similar question about SDIO. If someone placed an external SDIO card into your slot, would it not work?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 418
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arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0+ max-frequency = <202000000>;
Not needed?
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arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ + qcom,dll-config = <0x0007642c>; + + status = "disabled"; +
arch/arm64/boot/dts/qcom/sc7280.dtsi line 433
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz =/bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1200000 76000>; + opp-avg-kBps = <1200000 50000>; + }; + opp-202000000 {
Blank line between the OPPs?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 438
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3500000 1200000>; + opp-avg-kBps = <5000000 100000>; + };
Similar questions about why the OPPs are so vastly different from sc7180.
Quoted 24 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +17
-0+ }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;@@ -374,6 +485,108 @@ pins = "gpio46", "gpio47"; function = "qup13"; }; + + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; +
arch/arm64/boot/dts/qcom/sc7280.dtsi line 511
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + };
* generally "bias" doesn't belong in the SoC file but instead should be in the board file. Some boards might have external pulls (even if the internal ones would work fine, hardware designers do weird things) and thus might need to disable the internal ones (double pulls are not great).
* generally drive-strength doesn't belong in the SoC file but should be in the board file. Different boards with different layouts might need different drive strengths, right?
If you remove those two things, I guess there's not actually much left in the SoC dtsi file so I guess move these all to the board file? That seems to be what we ended up with in "qrb5165-rb5.dts" / "sm8250.dtsi" which is an example of a board using the new style of pinctrl for devicetree.
Quoted 16 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +16
-0+ }; + + sdc1_off: sdc1-off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data {
arch/arm64/boot/dts/qcom/sc7280.dtsi line 537
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + };
No need for a sleep state for the rclk since it's the same as the active state, right? NOTE: one way to handle this would be to define one node per pingroup and thus do something like:
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk>;
I do wish we could avoid having to duplicate the "bias" in every board file. Hrm, I wonder if this could be made simpler by actually putting the "sleep" states in the sc7180.dtsi file (not the board file) and using "bias-bus-hold" to avoid it being board specific?
Thus (assuming it works), the total summary would be:
1. Board dts file fully defines "sdc1_clk", "sdc1_cmd", "sdc1_data", "sdc1_rclk", specifying whatever bias and drive strength needed for the board.
2. SoC dtsi fully defines "sdc1_clk_sleep", "sdc1_cmd_sleep", "sdc1_data_sleep", "sdc1_rclk_sleep", specifying drive-strength of 2 (for outputs) and "bias-bus-hold" which is OK for all board.
Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +12
-0+ + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>;
arch/arm64/boot/dts/qcom/sc7280.dtsi line 559
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio91";
NOTE: even if we find some reason to keep some of the pinctrl in the SoC dtsi file, the card detect almost certainly needs to move _fully_ to the board dts file. Different boards could use a different card detect pin.
arch/arm64/boot/dts/qcom/sc7280.dtsi line 561
Quoted 2 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0+ bias-pull-up; + drive-strength = <2>;
Drive strength isn't needed for input pins. Please remove.
Quoted 17 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +17
-0+ }; + }; + + sdc2_off: sdc2-off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data {
arch/arm64/boot/dts/qcom/sc7280.dtsi line 588
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio91"; + bias-pull-up; + drive-strength = <2>; + };
There's definitely no need for a separate sleep state for the CD line.
-Doug
Quoted 113 lines · Doug Anderson
Hi,
Quoted 35 lines · Shaik Sajida Bhanu
Add nodes for eMMC and SD card on sc7280.
Signed-off-by Shaik Sajida Bhanu <[email protected]>---
This change is depends on the below patch series:
https://lore.kernel.org/patchwork/project/lkml/list/?series=488871
https://lore.kernel.org/patchwork/project/lkml/list/?series=489530
https://lore.kernel.org/patchwork/project/lkml/list/?series=488429Changes since V1:
- Moved SDHC nodes as suggested by Bjorn Andersson.
- Dropped "pinconf-" prefix as suggested by Bjorn Andersson.
- Removed extra newlines as suggested by Konrad Dybcio.
- Changed sd-cd pin to bias-pull-up insdc2_offas suggested by Veerabhadrarao Badiganti.
- Added bandwidth votes for eMMC and SD card.--- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 25 ++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 213 ++++++++++++++++++++++++++++++++ 2 files changed, 238 insertions(+)arch/arm64/boot/dts/qcom/sc7280-idp.dts +1
-0@@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Qualcomm Technologies, Inc. sc7280 IDP platform";arch/arm64/boot/dts/qcom/sc7280-idp.dts line 247
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +2
-0@@ -242,6 +243,30 @@ status = "okay"; }; +&sdhc_1 { + status = "okay";When I apply your patch I find that your sort order is wrong. "s" comes before "u" and after "q" in the alphabet so "
sdhc_1" and "sdhc_2" should sort_after"qupv3_id_0" and before "uart5"Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +9
-0+ pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; +}; + +&sdhc_2 {arch/arm64/boot/dts/qcom/sc7280-idp.dts line 267
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +10
-0+ status = "okay"; + + pinctrl-names = "default","sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;Where is the pinctrl for the card detect? Oh, I see it's in "
sdc2_on". Probably would be good to break it out since this is board-specific. See below.Quoted 22 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +2
-0+}; + /* PINCTRL - additions to nodes defined in sc7280.dtsi */ &qup_uart5_default {arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0@@ -20,6 +20,11 @@ chosen { }; + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock";arch/arm64/boot/dts/qcom/sc7280.dtsi line 314
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0@@ -305,6 +310,64 @@ #power-domain-cells = <1>; }; + sdhc_1: sdhci@7c4000 { + compatible = "qcom,sdhci-msm-v5";Please make the compatible:
compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";...and add to the bindings. It should be a trivial bindings patch so not too much trouble.
NOTE: even though the "qcom,sc7280-sdhci" should be in the bindings and here you _shouldn't_ be adding any code for it. Just let the fallback compatible string ("qcom,sdhci-msm-v5") do its magic. Adding the sc7280 specific version is more of a "just in case we need it later" type thing.
Quoted 14 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 327
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arch/arm64/boot/dts/qcom/sc7280.dtsi +13
-0+ reg = <0 0x7c4000 0 0x1000>, + <0 0x7c5000 0 0x1000>; + reg-names = "hc", "cqhci"; + + iommus = <&apps_smmu 0xC0 0x0>; + interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo";I'm curious: why is the "xo" clock needed here but not for sc7180?
Actually its needed even for sc7180. We are making use of this clock in msm_init_cm_dll() The default PoR value is also same as calculated value for HS200/HS400/SDR104 modes. But just not to rely on default register values we need this entry.
Quoted 17 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 335
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arch/arm64/boot/dts/qcom/sc7280.dtsi +8
-0+ interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + bus-width = <8>; + non-removable;This was actually a problem on sc7180 too, but you probably don't want "non-removable" in the SoC file. Board files really should be adding this. Though the SoC might be designed with the idea that this would be used for a non-removable eMMC card I don't know why it wouldn't be possible for someone to hook this up to an external slot and use a GPIO somewhere as a card detect.
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 338
Quoted 3 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ supports-cqe; + no-sd; + no-sdio;Does the port really not support SD / SDIO, or are you adding these two properties just because on your reference board it's not hooked up to SD/SDIO? What exactly makes it impossible to use SD/SDIO on this port?
By having this, we can optimize emmc device scan time. Driver wont issue SDIO & SDcards specific commands while scanning the device.Its little optimization.
I think board specific dt is right place.
Quoted 81 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 340
Quoted 1 line
arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0+ max-frequency = <192000000>;Why do you need to specify this?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 343
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arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0+ qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>;These magic hex values really have no place being in dts which should have things expressed at a higher level. ...but I guess that ship has sailed and this is in the bindings so I guess we're stuck with them, so I guess they're fine.
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arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +arch/arm64/boot/dts/qcom/sc7280.dtsi line 359
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arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ status = "disabled"; + + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1200000 76000>; + opp-avg-kBps = <1200000 50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 366
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arch/arm64/boot/dts/qcom/sc7280.dtsi +7
-0+ }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <6000000 300000>;These opp numbers are also quite different than sc7180
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arch/arm64/boot/dts/qcom/sc7280.dtsi +24
-0+ }; + }; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>;@@ -328,6 +391,54 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + iommus = <&apps_smmu 0x100 0x0>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + bus-width = <4>;
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arch/arm64/boot/dts/qcom/sc7280.dtsi line 416
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arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ + no-mmc; + no-sdio;Similar question to above: why exactly would mmc not work? Are you saying that if someone hooked this up to a full sized SD card slot and placed an MMC card into the slot that it wouldn't work? Similar question about SDIO. If someone placed an external SDIO card into your slot, would it not work?
As mentioned above, its just to optimize SDcard scan time a little.
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arch/arm64/boot/dts/qcom/sc7280.dtsi line 418
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arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0+ max-frequency = <202000000>;Not needed?
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arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ + qcom,dll-config = <0x0007642c>; + + status = "disabled"; +arch/arm64/boot/dts/qcom/sc7280.dtsi line 433
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arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz =/bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1200000 76000>; + opp-avg-kBps = <1200000 50000>; + }; + opp-202000000 {Blank line between the OPPs?
arch/arm64/boot/dts/qcom/sc7280.dtsi line 438
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arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3500000 1200000>; + opp-avg-kBps = <5000000 100000>; + };Similar questions about why the OPPs are so vastly different from sc7180.
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arch/arm64/boot/dts/qcom/sc7280.dtsi +17
-0+ }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;@@ -374,6 +485,108 @@ pins = "gpio46", "gpio47"; function = "qup13"; }; + + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; +arch/arm64/boot/dts/qcom/sc7280.dtsi line 511
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arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + };* generally "bias" doesn't belong in the SoC file but instead should be in the board file. Some boards might have external pulls (even if the internal ones would work fine, hardware designers do weird things) and thus might need to disable the internal ones (double pulls are not great).
* generally drive-strength doesn't belong in the SoC file but should be in the board file. Different boards with different layouts might need different drive strengths, right?
If you remove those two things, I guess there's not actually much left in the SoC dtsi file so I guess move these all to the board file? That seems to be what we ended up with in "
qrb5165-rb5.dts" / "sm8250.dtsi" which is an example of a board using the new style of pinctrl for devicetree.Quoted 16 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +16
-0+ }; + + sdc1_off: sdc1-off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data {arch/arm64/boot/dts/qcom/sc7280.dtsi line 537
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arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + };No need for a sleep state for the rclk since it's the same as the active state, right? NOTE: one way to handle this would be to define one node per pingroup and thus do something like:
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk>;I do wish we could avoid having to duplicate the "bias" in every board file. Hrm, I wonder if this could be made simpler by actually putting the "sleep" states in the
sc7180.dtsifile (not the board file) and using "bias-bus-hold" to avoid it being board specific?Thus (assuming it works), the total summary would be:
1. Board dts file fully defines "
sdc1_clk", "sdc1_cmd", "sdc1_data", "sdc1_rclk", specifying whatever bias and drive strength needed for the board.2. SoC dtsi fully defines "
sdc1_clk_sleep", "sdc1_cmd_sleep", "sdc1_data_sleep", "sdc1_rclk_sleep", specifying drive-strength of 2 (for outputs) and "bias-bus-hold" which is OK for all board.Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +12
-0+ + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>;arch/arm64/boot/dts/qcom/sc7280.dtsi line 559
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arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio91";NOTE: even if we find some reason to keep some of the pinctrl in the SoC dtsi file, the card detect almost certainly needs to move _fully_ to the board dts file. Different boards could use a different card detect pin.
arch/arm64/boot/dts/qcom/sc7280.dtsi line 561
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arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0+ bias-pull-up; + drive-strength = <2>;Drive strength isn't needed for input pins. Please remove.
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arch/arm64/boot/dts/qcom/sc7280.dtsi +17
-0+ }; + }; + + sdc2_off: sdc2-off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data {arch/arm64/boot/dts/qcom/sc7280.dtsi line 588
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arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio91"; + bias-pull-up; + drive-strength = <2>; + };There's definitely no need for a separate sleep state for the CD line.
-Doug
Hi,
Quoted 11 lines · Veerabhadrarao Badiganti
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arch/arm64/boot/dts/qcom/sc7280.dtsi line 327
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arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo";I'm curious: why is the "xo" clock needed here but not for sc7180?
Actually its needed even for sc7180. We are making use of this clock in
msm_init_cm_dll()
The default PoR value is also same as calculated value for HS200/HS400/SDR104 modes.
But just not to rely on default register values we need this entry.
Can you post a patch for sc7180?
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arch/arm64/boot/dts/qcom/sc7280.dtsi line 416
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arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ bus-width = <4>; + + no-mmc; + no-sdio;Similar question to above: why exactly would mmc not work? Are you saying that if someone hooked this up to a full sized SD card slot and placed an MMC card into the slot that it wouldn't work? Similar question about SDIO. If someone placed an external SDIO card into your slot, would it not work?
As mentioned above, its just to optimize SDcard scan time a little.
OK. ...but while the eMMC one can make sense since the eMMC is soldered down (but in the board dts file, not in the SoC dtsi file) I think you should just remove these for SD card because:
1. Even if only a uSD slot is exposed it's still _possible_ for someone to insert a card that uses MMC or SDIO signaling. If nothing else I have a (probably non-compliant) adapter that plugs into a uSD slot and provides a full sided SD slot. I could plug an MMC card or SDIO card in.
2. Presumably the SD card scan time optimization is tiny.
-Doug
Quoted 9 lines · Doug Anderson
Hi,
Quoted 5 lines · Veerabhadrarao Badiganti
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arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo";
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I'm curious: why is the "xo" clock needed here but not for sc7180?
Actually its needed even for sc7180. We are making use of this clock in
msm_init_cm_dll()
The default PoR value is also same as calculated value for HS200/HS400/SDR104 modes.
But just not to rely on default register values we need this entry.Can you post a patch for sc7180?
sure will post a patch for sc7180.
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arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ bus-width = <4>; + + no-mmc; + no-sdio;Quoted 7 lines
Quoted 6 lines
Similar question to above: why exactly would mmc not work? Are you saying that if someone hooked this up to a full sized SD card slot and placed an MMC card into the slot that it wouldn't work? Similar question about SDIO. If someone placed an external SDIO card into your slot, would it not work?
As mentioned above, its just to optimize SDcard scan time a little.
OK. ...but while the eMMC one can make sense since the eMMC is soldered down (but in the board dts file, not in the SoC dtsi file) I think you should just remove these for SD card because:
Quoted 8 lines
1. Even if only a uSD slot is exposed it's still _possible_ for someone to insert a card that uses MMC or SDIO signaling. If nothing else I have a (probably non-compliant) adapter that plugs into a uSD slot and provides a full sided SD slot. I could plug an MMC card or SDIO card in.
2. Presumably the SD card scan time optimization is tiny.
sure will remove these for SD card and will move eMMC flags(no-sd and no-sdio) to board dts file.
Quoted 2 lines
-Doug
Quoted 45 lines · Veerabhadrarao Badiganti
Quoted 44 lines · Doug Anderson
Hi,
Quoted 40 lines · Shaik Sajida Bhanu
Add nodes for eMMC and SD card on sc7280.
Signed-off-by Shaik Sajida Bhanu <[email protected]>---
This change is depends on the below patch series:
https://lore.kernel.org/patchwork/project/lkml/list/?series=488871
https://lore.kernel.org/patchwork/project/lkml/list/?series=489530
https://lore.kernel.org/patchwork/project/lkml/list/?series=488429Changes since V1:
- Moved SDHC nodes as suggested by Bjorn Andersson.
- Dropped "pinconf-" prefix as suggested by Bjorn Andersson.
- Removed extra newlines as suggested by Konrad Dybcio.
- Changed sd-cd pin to bias-pull-up insdc2_offas suggested
by
Veerabhadrarao Badiganti.
- Added bandwidth votes for eMMC and SD card.--- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 25 ++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 213 ++++++++++++++++++++++++++++++++ 2 files changed, 238 insertions(+)arch/arm64/boot/dts/qcom/sc7280-idp.dts +1
-0@@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Qualcomm Technologies, Inc. sc7280 IDP platform";@@ -242,6 +243,30 @@ status = "okay"; };
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arch/arm64/boot/dts/qcom/sc7280-idp.dts line 247
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arch/arm64/boot/dts/qcom/sc7280-idp.dts +2
-0+&sdhc_1 { + status = "okay";When I apply your patch I find that your sort order is wrong. "s" comes before "u" and after "q" in the alphabet so "
sdhc_1" and "sdhc_2" should sort_after"qupv3_id_0" and before "uart5"
sure will change the order.
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arch/arm64/boot/dts/qcom/sc7280-idp.dts +15
-0+ pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default","sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; +
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arch/arm64/boot/dts/qcom/sc7280-idp.dts line 267
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arch/arm64/boot/dts/qcom/sc7280-idp.dts +4
-0+ vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;Where is the pinctrl for the card detect? Oh, I see it's in "
sdc2_on". Probably would be good to break it out since this is board-specific. See below.
okay
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arch/arm64/boot/dts/qcom/sc7280-idp.dts +2
-0+}; + /* PINCTRL - additions to nodes defined in sc7280.dtsi */ &qup_uart5_default {arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0@@ -20,6 +20,11 @@ chosen { }; + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock";arch/arm64/boot/dts/qcom/sc7280.dtsi line 314
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arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0@@ -305,6 +310,64 @@ #power-domain-cells = <1>; }; + sdhc_1: sdhci@7c4000 { + compatible = "qcom,sdhci-msm-v5";Please make the compatible:
compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";...and add to the bindings. It should be a trivial bindings patch so not too much trouble.
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NOTE: even though the "qcom,sc7280-sdhci" should be in the bindings and here you _shouldn't_ be adding any code for it. Just let the fallback compatible string ("qcom,sdhci-msm-v5") do its magic. Adding the sc7280 specific version is more of a "just in case we need it later" type thing.
sure
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arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ reg = <0 0x7c4000 0 0x1000>, + <0 0x7c5000 0 0x1000>; + reg-names = "hc", "cqhci"; + + iommus = <&apps_smmu 0xC0 0x0>;arch/arm64/boot/dts/qcom/sc7280.dtsi line 327
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arch/arm64/boot/dts/qcom/sc7280.dtsi +8
-0+ interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo";I'm curious: why is the "xo" clock needed here but not for sc7180?
Quoted 24 lines
Actually its needed even for sc7180. We are making use of this clock in
msm_init_cm_dll()
The default PoR value is also same as calculated value for HS200/HS400/SDR104 modes.
But just not to rely on default register values we need this entry.Quoted 18 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 335
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arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0+ interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0&cnoc2
SLAVE_SDCC_10>;arch/arm64/boot/dts/qcom/sc7280.dtsi +6
-0+ interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + bus-width = <8>; + non-removable;This was actually a problem on sc7180 too, but you probably don't want "non-removable" in the SoC file. Board files really should be adding this. Though the SoC might be designed with the idea that this would be used for a non-removable eMMC card I don't know why it wouldn't be possible for someone to hook this up to an external slot and use a GPIO somewhere as a card detect.
sure will move
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arch/arm64/boot/dts/qcom/sc7280.dtsi line 338
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arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ supports-cqe; + no-sd; + no-sdio;Does the port really not support SD / SDIO, or are you adding these two properties just because on your reference board it's not hooked up to SD/SDIO? What exactly makes it impossible to use SD/SDIO on this port?
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By having this, we can optimize emmc device scan time. Driver wont issue SDIO & SDcards specific commands while scanning the device.Its little optimization.
I think board specific dt is right place.Quoted 2 lines
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+ max-frequency = <192000000>;
Why do you need to specify this?
This helps to avoid lower speed modes running in high clock rate, and As Veerabhadrarao Badiganti mentioned
This will align clock requests between mmc core layer and sdhci-msm platform driver. Say, for HS200/HS400 modes of eMMC, mmc-core layer tries to set clock at 200Mhz, whereas sdhci-msm expects 192Mhz for these modes. So we have to rely on clock driver floor/ceil values. By having this property, mmc-core layer itself request for 192Mhz.
Same is for SD card SDR104 mode, core layer expects clock at 208Mhz whereas sdhci-msm can max operate only at 202Mhz. By having this property, core layer requests only for 202Mhz for SDR104 mode.
BTW, this helps only for max possible speed modes.
In case of lower-speed modes (for DDR52) we still need to rely on clock floor rounding.
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arch/arm64/boot/dts/qcom/sc7280.dtsi line 343
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arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0+ qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>;These magic hex values really have no place being in dts which should have things expressed at a higher level. ...but I guess that ship has sailed and this is in the bindings so I guess we're stuck with them, so I guess they're fine.
sure
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arch/arm64/boot/dts/qcom/sc7280.dtsi +12
-0+ mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + status = "disabled"; + + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64Quoted 7 lines
<100000000>;
+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1200000
76000>;
+ opp-avg-kBps = <1200000
50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
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b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
We calculated bus votes values for both sc7180 and sc7280 with ICB tool, above mentioned values we got for sc7280.
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arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ }; + + opp-384000000 { + opp-hz = /bits/ 64<384000000>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000
1600000>;
+ opp-avg-kBps = <6000000
300000>;
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These opp numbers are also quite different than sc7180
We calculated bus votes values for both sc7180 and sc7280 with ICB tool, above mentioned values we got for sc7280.
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arch/arm64/boot/dts/qcom/sc7280.dtsi +19
-0+ }; + }; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>;@@ -328,6 +391,54 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + iommus = <&apps_smmu 0x100 0x0>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0&cnoc2
SLAVE_SDCC_20>;arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + bus-width = <4>;Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 416
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arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ + no-mmc; + no-sdio;Similar question to above: why exactly would mmc not work? Are you saying that if someone hooked this up to a full sized SD card slot and placed an MMC card into the slot that it wouldn't work? Similar question about SDIO. If someone placed an external SDIO card into your slot, would it not work?
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As mentioned above, its just to optimize SDcard scan time a little.
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+ max-frequency = <202000000>;
Not needed?
yes it is needed same as above
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arch/arm64/boot/dts/qcom/sc7280.dtsi +7
-0+ + qcom,dll-config = <0x0007642c>; + + status = "disabled"; + + sdhc2_opp_table: sdhc2-opp-table { + compatible ="operating-points-v2";
arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ + opp-100000000 { + opp-hz =/bits/ 64<100000000>;
+ required-opps =
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arch/arm64/boot/dts/qcom/sc7280.dtsi line 433
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<
&rpmhpd_opp_low_svs>;
+ opp-peak-kBps =
<1200000 76000>;
+ opp-avg-kBps =
<1200000 50000>;arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0+ }; + opp-202000000 {Blank line between the OPPs?
sure
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+ opp-hz = /bits/ 64
<202000000>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ opp-peak-kBps =
<3500000 1200000>;
+ opp-avg-kBps =
<5000000 100000>;
+ };Similar questions about why the OPPs are so vastly different from sc7180.
We calculated bus votes values for both sc7180 and sc7280 with ICB tool, above mentioned values we got for sc7280.
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arch/arm64/boot/dts/qcom/sc7280.dtsi +17
-0+ }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;@@ -374,6 +485,108 @@ pins = "gpio46", "gpio47"; function = "qup13"; }; + + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; +arch/arm64/boot/dts/qcom/sc7280.dtsi line 511
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arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + };* generally "bias" doesn't belong in the SoC file but instead should be in the board file. Some boards might have external pulls (even if the internal ones would work fine, hardware designers do weird things) and thus might need to disable the internal ones (double pulls are not great).
* generally drive-strength doesn't belong in the SoC file but should be in the board file. Different boards with different layouts might need different drive strengths, right?
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If you remove those two things, I guess there's not actually much left in the SoC dtsi file so I guess move these all to the board file? That seems to be what we ended up with in "
qrb5165-rb5.dts" / "sm8250.dtsi" which is an example of a board using the new style of pinctrl for devicetree.
sure
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arch/arm64/boot/dts/qcom/sc7280.dtsi +16
-0+ }; + + sdc1_off: sdc1-off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data {arch/arm64/boot/dts/qcom/sc7280.dtsi line 537
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arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + };No need for a sleep state for the rclk since it's the same as the active state, right? NOTE: one way to handle this would be to define one node per pingroup and thus do something like:
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk>;I do wish we could avoid having to duplicate the "bias" in every board file. Hrm, I wonder if this could be made simpler by actually putting the "sleep" states in the
sc7180.dtsifile (not the board file) and using "bias-bus-hold" to avoid it being board specific?Thus (assuming it works), the total summary would be:
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1. Board dts file fully defines "
sdc1_clk", "sdc1_cmd", "sdc1_data", "sdc1_rclk", specifying whatever bias and drive strength needed for the board.2. SoC dtsi fully defines "
sdc1_clk_sleep", "sdc1_cmd_sleep", "sdc1_data_sleep", "sdc1_rclk_sleep", specifying drive-strength of 2 (for outputs) and "bias-bus-hold" which is OK for all board.
sure
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arch/arm64/boot/dts/qcom/sc7280.dtsi +12
-0+ + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>;arch/arm64/boot/dts/qcom/sc7280.dtsi line 559
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arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio91";NOTE: even if we find some reason to keep some of the pinctrl in the SoC dtsi file, the card detect almost certainly needs to move _fully_ to the board dts file. Different boards could use a different card detect pin.
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arch/arm64/boot/dts/qcom/sc7280.dtsi line 561
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arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0+ bias-pull-up; + drive-strength = <2>;Drive strength isn't needed for input pins. Please remove.
sure
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arch/arm64/boot/dts/qcom/sc7280.dtsi +20
-0+ }; + }; + + sdc2_off: sdc2-off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>;
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arch/arm64/boot/dts/qcom/sc7280.dtsi line 562
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arch/arm64/boot/dts/qcom/sc7280.dtsi +7
-0+ }; + + sd-cd { + pins = "gpio91"; + bias-pull-up; + drive-strength = <2>; + };There's definitely no need for a separate sleep state for the CD line.
okay
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-Doug
Hi,
Quoted 5 lines · On Thu, Mar 25, 2021 at 11:57 PM <[email protected]> wrote:
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+ max-frequency = <192000000>;
Why do you need to specify this?
This helps to avoid lower speed modes running in high clock rate, and As Veerabhadrarao Badiganti mentioned
Just to be clear, both Stephen and I agree that you should remove "max-frequency" here (see previous discussion). Bjorn is, of course, the file decision maker. However, unless he says "yeah, totally keep it in" I'd suggest dropping it from the next version.
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+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1200000
76000>;
+ opp-avg-kBps = <1200000
50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
Quoted 8 lines
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c) The numbers are essentially random and don't really matter.
Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
We calculated bus votes values for both sc7180 and sc7280 with ICB tool, above mentioned values we got for sc7280.
I don't know what an ICB tool is. Please clarify.
Also: just because a tool spits out numbers that doesn't mean it's correct. Presumably the tool could be wrong or incorrectly configured. We need to understand why these numbers are different.
-Doug
Quoted 5 lines · Doug Anderson
Hi,
Quoted 2 lines · On Thu, Mar 25, 2021 at 11:57 PM <[email protected]> wrote:
Quoted 2 lines
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+ max-frequency = <192000000>;
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Why do you need to specify this?
This helps to avoid lower speed modes running in high clock rate, and As Veerabhadrarao Badiganti mentioned
Just to be clear, both Stephen and I agree that you should remove "max-frequency" here (see previous discussion). Bjorn is, of course, the file decision maker. However, unless he says "yeah, totally keep it in" I'd suggest dropping it from the next version.
sure will drop in next version.
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+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1200000
76000>;
+ opp-avg-kBps = <1200000
50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
Quoted 9 lines
Quoted 2 lines
We calculated bus votes values for both sc7180 and sc7280 with ICB tool, above mentioned values we got for sc7280.
I don't know what an ICB tool is. Please clarify.
Also: just because a tool spits out numbers that doesn't mean it's correct. Presumably the tool could be wrong or incorrectly configured. We need to understand why these numbers are different.
we checked with ICB tool team on this they conformed as Rennell & Kodiak are different chipsets, we might see delta in ib/ab values due to delta in scaling factors.
Quoted 1 line
-Doug
Hi,
Quoted 26 lines · On Tue, Apr 13, 2021 at 3:59 AM <[email protected]> wrote:
Quoted 26 lines
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+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1200000
76000>;
+ opp-avg-kBps = <1200000
50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
Quoted 7 lines
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Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
We calculated bus votes values for both sc7180 and sc7280 with ICB tool,
above mentioned values we got for sc7280.I don't know what an ICB tool is. Please clarify.
Quoted 7 lines
Quoted 4 lines
Also: just because a tool spits out numbers that doesn't mean it's correct. Presumably the tool could be wrong or incorrectly configured. We need to understand why these numbers are different.
we checked with ICB tool team on this they conformed as Rennell & Kodiak are different chipsets,
we might see delta in ib/ab values due to delta in scaling factors.
...but these numbers are in kbps, aren't they? As I understand it these aren't supposed to be random numbers spit out by a tool but are supposed to be understandable by how much bandwidth an IP block (like MMC) needs from the busses it's connected to. Since the MMC IP block on sc7180 and sc7280 is roughly the same there shouldn't be a big difference in numbers.
Something smells wrong.
Adding a few people who understand interconnects better than I do, though.
-Doug
Hi,
Quoted 36 lines · Doug Anderson
Hi,
Quoted 33 lines · On Tue, Apr 13, 2021 at 3:59 AM <[email protected]> wrote:
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+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1200000
76000>;
+ opp-avg-kBps = <1200000
50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
Quoted 7 lines
Quoted 3 lines
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Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
We calculated bus votes values for both sc7180 and sc7280 with ICB tool,
above mentioned values we got for sc7280.Quoted 6 lines
I don't know what an ICB tool is. Please clarify.
Also: just because a tool spits out numbers that doesn't mean it's correct. Presumably the tool could be wrong or incorrectly configured. We need to understand why these numbers are different.
we checked with ICB tool team on this they conformed as Rennell & Kodiak are different chipsets,
we might see delta in ib/ab values due to delta in scaling factors.
If the scaling factor is different, maybe this should be reflected in the BCM data, where we have the following:
@vote_scale: scaling factor for vote_x and vote_y
This is 1000 by default, but maybe we should set it to some different value for some of the BCMs?
I'm adding Odelu, who is more familiar with this platform.
Quoted 8 lines
...but these numbers are in kbps, aren't they? As I understand it these aren't supposed to be random numbers spit out by a tool but are supposed to be understandable by how much bandwidth an IP block (like MMC) needs from the busses it's connected to. Since the MMC IP block on sc7180 and sc7280 is roughly the same there shouldn't be a big difference in numbers.
Quoted 4 lines
Something smells wrong.
Adding a few people who understand interconnects better than I do, though.
Thanks!
Georgi
Quoted 44 lines · Doug Anderson
Hi,
Quoted 26 lines · On Tue, Apr 13, 2021 at 3:59 AM <[email protected]> wrote:
Quoted 26 lines
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+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1200000
76000>;
+ opp-avg-kBps = <1200000
50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
Quoted 7 lines
Quoted 3 lines
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Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
We calculated bus votes values for both sc7180 and sc7280 with ICB tool,
above mentioned values we got for sc7280.I don't know what an ICB tool is. Please clarify.
Quoted 7 lines
Quoted 4 lines
Also: just because a tool spits out numbers that doesn't mean it's correct. Presumably the tool could be wrong or incorrectly configured. We need to understand why these numbers are different.
we checked with ICB tool team on this they conformed as Rennell & Kodiak are different chipsets,
we might see delta in ib/ab values due to delta in scaling factors....but these numbers are in kbps, aren't they? As I understand it these aren't supposed to be random numbers spit out by a tool but are supposed to be understandable by how much bandwidth an IP block (like MMC) needs from the busses it's connected to. Since the MMC IP block on sc7180 and sc7280 is roughly the same there shouldn't be a big difference in numbers.
Quoted 4 lines
Something smells wrong.
Adding a few people who understand interconnects better than I do, though.
ICB team has re-checked the Rennell ICB tool and they confirmed that some configs were wrong in Rennell ICB tool and they corrected it.With the new updated Rennell ICB tool below are the values :
Rennell LC:(Sc7180)
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <5400000 490000>;
opp-avg-kBps = <6600000 300000>;
};And now, these values are near to Kodaik LC values:
Kodaik LC:(SC7280)
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <5400000 399000>;
opp-avg-kBps = <6000000 300000>;
};Quoted 1 line
-Doug
Hi,
Quoted 70 lines · On Tue, Apr 20, 2021 at 10:21 AM <[email protected]> wrote:
Quoted 45 lines · Doug Anderson
Hi,
Quoted 26 lines · On Tue, Apr 13, 2021 at 3:59 AM <[email protected]> wrote:
Quoted 26 lines
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+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1200000
76000>;
+ opp-avg-kBps = <1200000
50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
Quoted 7 lines
Quoted 3 lines
Quoted 3 lines
Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
We calculated bus votes values for both sc7180 and sc7280 with ICB tool,
above mentioned values we got for sc7280.I don't know what an ICB tool is. Please clarify.
Quoted 8 lines
Quoted 4 lines
Also: just because a tool spits out numbers that doesn't mean it's correct. Presumably the tool could be wrong or incorrectly configured. We need to understand why these numbers are different.
we checked with ICB tool team on this they conformed as Rennell & Kodiak
are different chipsets,
we might see delta in ib/ab values due to delta in scaling factors....but these numbers are in kbps, aren't they? As I understand it these aren't supposed to be random numbers spit out by a tool but are supposed to be understandable by how much bandwidth an IP block (like MMC) needs from the busses it's connected to. Since the MMC IP block on sc7180 and sc7280 is roughly the same there shouldn't be a big difference in numbers.
Quoted 5 lines
Something smells wrong.
Adding a few people who understand interconnects better than I do, though.
ICB team has re-checked the Rennell ICB tool and they confirmed that some configs were wrong in Rennell ICB tool and they corrected it.With the new updated Rennell ICB tool below are the values :
Rennell LC:(Sc7180)
opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 490000>; opp-avg-kBps = <6600000 300000>; };And now, these values are near to Kodaik LC values:
Quoted 8 lines
Kodaik LC:(SC7280)
opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 399000>; opp-avg-kBps = <6000000 300000>; };
This still isn't making sense to me.
* sc7180 and sc7280 are running at the same speed. I'm glad the numbers are closer now, but I would have thought they'd be exactly the same.
* Aren't these supposed to be sensible? This is eMMC that does max transfer rates of 400 megabytes / second to the external device. You have bandwidths listed here of 5,400,000 kBps = 5,400,000 kilobytes / second = 5400 megabytes / second. I can imagine there being some overhead where an internal bus might need to be faster but that seems excessive. This is 13.5x!
* I can't see how it can make sense that "average" values are higher than "peak" values.
It still feels like there's a misconfiguration somewhere.
-Doug
Quoted 88 lines · Doug Anderson
Hi,
Quoted 70 lines · On Tue, Apr 20, 2021 at 10:21 AM <[email protected]> wrote:
Quoted 45 lines · Doug Anderson
Hi,
Quoted 26 lines · On Tue, Apr 13, 2021 at 3:59 AM <[email protected]> wrote:
Quoted 26 lines
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+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1200000
76000>;
+ opp-avg-kBps = <1200000
50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
Quoted 7 lines
Quoted 3 lines
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Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
We calculated bus votes values for both sc7180 and sc7280 with ICB tool,
above mentioned values we got for sc7280.I don't know what an ICB tool is. Please clarify.
Quoted 8 lines
Quoted 4 lines
Also: just because a tool spits out numbers that doesn't mean it's correct. Presumably the tool could be wrong or incorrectly configured. We need to understand why these numbers are different.
we checked with ICB tool team on this they conformed as Rennell & Kodiak
are different chipsets,
we might see delta in ib/ab values due to delta in scaling factors....but these numbers are in kbps, aren't they? As I understand it these aren't supposed to be random numbers spit out by a tool but are supposed to be understandable by how much bandwidth an IP block (like MMC) needs from the busses it's connected to. Since the MMC IP block on sc7180 and sc7280 is roughly the same there shouldn't be a big difference in numbers.
Quoted 5 lines
Something smells wrong.
Adding a few people who understand interconnects better than I do, though.
ICB team has re-checked the Rennell ICB tool and they confirmed that some configs were wrong in Rennell ICB tool and they corrected it.With the new updated Rennell ICB tool below are the values :
Rennell LC:(Sc7180)
opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 490000>; opp-avg-kBps = <6600000 300000>; };And now, these values are near to Kodaik LC values:
Quoted 8 lines
Kodaik LC:(SC7280)
opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 399000>; opp-avg-kBps = <6000000 300000>; };This still isn't making sense to me.
* sc7180 and sc7280 are running at the same speed. I'm glad the numbers are closer now, but I would have thought they'd be exactly the same.
Quoted 7 lines
* Aren't these supposed to be sensible? This is eMMC that does max transfer rates of 400 megabytes / second to the external device. You have bandwidths listed here of 5,400,000 kBps = 5,400,000 kilobytes / second = 5400 megabytes / second. I can imagine there being some overhead where an internal bus might need to be faster but that seems excessive. This is 13.5x!
These numbers are not related to SDCC bandwidth, these are the values needed for the NOC's to run in nominal voltage corners (internal to hardware) and thus it helps SDCC to run in nominal to get required through put (384MBps).So above calculation mentioned by you is not applicable here.
Quoted 2 lines
* I can't see how it can make sense that "average" values are higher than "peak" values.
Here actual peak = peak number * 2
actual average = average number
and this multiplication is taken care by ICC driver, so technically actual peak is still high than average.
Quoted 4 lines
It still feels like there's a misconfiguration somewhere.
-Doug
Hi,
Quoted 98 lines · On Wed, Apr 28, 2021 at 3:47 AM <[email protected]> wrote:
Quoted 88 lines · Doug Anderson
Hi,
Quoted 70 lines · On Tue, Apr 20, 2021 at 10:21 AM <[email protected]> wrote:
Quoted 45 lines · Doug Anderson
Hi,
Quoted 26 lines · On Tue, Apr 13, 2021 at 3:59 AM <[email protected]> wrote:
Quoted 26 lines
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+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1200000
76000>;
+ opp-avg-kBps = <1200000
50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
Quoted 7 lines
Quoted 3 lines
Quoted 3 lines
Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
We calculated bus votes values for both sc7180 and sc7280 with ICB tool,
above mentioned values we got for sc7280.I don't know what an ICB tool is. Please clarify.
Quoted 8 lines
Quoted 4 lines
Also: just because a tool spits out numbers that doesn't mean it's correct. Presumably the tool could be wrong or incorrectly configured. We need to understand why these numbers are different.
we checked with ICB tool team on this they conformed as Rennell & Kodiak
are different chipsets,
we might see delta in ib/ab values due to delta in scaling factors....but these numbers are in kbps, aren't they? As I understand it these aren't supposed to be random numbers spit out by a tool but are supposed to be understandable by how much bandwidth an IP block (like MMC) needs from the busses it's connected to. Since the MMC IP block on sc7180 and sc7280 is roughly the same there shouldn't be a big difference in numbers.
Quoted 5 lines
Something smells wrong.
Adding a few people who understand interconnects better than I do, though.
ICB team has re-checked the Rennell ICB tool and they confirmed that some configs were wrong in Rennell ICB tool and they corrected it.With the new updated Rennell ICB tool below are the values :
Rennell LC:(Sc7180)
opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 490000>; opp-avg-kBps = <6600000 300000>; };And now, these values are near to Kodaik LC values:
Quoted 8 lines
Kodaik LC:(SC7280)
opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 399000>; opp-avg-kBps = <6000000 300000>; };This still isn't making sense to me.
* sc7180 and sc7280 are running at the same speed. I'm glad the numbers are closer now, but I would have thought they'd be exactly the same.
Quoted 7 lines
* Aren't these supposed to be sensible? This is eMMC that does max transfer rates of 400 megabytes / second to the external device. You have bandwidths listed here of 5,400,000 kBps = 5,400,000 kilobytes / second = 5400 megabytes / second. I can imagine there being some overhead where an internal bus might need to be faster but that seems excessive. This is 13.5x!
Quoted 5 lines
These numbers are not related to SDCC bandwidth, these are the values needed for the NOC's to run in nominal voltage corners (internal to hardware) and
thus it helps SDCC to run in nominal to get required through put (384MBps).So above calculation mentioned by you is not applicable here.
OK. I guess if everyone else understands this and it's just me that doesn't then I won't stand in the way. In general, though, the device tree is supposed to be describing the hardware in a way that makes sense on its own. It's not a place to just dump in magic numbers. These numbers must be somehow related to the transfer rate of the SD card since otherwise they wouldn't scale up with faster card clocks. Given that these numbers are expressed in "kBps" (since you're storing them in a property that has "kBps" in the name), I would expect that these numbers are expressing some type of bandwidth. I still haven't really understood why you have to scale some bandwidth at over 10x the card clock speed.
Said another way: you're saying that you need these numbers because they make a whole bunch of math work out. I'm saying that these aren't just supposed to be magic numbers. They're supposed to make sense on their own and you should be able to describe to me how you arrived at these numbers in a way that I could do the math on my own. Saying "we plugged this into some program and it spit out these numbers" isn't good enough.
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* I can't see how it can make sense that "average" values are higher than "peak" values.
Here actual peak = peak number * 2
actual average = average numberand this multiplication is taken care by ICC driver, so technically actual peak is still high than average.
Sorry, but that is really counter-intuitive. Georgi: is that how this is normally expected to work?
-Doug
Quoted 119 lines · Doug Anderson
Hi,
Quoted 98 lines · On Wed, Apr 28, 2021 at 3:47 AM <[email protected]> wrote:
Quoted 88 lines · Doug Anderson
Hi,
Quoted 70 lines · On Tue, Apr 20, 2021 at 10:21 AM <[email protected]> wrote:
Quoted 45 lines · Doug Anderson
Hi,
Quoted 26 lines · On Tue, Apr 13, 2021 at 3:59 AM <[email protected]> wrote:
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+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1200000
76000>;
+ opp-avg-kBps = <1200000
50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
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Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
We calculated bus votes values for both sc7180 and sc7280 with ICB tool,
above mentioned values we got for sc7280.I don't know what an ICB tool is. Please clarify.
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Also: just because a tool spits out numbers that doesn't mean it's correct. Presumably the tool could be wrong or incorrectly configured. We need to understand why these numbers are different.
we checked with ICB tool team on this they conformed as Rennell & Kodiak
are different chipsets,
we might see delta in ib/ab values due to delta in scaling factors....but these numbers are in kbps, aren't they? As I understand it these aren't supposed to be random numbers spit out by a tool but are supposed to be understandable by how much bandwidth an IP block (like MMC) needs from the busses it's connected to. Since the MMC IP block on sc7180 and sc7280 is roughly the same there shouldn't be a big difference in numbers.
Quoted 5 lines
Something smells wrong.
Adding a few people who understand interconnects better than I do, though.
ICB team has re-checked the Rennell ICB tool and they confirmed that some configs were wrong in Rennell ICB tool and they corrected it.With the new updated Rennell ICB tool below are the values :
Rennell LC:(Sc7180)
opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 490000>; opp-avg-kBps = <6600000 300000>; };And now, these values are near to Kodaik LC values:
Quoted 8 lines
Kodaik LC:(SC7280)
opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 399000>; opp-avg-kBps = <6000000 300000>; };This still isn't making sense to me.
* sc7180 and sc7280 are running at the same speed. I'm glad the numbers are closer now, but I would have thought they'd be exactly the same.
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* Aren't these supposed to be sensible? This is eMMC that does max transfer rates of 400 megabytes / second to the external device. You have bandwidths listed here of 5,400,000 kBps = 5,400,000 kilobytes / second = 5400 megabytes / second. I can imagine there being some overhead where an internal bus might need to be faster but that seems excessive. This is 13.5x!
Quoted 5 lines
These numbers are not related to SDCC bandwidth, these are the values needed for the NOC's to run in nominal voltage corners (internal to hardware) and
thus it helps SDCC to run in nominal to get required through put (384MBps).So above calculation mentioned by you is not applicable here.OK. I guess if everyone else understands this and it's just me that doesn't then I won't stand in the way. In general, though, the device tree is supposed to be describing the hardware in a way that makes sense on its own. It's not a place to just dump in magic numbers. These numbers must be somehow related to the transfer rate of the SD card since otherwise they wouldn't scale up with faster card clocks. Given that these numbers are expressed in "kBps" (since you're storing them in a property that has "kBps" in the name), I would expect that these numbers are expressing some type of bandwidth. I still haven't really understood why you have to scale some bandwidth at over 10x the card clock speed.
Quoted 7 lines
Said another way: you're saying that you need these numbers because they make a whole bunch of math work out. I'm saying that these aren't just supposed to be magic numbers. They're supposed to make sense on their own and you should be able to describe to me how you arrived at these numbers in a way that I could do the math on my own. Saying "we plugged this into some program and it spit out these numbers" isn't good enough.
Agree.
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* I can't see how it can make sense that "average" values are higher than "peak" values.
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Here actual peak = peak number * 2
actual average = average numberand this multiplication is taken care by ICC driver, so technically actual peak is still high than average.
Sorry, but that is really counter-intuitive. Georgi: is that how this is normally expected to work?
Average bandwidth being higher than peak does not make sense to me. The numbers in DT should reflect the real bandwidth that is being requested. If some links between nodes consist of multiple channels, or there is anything specific to the topology or the hardware platform (scaling factors, buswidth, etc), this should be handled in the interconnect provider driver. The goal is to use bandwidth values and not magic numbers.
Thanks,
Georgi
Quoted 130 lines · Georgi Djakov
Quoted 121 lines · Doug Anderson
Hi,
Quoted 100 lines · On Wed, Apr 28, 2021 at 3:47 AM <[email protected]> wrote:
Quoted 90 lines · Doug Anderson
Hi,
Quoted 72 lines · On Tue, Apr 20, 2021 at 10:21 AM <[email protected]> wrote:
Quoted 47 lines · Doug Anderson
Hi,
Quoted 28 lines · On Tue, Apr 13, 2021 at 3:59 AM <[email protected]> wrote:
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+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps =
<1200000
76000>;
+ opp-avg-kBps =
<1200000
50000>;Why are the kBps numbers so vastly different than the ones on sc7180 for the same OPP point. That implies:
a) sc7180 is wrong.
b) This patch is wrong.
c) The numbers are essentially random and don't really matter.
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Can you identify which of a), b), or c) is correct, or propose an alternate explanation of the difference?
We calculated bus votes values for both sc7180 and sc7280 with ICB tool,
above mentioned values we got for sc7280.I don't know what an ICB tool is. Please clarify.
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Also: just because a tool spits out numbers that doesn't mean it's correct. Presumably the tool could be wrong or incorrectly configured. We need to understand why these numbers are different.
we checked with ICB tool team on this they conformed as Rennell & Kodiak
are different chipsets,
we might see delta in ib/ab values due to delta in scaling factors....but these numbers are in kbps, aren't they? As I understand it these aren't supposed to be random numbers spit out by a tool but are supposed to be understandable by how much bandwidth an IP block (like MMC) needs from the busses it's connected to. Since the MMC IP block on sc7180 and sc7280 is roughly the same there shouldn't be a big difference in numbers.
Quoted 5 lines
Something smells wrong.
Adding a few people who understand interconnects better than I do, though.
ICB team has re-checked the Rennell ICB tool and they confirmed that some configs were wrong in Rennell ICB tool and they corrected it.With the new updated Rennell ICB tool below are the values :
Rennell LC:(Sc7180)
opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 490000>; opp-avg-kBps = <6600000 300000>; };And now, these values are near to Kodaik LC values:
Quoted 8 lines
Kodaik LC:(SC7280)
opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 399000>; opp-avg-kBps = <6000000 300000>; };This still isn't making sense to me.
* sc7180 and sc7280 are running at the same speed. I'm glad the numbers are closer now, but I would have thought they'd be exactly the same.
Quoted 7 lines
* Aren't these supposed to be sensible? This is eMMC that does max transfer rates of 400 megabytes / second to the external device. You have bandwidths listed here of 5,400,000 kBps = 5,400,000 kilobytes / second = 5400 megabytes / second. I can imagine there being some overhead where an internal bus might need to be faster but that seems excessive. This is 13.5x!
Quoted 5 lines
These numbers are not related to SDCC bandwidth, these are the values needed for the NOC's to run in nominal voltage corners (internal to hardware) and
thus it helps SDCC to run in nominal to get required through put (384MBps).So above calculation mentioned by you is not applicable here.OK. I guess if everyone else understands this and it's just me that doesn't then I won't stand in the way. In general, though, the device tree is supposed to be describing the hardware in a way that makes sense on its own. It's not a place to just dump in magic numbers. These numbers must be somehow related to the transfer rate of the SD card since otherwise they wouldn't scale up with faster card clocks. Given that these numbers are expressed in "kBps" (since you're storing them in a property that has "kBps" in the name), I would expect that these numbers are expressing some type of bandwidth. I still haven't really understood why you have to scale some bandwidth at over 10x the card clock speed.
Quoted 7 lines
Said another way: you're saying that you need these numbers because they make a whole bunch of math work out. I'm saying that these aren't just supposed to be magic numbers. They're supposed to make sense on their own and you should be able to describe to me how you arrived at these numbers in a way that I could do the math on my own. Saying "we plugged this into some program and it spit out these numbers" isn't good enough.
Quoted 2 lines
Agree.
Peak bandwidth is an instantaneous bandwidth used as a floor vote to take care of latency (in this case for DDR). It is a mechanism to vote for floor frequency to counter latency as opposed to an actual bandwidth requirement.
So a client could say I need the clock to run @200 MHz and simply take the bus width times the frequency as the required peak bandwidth vote (peak bandwidth vote = 200 * bus_width ) and vote for it.
So, we are passing peak bandwidth votes for DDR and CNOC for nom frequencies from device tree.
SDCC clocks are running at Nom. frequenices, which are power driven by the cx rail. The same cx rail will also power driven to DDR clocks too.
So, DDR clocks can also scale upto to Nom. frequenices without any extra power drawing by the cx rail. This will helps to get optimal performance.
So, on doing the math with DDR Nom. frequency (1.3GHz) and also considering the Gerogi points [If some links between nodes consist of multiple channels,
or there is anything specific to the topology or the hardware platform (scaling factors, buswidth, etc), this should be handled in the
interconnect provider driver.] we will get values close to 5400000KBps.
same applies to CNOC config path Nom. frequency (403MHz), we will get values close to 1600000KBps.
math used :
peak bandwidth = minimum DDR * effective width; //4bytes for DDR for SC7280. average bandwidth = is the actual throughput requirement.
By considering the above points, the new b/w values looks as below.
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <5400000 1600000>;
opp-avg-kBps = <390000 0>;
};similarly for 100Mhz
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1800000 400000>;
opp-avg-kBps = <100000 0>;
};Quoted 21 lines
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* I can't see how it can make sense that "average" values are higher than "peak" values.
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Here actual peak = peak number * 2
actual average = average numberand this multiplication is taken care by ICC driver, so technically actual peak is still high than average.
Sorry, but that is really counter-intuitive. Georgi: is that how this is normally expected to work?
Average bandwidth being higher than peak does not make sense to me. The numbers in DT should reflect the real bandwidth that is being requested. If some links between nodes consist of multiple channels, or there is anything specific to the topology or the hardware platform (scaling factors, buswidth, etc), this should be handled in the interconnect provider driver. The goal is to use bandwidth values and not magic numbers.
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Thanks,
Georgi
Sure, we will update this Average bandwidth vote values.