Mainstone mmc support
PATCH 1/1 Mainstone mmc support
Hello,
Please consider this patch for inclusion.
This adds MMC and the rest of the FPGA irq definitions for the Mainstone II
Kind regards,
Armin
hw/mainstone.c +4 -0
@@ -76,6 +76,10 @@ static void mainstone_common_init(int ra } mst_irq =mst_irq_init (cpu,MST_FPGA_PHYS ,PXA2XX_PIC_GPIO_0 ); + +/* MMC/SD host */ +pxa2xx_mmci_handlers (cpu->mmc, mst_irq[MMC_IRQ ], mst_irq[MMC_IRQ ]); +smc91c111_init (&nd_table[0 ],MST_ETH_PHYS , mst_irq[ETHERNET_IRQ ]); arm_load_kernel(cpu->env, mainstone_ram, kernel_filename, kernel_cmdline,
hw/mainstone.h +14 -1
@@ -17,7 +17,20 @@#define MST_FLASH_1 0x04000000/* IRQ definitions */ -#define ETHERNET_IRQ 3 +#define MMC_IRQ 0 +#define USIM_IRQ 1 +#define USBC_IRQ 2 +#define ETHERNET_IRQ 3 +#define AC97_IRQ 4 +#define PEN_IRQ 5 +#define MSINS_IRQ 6 +#define EXBRD_IRQ 7 +#define S0_CD_IRQ 9 +#define S0_STSCHG_IRQ 10 +#define S0_IRQ 11 +#define S1_CD_IRQ 13 +#define S1_STSCHG_IRQ 14 +#define S1_IRQ 15extern qemu_irq *mst_irq_init (struct pxa2xx_state_s *cpu,uint32_t base,int irq);
Quoted 5 lines · Armin
Hello,
Please consider this patch for inclusion.
This adds MMC and the rest of the FPGA irq definitions for the Mainstone II
Why are both the write-protect and card-detect signals being connected to one input? If one of the inputs doesn't exist then just pass NULL for the parameter, and if they are supposed to be ORed or ANDed then this needs to be done explicitely.
The way it is in the patch the input will randomly take the level of one of the two signals.
Regards
Andrzej,
Quoted 4 lines · andrzej zaborowski
Quoted 2 lines · Armin
Hello,
Quoted 10 lines
Quoted 4 lines
Please consider this patch for inclusion.
This adds MMC and the rest of the FPGA irq definitions for the Mainstone II
Why are both the write-protect and card-detect signals being connected to one input? If one of the inputs doesn't exist then just pass NULL for the parameter,
The write protect does not exist so I will change it to a "NULL"
thanks,
- Armin